JPS59117668A - Time division multiplying circuit - Google Patents

Abstract

PURPOSE:To perform a high-precision multiplying operation, by preventing the output error due to the floating capacity of a switching element and the output error due to the existence of the period when two switching elements are turned on simultaneously. CONSTITUTION:An output signal (b) from a pulse width modulating circuit 1 is inputted to gates G4 and G5. A signal (c) attained by delaying the signal (b) in an inverter G2 by DELTAT2 is inputted to gates G4 and G5 through an inerter G3. A switching signal (h) impressed to switching elements AS1 and AS2 is outputted from the gate G4, and a switching signal (i) impressed to switching elements AS2 and AS3 is outputted from the gate G5. Though switching signals (h) and (i) are signals corresponding to outputs (b) and (c) of the pulse width modulating circuit 1 respectively, rise and fall timings of both signals are operated minutely, and a minute period DELTAT when both signals are in the L level together is included at all change points of both signals but the period when they are in the H level together is not included, and thus, switching elements AS1-AS4 are not turned on simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to an improvement in a time division multiplication circuit that obtains an analog output proportional to the product of two analog inputs, X and Y.

(Prior Art and its Problems) Conventionally, circuits shown in FIGS. 1 and 2 are known as this type of time division multiplication circuit. The time division multiplication circuit shown in FIG. 1 is a pulse width modulation circuit 1 that outputs a periodic pulse train whose pulse width is controlled proportionally to one input voltage EX.
In response to the other input voltage Ev, a voltage +E of opposite polarity is generated.
Amplifier circuits 2 and 3 output Y and -EY, and an amplifier circuit 2 synchronizes with the outputs S and C of the pulse width modulation circuit 1.
It has a switching circuit 4 which alternately switches outputs +EY and -EY of J: and 3 and inputs them into a low-pass filter 5, and the low-pass filter 5 averages the inputs to obtain the two input voltages. It is configured to obtain an output EZ proportional to the product of EX and EY.

FIG. 2 shows operating waveforms of each part of the circuit of FIG. 1.

The pulse width modulation circuit 1 includes an integrating circuit 10 consisting of a resistor R1, a capacitor C1, and an operational amplifier A1;
An output inversion type Schmitt circuit G1 (inverter with hysteresis) that differentiates the level of the output voltage a with hysteresis, and the output of the Schmitt circuit G1 is logically inverted and its output C is fed back to the integrating circuit 10 via the resistor R2. and an inverter G2.

The entire circuit shown in FIG. 1 operates by being supplied with positive and negative power supply voltages V+ and V- having the same absolute value with respect to the ground potential. Therefore, the output ba5 of the Schmidts[- circuit G1 and the output C of the inverter G2 take a logical state of H level-voltage V+ and level-voltage V-.

In the IC pulse width modulation circuit 1 configured in this way, the second
As shown in the waveform diagram in the figure, a kind of excavation loop is formed in which the operating direction of the integrating circuit 10 that integrates the input voltage EX is reversed to the positive or negative direction by the output C of the inverter G2, and the Schmitt circuit G1 A pulse train with a constant period is obtained from the output t5 and the output C of the inverter G2, but the duty of the pulse train does not satisfy the following relationship.

T I + T 2 The amplifying circuit 2 is an inverting amplifier with a gain of 1, consisting of resistors R3 and R4 and an operational amplifier A2, and a voltage -Ev obtained by inverting the polarity of the input voltage Fv is obtained at its output. Similarly, the amplifier circuit 3 is also an inverting amplifier circuit with a gain of 1, consisting of resistors R5 and R6 and an operational amplifier A3.
Voltage -1-E with the polarity of the output voltage of amplifier circuit 2 inverted
Output v.

The switching circuit 4 has a switching element ΔS1 consisting of F E 1" that connects the output +EV of the amplifier circuit 3 and the input side of the low-pass filter 5, and a switching element ΔS1 that connects the output -EY of the amplifier circuit 2 and the input side of the low-pass filter 5. 81 to one switching element.
is controlled on and off by the output of the Schmitt circuit G1 of the pulse width modulation circuit 1, and the other switching element ΔS2 is controlled on and off by the output C of the inverter G2.

In other words, the switching elements ΔS1 and AS2 are driven in a complementary manner by the output signals S and O of the pulse width modulation circuit 1, which are in opposite phases to each other, and the output terminals EY of the amplifier circuit 3 and the outputs of the amplifier circuit 2)
]-EY and enters the low-pass filter 5.

The low-pass filter 5 is an active filter composed of two parallel input resistors R7 and R8 with equal resistance values, a capacitor C2, a resistor R9, and an operational amplifier Δ4. The input signals to which EV and -EY are applied alternately are averaged and the DC component thereof is extracted and used as the output voltage EZ. As is well known, the output voltage EZ of the low-pass filter 5 is determined by the two input voltages Ex and EY.
is proportional to the product of

The conventional time division multiplication circuit configured as described above has the following problems. switching element AS
1. When a semiconductor switching element such as an FET is used as ΔS2, the control terminal (gate) and output terminal (source) of the switching element are connected as shown by the dotted line in Figure 1.
A floating capacitance ff1c10.020 exists between the two. For this purpose, element AS1. As the AS2 switches, a differential signal is generated on its output side, and this differential signal is input to the low-pass filter 5, causing an output error. 4 is shown in FIG. 3 to generate the above-mentioned differential signal with respect to the waveforms at the output point d of the switching element AS1 and the output point e of the switching element AS2. In this figure, the dotted line shows the waveform on which the differential signal is superimposed, and the solid line shows the desired switching characteristics.

The generation of the above differential signal will be explained in detail. The output V+ is applied to the control terminal of the switching element ΔS1, 81 becomes conductive to the switching element, and the voltage +Ev is applied to the output side of the switching element ΔS1.
Suppose that this occurs. At this time, switching element AS
The floating capacitance fic10 of 1 is charged with a voltage of V÷-Ev. After that, when the signal is reversed to V- and the switching element AS1 is turned off, the output of the switching element AS1 changes to V-- (V"-Ev), and the charge in the stray capacitance C10 is discharged via the resistor R8. This results in a differential signal as shown by the dotted line in Figure 3d.

Similarly, when switching element AS2 changes from on to off, a differential signal as shown by the dotted line at e in FIG. 3 is generated.

Such a switching element AS1. △S2 stray capacitance CI'0. The differential pulse caused by C20 causes an error in the output EZ of the low-pass filter 5, but this error is caused by changing the period 1゛10T2 of the pulse width modulation circuit 1 in order to increase the response as a multiplication circuit. The smaller the size, the larger the size, which cannot be ignored.Furthermore, the conventional circuit shown in FIG. 1 has the following problems. A two-phase switching signal that drives switching elements △S1 and △S2 in a complementary manner is C, which is a pulse width modulation circuit 1.
The output signal C is obtained from the input and output sides of the inverter G2 respectively, but the output signal C is somewhat delayed due to the propagation time of the inverter G2 relative to the input signal. This situation is shown in a somewhat exaggerated manner in Figure 4. If the signal C is delayed by ΔT2 with respect to the signal S in this way, at the rising edge of the signal S, both signals S, C and 61-levels, and at one point at the falling edge of the signal S, both signals S, C It becomes L level.

The problem here is that there is a period in which both signals S and C become 1 level at the same time. When both signals S and C become H level, switching elements AS1 and AS2 are turned on simultaneously.

As a result, for example, although the switching element AS2 should be turned off and the amplifier circuit 2 and the low-pass filter 5 should be cut off immediately, the output side of the amplifier circuit 2 is delayed due to the delay in the off timing of the switching element ΔS2. Since the potential is forcibly lowered to the ground potential, the amplification circuits 2 and 3 cannot faithfully perform amplification. Naturally, this also causes an output error.

(Object of the Invention) An object of the present invention is to provide a high-precision timer that prevents the output errors caused by the stray capacitance of the switching elements mentioned above and the output errors caused by the existence of periods in which two switching elements are turned on at the same time. Provides a split frame circuit for covering.

(Structure and Effect of the Invention) In order to achieve the above object, the present invention adds a switching element that works to quickly connect the output side of the switching element to the ground potential when the switching element changes from on to off. At the same time, the switching elements of the two systems are
The present invention is characterized in that a timing adjustment circuit is provided for the switching signals that are auxiliary drives, so that simultaneous on periods are eliminated at the change points of both switching signals, and on the contrary, a minute simultaneous off period is generated.

According to this configuration, even if there is stray capacitance in the switching element, a harmful differential signal will not be generated, and the simultaneous A state of the switching element will not occur, so the conventional output error as described above can be prevented. A highly accurate multiplication operation can be realized.

(Description of Embodiments) FIG. 5 shows a configuration example of an LC time division multiplication circuit to which the present invention is applied. In the circuit of FIG. 5, pulse width modulation circuit 1.
Amplifier circuits 2 and 3. The configuration of the low-pass filter 5 is exactly the same as that of the conventional filter shown in FIG. 1, and the same parts are denoted by the same reference numerals and the explanation thereof will be omitted.

The time-sharing hanging frame circuit according to the present invention is characterized by the following configuration. First, by receiving the output signals S and C of the pulse width modulation circuit 1 and slightly manipulating their changing point timings, the timings of the changing points are almost opposite to each other and are simultaneously 11011 at all changing points.
In other words, a timing adjustment circuit 6 is provided which generates a switching signal consisting of a two-phase pulse train including a minute time when the signal reaches the L level.

The switching circuit 5 also includes a switching element ΔS1 that connects the output note EY of the amplifier circuit 3 and the input side of the low-pass filter 5, and a switching element that connects the output side of this switching element AS1 and a ground potential point. AS3 has a switching element AS2 that connects the output -Ev of the amplifier circuit 2 and the input side of the low-pass filter 5, and a switching element ΔS4 that connects the output j side of this switching element AS2 and the ground potential point. and switching element AS1 to 84
are turned on and off simultaneously by one of the switching signals, and switching elements AS2 and AS2 are simultaneously turned on and off by the other switching signal i.

In this embodiment, the timing adjustment circuit 6 includes an inverter G3, an AND gate G4, and NoR gates 4 to G5, and the operating waveforms of this circuit are shown in FIG.

The output signal from the pulse width modulation circuit 1 is an AND game h
G4 and NOR gate G5, respectively.

Further, the signal C, which is distorted by ΔT2 by passing the inverter G2, is input to the AND gate G4 and the NOR gates i to G5 through the inverter G3.

Then, from the AND game h G 4, the switching element △
The switching signal applied to S1 and AS4 is output, and NO
A switching signal i applied to switching elements AS2 and ΔS3 is output from R gate G5.

Here, the input/output C→9 of the inverter G3 is accompanied by a response delay of ΔT3 as shown in FIG. 6, and the input/output of the AND gate G4 is also accompanied by a response delay of ΔT4. The input/output is accompanied by a response delay of ΔT5. By utilizing these response delays, as shown in Fig. 6, the switching signals R and i correspond to the outputs of the pulse width modulation circuit 1 and C, respectively. The rising and falling timings are slightly manipulated,
T is included in the minute period in which both signals are at L level at all changing points, and the signal does not include any period in which both signals are at H level.

As a result, switching elements ΔS1 to AS4 simultaneously switch to A
This eliminates the possibility that the output sides of the two J-width circuits 2 and 3 become short-circuited and impair the normal amplification function as in the conventional case, and it is possible to prevent output errors at this point. can.

Furthermore, as the switching element ΔS1 changes from on to off, the switching element AS3 simultaneously changes from on to off, and the output side of the switching element AS1 is quickly pulled down to the ground potential.
The charge discharge of the stray capacitance cio of I is also instantaneously performed, and the disadvantage of generating a differential signal and inputting it to the low frequency filter 5 side as in the conventional case is eliminated. The same applies to the operation of the switching element AS2, and the action of the switching element Δ$4 prevents a differential signal from being input through the resistor R7 of the low-pass filter 5 as in the conventional case.

Note that the switching elements AS1 to Δs4. Schmitt circuit G1. Inverter G2. G3. NAD gate G4. N
It is preferable that the OR gate G5 is a C-MOS and is further subjected to an iF. In this case, since the input/output transmission time of the C-MOS gate 1~ is about 5Qns, even if the output period of the pulse width modulation circuit 1 is sufficiently small as 100μs, the timing adjustment circuit 6 will not be able to adjust the above ΔT. The error is very small, 0.1% or less, and can be suppressed to a negligible level.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional differential division multiplication circuit, Figure 2 is a waveform diagram showing the operation of the circuit in Figure 1, and Figures 3 and 4 show problems with the circuit in Figure 1. A waveform diagram, and FIG. 5 is a circuit diagram showing the configuration of a time-sharing multiplication circuit to which the present invention is applied.
FIG. 6 is an operational waveform diagram of the timing adjustment circuit 6 shown in FIG. 1...Pulse width modulation circuit 23...Amplification circuit 4...Switching circuit 5...Low pass filter 6...Timing adjustment circuit ASI to AS4. ... Switching element patent applicant Tateishi Electric Co., Ltd. Figure 3 Figure 4 Figure 6 Figure 5

Claims (1)

[Claims] (1) A pulse width modulation circuit that outputs a periodic pulse train whose pulse width is controlled proportionally to input signal X on one side, and voltages +Ev and -EY of opposite polarity proportional to input signal Y on the other side. outputs 1 to EY and - of the amplifier circuit in synchronization with the output of the amplifier circuit and the pulse width modulation circuit.
a switching circuit that alternately switches Ev and inputs it to a low-pass filter, and a time-sharing multiplication circuit that averages the input in the low-pass filter to obtain an output proportional to the product of two input signals X and Y. In the above, the pulse train output of the pulse width modulation circuit is received and its change timing is slightly manipulated to produce a two-phase pulse train that is almost in opposite phase to each other and includes a short time period in which all change points become zero at the same time. The switching circuit includes a switching element ΔS1 that connects the output +EY of the amplifier circuit and the input side of the low-pass filter, and this switching element Δs1.
A switching element Δs3 connects the output side of the switching element Δs3 to the ground potential point, a switching element AS2 connects the output side of the amplifier circuit -EY and the input side of the low-pass filter, and the output side of this switching element AS2 connects to the ground potential point. It has a switching element ΔS4 that connects the points, and the switching elements AS1 and AS
4 are simultaneously turned on and off by one of the switching signals, and the switching elements AS2 and ΔS3 are simultaneously turned on and off by the other switching signal i. Multiplication circuit.