SU1495981A1 - Stabilized generator of triangular voltages - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automatic control devices. The purpose of the invention is to increase the speed of the device by accelerating twice the transient processes of establishing a predetermined amplitude of the triangular voltage with a change in its frequency. The device containing the tilt control unit 1, the modulator 2, the integrator 3, the inverter 4, the reference voltage source 5, the threshold elements 6,7, the control unit 9, the delay element 8 is entered, the new connections, and the control unit 9 contains the inverters 14-19, elements AND 20-23, an exclusive OR element 24, and an element 2I - 2 OR 25. In a tilt control unit 1, a voltage is applied through the modulator 2, which can change the polarity of this voltage, to the integrator 3. When the triangular voltage reaches the value given by source 5, in block 1 Odita reduction control voltage, and if the amplitude of the triangular voltage reaches a predetermined value, the voltage in the unit 1 is increased. Due to the distinctive features, voltage changes in block 1 occur twice as often. 2 hp formulas. 4 il.

Description

,

The invention relates to a pulse technique, and can be used in automatic control devices.

The purpose of the invention is to increase the speed at the expense of doubling the speed of transient processes to establish a predetermined amplitude of the threefold voltage with a change in the driving frequency.

I FIG. 1 shows a structural | Generator diagram; in fig. 2 is a diagram of a tilt control unit; FIG. 3 is a modulator circuit; in fig. 4 - time diagrams of the device operation. I The proposed generator (Fig. 1) spans the tilt control unit 1, the modulator 2, the integrator 3 and the inverter: 4 connected in series, the source 5 of the reference voltage, the first: 6 and the second 7 threshold elements, | Delay 8, control unit 9, | control voltage bus 10, bus 11 | synchronization pulses, first 12 and second 13 output buses. : The input of unit 1 is connected to bus 11, and its output is connected to the second input of modulator 2. The outputs of integrator 3 and inverter 4 are connected to the first inputs of the first 6 and second 7 threshold elements, respectively, and also the first 12 and second 13 output tires, respectively. The second inputs of the first 6 and second 7 threshold elements are connected to the source 5, and the outputs to the first and second inputs of the control unit 9, respectively, the third input of which is connected to the bus 11 and through the delay element 8 to its fourth by the entrance. The first center-second outputs of control unit 9 are connected to the first and second control inputs of unit 1, and the third to sixth outputs are connected to the first, second, third, and fourth inputs of the modulator 2, respectively.

Control block 9 contains first to sixth elements NOT 14-19, first to fourth elements AND 20-23, an EXCLUSIVE IPI 24 element and element 2I-2ILI 25, the input of the first element NOT 14 being the first input of the control block 9 and connected to the first input of element 2I-2ILI 25, and the output connected to the first input of the first element AND 20, the input of the second element NOT 15 is the second input of control unit 9 and connected to the second 25

thirty

five

YU

5 35 40 p-45 jg 55 eye input element 2H-2ILI 25, and the output is connected to the first input of the second element And 21, the input of the third element NOT 16 is the third input of the control unit 9 and connected to the main inputs of the fourth element And 23 and EXCLUSIVE IPI 24, and the output is connected to the first input of the third element And 22, the second input of the element EXCLUSIVE OR 24 is the fourth input of control unit 9, and the output is the first output of control unit 9 and connected through the fourth element HE 17 to the second inputs of the third 22 and the fourth 23 elements And, out The ports of which are connected to the second inputs of the first 20 and second 21 elements AND, respectively, as well as the third and fourth inputs of element 2I-OR 25, the output of which is the second input of control unit 9, the outputs of the first 20 and second 21 elements AND are the sixth and the fifth outputs of the control unit 9, as well as connected respectively to the inputs of the fifth 18 and sixth 19 NO elements, the outputs of which are the fourth and third outputs of the control unit 9, respectively.

Block 1 (Fig. 2) contains the first 26 and second 27 resistors, the first 28 and second 29 switches, the capacitor 30, and the voltage follower 31. The first terminal of the resistor is the input of block 1, and the second is connected to the input of the first switch 28, the output of which is connected to the OUTPUT of the second switch 29, through a capacitor 30 to the common bus, which is connected through the second resistor 27 to the input of the second switch 29, output which is also connected to the input of the repeater 31, the output of which is the output of block 1, the first and second control inputs of which are controllers; and the inputs of the first 28 and second 2.9-keys, respectively,

Modulator 2 (FIG. 3) contains first to fourth switches 32-35, first to fourth resistors 36-39, and an operational amplifier 40, the output of which is the output of modulator 2, and through the third resistor 38 is connected to its inverting input . The inputs of the first 32 and second 33 keys are the first and second inputs of the modulator, respectively, and their outputs are connected to the inputs, respectively.

the third ID 34 and the fourth 35 keys, as well as through the first 36 and second 37 resistors, respectively, with inverting and non-inverting inputs of the operational amplifier 40. The outputs of the third and fourth keys 3 35 are connected to the common bus, and through the fourth resistor 39 - with non-inverting input of the operational amplifier 40.

Block 9 (Fig. 1) can be performed according to another scheme, but must implement the following Boolean functions: UY1 1 and 2 + 1Л U2; (Ul tp + u1 tp); UY3 yiUY1tp; UY4 U1UY1tg;

,

where UYi,, 6 is the logical signal on the i-M output of the control unit;

U1 is a sequence of symmetric rectangular input pulses on the bus 11 that synchronize the operation of the device; U2 is a sequence of delayed symmetric rectangles of pulses from the output of element 8;

tp - output signals of the first 6 and second 7 threshold elements, respectively. A block can also be executed on one programmable permanent storage device (for example, a K155 REZ chip, if it is not used to frequently use inputs and outputs).

The generator works as follows.

The input pulses U1 (Fig. 4a) step on the input of element 8 (Fig. 1) and are converted into pulses U2 (Fig. 4b), which are delayed relative. At the time interval when U1 and U2 are simultaneously equal to the logical unit, control block 9 on the third and sixth outputs, it generates pulses (Fig. 4g, l), equal to a logical unit, and on the fourth and fifth outputs (Fig. 4k.k) - impulses, which are equal to a logical zero. In this case, in modulator 2, keys 32 and 33 are closed, and keys 33 and 34 are open .. Modulator 2

t ;,

transmits the voltage from block 1 to the input of the integrator 3 (Fig. 4, n). Do not change his sign. The voltage at the output of the integrator 3 (Fig. 1) decreases linearly with time, and at the output of the inverter 4 increases (Fig. 4o). When the voltage at the output of the inverter 4 reaches a voltage equal to

0 to the voltage U at the output of source 5, at the output of the second threshold element 7, a signal tp appears (fig.4d), equal to a logical unit, as a result of which, in modulator 2, switch 32

5 closes and key 34 closes. In this case, the input of the integrator 3 is connected to the common bus and the voltage at its output until the time point, until the signal U2, becomes equal to logical zero

0 is kept equal to the minimum value of Up, and at the output of the inverter 4, to the maximum value + U (Fig.4o), respectively. Block 9 generates an impulse UY2 (Fig. 4e), which is connected to the control input of key 29 in block 1. The key 25 closes and pulses the capacitor 30 through a current limiting resistor 27 to the common power supply bus. The bit is stopped at that time point when the signal U1 becomes zero. At the time interval when the signal U1 is equal to a logical zero 5 and U2 is a logical one, the control unit generates a pulse Y1 (Fig. 4c), which is fed to the control input of the key 28 in the block 1. The key 28 closes and the pulse charge of the capacitor 30 is performed and 10 via a resistor 26. Charging stops at. that time when the signal U2 becomes zero.

In the time interval when signals U1 and U2 are simultaneously equal to logical zero, control block 9 generates pulses UY4 and UY5 (Fig. 4h, k) equal to a logical one, and UY3 and UY6 (Fig. 4g, l) are equal to

Q logical zero. In this case, in module 2, keys 33 and 34 are closed, and keys 32 and 35 are open. The modulator 2 passes to the input of the integrator 3 the voltage from block 1 with the opposite sign

e (Fig. 4n). The voltage at the output of the integrator 3 (Fig. 1) increases linearly, and at the output of the inverter 4 decreases linearly (Fig. 4o). When the voltage at the integrator output reaches

0

five

0

five

a voltage equal to the voltage U at the output of the source 5, at the output of the first threshold element 6, a signal tp appears (fig. 4d) equal to the logical unit, as a result; the key 33 in the modulator 2 is dismounted, and the 1SOLUT 33 is locked. In this case, the input: the integrator 3 is again blocked and: the voltage at its output until time I, until the signal U2 becomes equal to a logical one, is maintained; equal to the maximum value of + and „,

and at the output of inverter 4, the minimum value of -U (fig.Ao), respectively.

I On the time intervals when the signals U1 and U2 are equal to logical zero, the signal tp is a logical one and when; Yes, the signal U1 is equal to the logical one, I cce, and the signal U2 - to logical zero; Similarly, the discharge and charge cycles of the ca- de torus 30 in the tilt control unit

(Fig. 4m). Further, the operation algorithm of the mouth; Repeatings are repeated.

Consider the process of stabilizing the amplitude of the triangular voltage at the level of U. Let the generator operate at some fixed frequency. Timing diagrams for this case are shown in FIG. 4, and the algorithm of the device operation is indicated.

Suppose that the frequency of the input pulses has increased. However, the established voltage value on the capacitor 30 does not immediately change and the slope of the voltage at the output of the integrator 3 at the first moment will remain the same. Then for the duration of the half period. input pulses, which decreases as the input frequency decreases, the output voltage of the integrator 3 (inverter 4) does not reach the voltage level, therefore, the first (second) threshold element 6 (7) does not operate. This will cause the tp (tp) bit pulses to disappear and the key 29 in the tilt control unit 1 will no longer work. After that, the peg transition process of the capacitor 20 dosage will begin to the voltage value characterizing the new steady state, corresponding to the increased

. frequency of input pulses.

Suppose that the frequency of the input pulses is yMeHbniHJiacb. As in the previous case, the set value

0

five

0

c 0 g

0

five

the voltage on the capacitor 30. does not immediately change and the slope of the voltage at the output of the integrator 3 will remain the same at the first moment. Then, over the half-cycle duration of the input pulses, which increased as the input frequency decreases, the output voltage of the integrator 3 (inverter 4) reaches the voltage level t from the output of source 5 and the first (second) threshold element 6 (7) is triggered. However, the duration of the discharge pulses tp (tp) will increase by the same magnitude as the half period of the input pulses. Thereafter, a transient discharge of capacitor 30 will begin to a voltage value characterizing the new steady state corresponding to the reduced frequency of the input pulses.

In the known device, the transients when changing the input frequency go two times slower than in the proposed one, since the charge-discharge cycles of the storage capacitors, which lead to a change in the voltage across them, occur once per period of the input pulses. In the proposed device, charge-discharge cycles of the storage capacitor occur in each half-cycle of the input pulses, which increases the speed of the device

Thus, the proposed generator has a faster response than the known one.

Claims (1)

Invention Formula A triangular voltage generator with a tilt control unit, the input of which is connected to the control voltage bus and the output to the first input of the modulator, the output of which is connected to the input of the integrator, the output of which is connected to the first input of the first threshold element and through the inverter the first input of the second threshold element, the second inputs of the first and second threshold elements being connected to the output of the voltage source, and the outputs to the first and BTopbiM inputs of the control unit; the third input of which is connected to the synchronization pulse bus, the first and second outputs of the control unit being connected respectively to / Fib.2 Phie. 3 th S g in w J and x J m and t j J i t Phie.