SU1256191A1 - Switching device - Google Patents

Abstract

The invention relates to automation and measurement technology. The purpose of the invention is to reduce the consumption of electrical energy and enhance functionality. The switching device contains a quartz oscillator 1, N-bit divider 2 frequencies and a transistor-opto-module 10 galvanically isolated. Introduction of the multiplexer 3 switching periods, trigger 4, unit 5 of the period code, multiplexer 6 of the charge-discharge period, block 7 of the driver-for-charge-pulse-formers — made in the form of two formers 8 and 9 of the charge-control pulses and discharge and the formation of new connections reduce the constant power dissipation and provide the possibility of automatically changing the charge-discharge periods of the capacitor and the switching period. 2 h. n. f-ly, 5 ill. Jsyf-f

Description

one

The invention relates to automation and measurement technology and can be used in automatic switching devices.

The purpose of the invention is to reduce electrical energy consumption at a time of expanding the functionality by reducing the constant power dissipation and allowing automatic change of the charge-discharge periods of the capacitor and the switching period.

Figure 1 shows the structural. switching device circuit; FIG. 2 is a diagram of a transistor-optocoupler of the galvanic isolation unit; Fig. "3 is a diagram of a charge or discharge control pulse driver. :: first choice; figure 4, - the same, according to the second option; figure 5 is a timing diagram of the operation of the switching device.

The switching device contains a quartz oscillator 1, the output of which is connected to the input of the N-bit divider 2 frequency, the multiplexer 3 of the switching period, the output of which is connected to the input of the trigger 4, the setpoint 5 of the period code, the outputs of which are connected to the multiplexer 6 of the charging period - discharge and the input of the multiplexer 3 switching periods, and the output of the multiplexer 6. is connected to the clock inputs of the block 7 of the drivers of charge-discharge control impulses, consisting of drivers of charge and discharge pulses with responsibly, signal inputs of which are connected respectively to direct and invariant population-inverted outputs of the flip-flop 4, and outputs connected to inputs of the transistor unit 10-photocouple galvanic decoupling, the outputs of which are schinoy control 11. The outputs of the N-bit divider frequency 2 are connected to the corresponding inputs of the multiplexer 3 switching periods and multiplexer 6 of the charging-discharge period. The transistor-optic block 10 contains the first resistor 12, the relay 13, the capacitor 14, the first transistor 15, the first bus 16. the power source, the second transistor 17, the photodiode 18 block of the Optrons, the second resistor 1.9, the third transistor 20, the third a resistor 21 and a second power supply bus 22.

1912

The first terminal of the first resistor 12 is connected to the output of the driver 8 for the charge control pulses, and the second terminal is connected to the base of the first p - p - n transistor 15, the emitter of which is connected to the first bus 16 of the power supply, and the collector - to the emitter of the second p - p - p-transistor 17, the first output of the block 18 photodiode optocouplers and the common point of the electrolytic capacitor 14 and the winding of the relay 13, the contacts of which are connected to the control bus 11, and the second output of the winding of the relay 13 - to the second bus

22 of the power source I with the collector of the second p - p - p transistor 17, the base of which is connected to the second output of the photodiode photodiode unit 18, the first input of which is connected to the second power supply bus 22, and the first input through the second resistor 19 is connected to the collector of the third p - p - n-transistor 20, the emitter of which is connected to the first bus 16 of the power supply, and the base through the third resistor 21 is connected to the output of the driver 9 control pulses

capacitor discharge 14. I

Shaper 8 is a control pulse of a capacitor 14 or shaper 9 of a pulse. the discharge of the capacitor 14 of the block 7 of the pulse-control drivers of the charge-discharge of the capacitor 14 according to the first variant of the circuit comprises the first trigger 23, the first AND-NO element 24, the resistor 25, the second trigger 26, the second AND-NE element 27 and the inverter 28, Synchronization input of the first trigger

23 is the signal input of the driver 8 and 9 and is connected to the output of trigger 4, and the direct Q and inverse Q outputs of the first trigger 23 are connected respectively to the information input of the second trigger 26 and to the first input of the first AND-24 element 24, the output of which is connected to the zeroing input of the second trigger 26, and the second input to the zeroing input of the first trigger .23, the input of the inverter 28 and the output of the second AND-NE-27 element, the first and second inputs of which are connected respectively to the direct output and the synchronization input second trigger 26. Installation in the course of the second 26 and the information and installation inputs of the first 23 trigger are combined and connected via a resistor 25 to the third source bus

(+5 V). The synchronization input of the second trigger 26 is the clock input of the generator 8 or 9 of the charge control pulses I.PI discharge of the capacitor and connected to the output of the zero-multiplexer 6 of the period of charge-discharge Yes capacitor. The output of the inverter 28 is the output of the driver 8 or 9 of the control pulse or the discharge of the capacitor and is connected to the input of the transistor-opto-module 10.

Shaper 8 pulse control pulses or shaper 9 pulses of control of discharge of capacitor 14 of block 7 according to the second variant of the circuit contain the first trigger 29, the first element OR 30, the second trigger 31, the inverter 32, the second element OR NOT 33.

The forward output of the first trigger 29 is connected to the information input of the second trigger 26 and the first input of the first element OR-NOT 30, the output of which is connected to the zero input of the second trigger 31, and the second input to the zero input of the first trigger 29 and 33, the first and second inputs of which are connected respectively to the inverse output of the second trigger 31 and the output of the inverter 32, the input of which is connected to the synchronization input of the second trigger 31. The installation inputs of the second 31 and first 29 triggers and the information input of the first flip-flop 29 are respectively connected to a first bus 16 and the third power supply bus (5 in). The synchronization inputs of the first 29 and second 31 flip-flops are respectively the signal and clock inputs of the drivers 8 or 9 of the capacitor charge or discharge control pulses and connected to the output of the trigger 4 and the output of the multiplexer 6 of the charge-discharge period of the capacitor. The output of the second element OR-NE 33 is the output of the driver 8 or 9 pulses controlling the charge or discharge of the capacitor and is connected to the input of the transistor-opto-module 10.

FIG. 5 shows the sequence of pulses 34 of the crystal oscillator 1, the signal 35 is a square wave from the first Q, - output N - bit divider 2 frequencies, the signal 36 is square wave from the direct Q output of the trigger 4, the signal is 37 me

5 10

(5 20

25 about 0 5 0

five

five

andr from inverse Q-trigger of trigger 4, waveform 38 at the output of shaper 8, controlling the charge capacitor 14, pulse signal 39 at the shaper 9, controlling the discharge of the capacitor 14, voltage 40 at the capacitor 14, current waveform 41 and the voltage 42 in the winding of the relay 13.

The switching device operates as follows.

The quartz oscillator 1 forms a pulse train with a stable repetition rate f. The N-bit divider 2 frequencies from the bit outputs Q,., ..., Q |, ..., QN is the grid of short frequencies f, f, ,. .., f, ..., f. For example, for a binary divider, the frequency grid would be 1 / 2fg, 1 / 4fg, ..., 1/2 f,. . . , 1/2 fp or for periods. pulse repetitions, respectively, 2To, 4T,, ..., 2T ", ..., 24, where T (, is the pulse repetition period of the crystal oscillator 1. Pulse signals of the square wave type with multiple frequencies and repetition periods arrive at the corresponding inputs of the multiplexer 6 the period of charge-discharge of the capacitor 14 and to the inputs of multiplex 3, the switching periods of the two-position double-stable polarized electromagnetic relay 13. Depending on the code generated in the unit 5 of the period code, either manually or from a control microcomputer or microprocessor,one of N signals with a repetition period T passes through multiplexer 6 from divider 2 frequency (and one of signals with repetition period T passes through multiplexer 3, the inequality T T must be fulfilled. The signal from the output of multiplexer 6 is supplied to the clock signals The C inputs of the second DRS flip-flops 26 of the drivers 8 and 9 of the pulses control the charging and discharging of the capacitor 14. The output from the multiplexer 3 of the switching period of the relay 13 is fed to the input of the T-flip-flop 4. On the direct Q and inverse Q outputs T -trigger 4 form phase pulsed natural oscillations meander type with twice the period of repetition T c for which the condition is vtoln TTP 2X2 T. These oscillations are respectively fed to the signal C-inputs of the first PEZ-flip-flop drivers

S1256

and 9 pulses controlling the discharge of capacitor 14.

To the informational D input and installation S input of the first 23 and installation S input of the second 26, DRS triggers through the resistor 25 are denied; The power supply bus (+5 V) operates with a constant signal with the level of Ogic 1. When entering the first DRS-10. Trigger 23 with the I-signal of the first DRS-10 with a level of logical 1 on its direct and inverse Q- Outputs Voltages occur with a logic level of 1 and O, which are applied respectively to the D input of the second DRS flip-flop; 26 and the first input of the first element IS-NOT 24. At the output of the second element AND-NOT 27, a voltage is applied with a logic level 1, which is fed 20 to the R input of the DRS trigger 23 and the second input of the first element IS-NOT 24 at the output which appears voltage with a logic level 1, while at the R-inputs of the DRS-flip-flops 23 and 26 25 there is a voltage with a level of logic 1, which does not change the state of the outputs of these triggers.

When the n-i C synchronization input of the second DRS trigger 26 of the first clock pulse appears from the output of the multiplexer 6, a voltage appears at the first output of the second DRS trigger 26 with a logic level 1 which acts on the first input of the second element 35 AND-NOT 27, the second input of which is also acted upon by the logic level 1 from the first clock pulse of the multiplexer 6, as a result, the output of the second element IS-NOT 27 causes a voltage with an active logic level O that acts on the R input zeroing the first trigger 32 and zeroing it (-output, while at its inverse Q-output a voltage appears at logic level 1. When the first clock pulse transitions to logic half-period O, the output of the second AND-27 element in accordance with the truth table ° appears for example with a logic level of 1 which acts on the second input of the first element AND-NOT 24, at the output of which a voltage appears with an active logic level of 55 O, which wraps the direct Q output of the second PRS trigger 26 and at the output of the second element AND-NOT 27 appears

1916

voltage with a logic level 1, and at the output of the inverter 28 - voltage with a logic level O.

The second and subsequent clock pulses from the output of multiplexer 6 during the period of effect of the signal pulse from the output of T-flip-flop 4 do not change the output state of shaper 8 and 9, since the direct Q-outputs of DRS flip-flops 23 and 26 are in a state of logical O Thus, from a longer T-trigger signal pulse 4, a shorter pulse is generated at the output of the imaging unit 8 or 9 of the control or discharge control pulses of the capacitor 14, the duration of which is controlled by the period code setting unit 5.

The principle of operation of the formers 8 and 9 of the pulses controlling the charge or discharge of the capacitor in FIG. 4 is similar to the principle of the action of the formers 8 and 9 in FIG.

The output pulses of controlling the charge and discharge of the capacitor from the formers 8 and 9 are fed to the inputs of the transistor-opto-module 10.

Transistor-opto-unit 10 operates as follows.

The output pulses 38 and 39 (Fig. 5) of the formers 8 and 9 are fed through resistors 12 and 21 to the bases of n - p - n - transistors 15 and 20, which operate in key mode. When the logic level is high, the pulse that controls the capacitor charge, transistor 15 is switched to saturation mode and through the full transistor 15, electrolytic capacitor 14 and the resistance of a polarized two-position two-sided electromagnetic switch 13 from the second control unit 22 the charge current flows capacitor 14. In the winding of relay 13, a positive exponential impulse is generated. A voltage and current, the magnetic field of which, interacting with the magnetic field of the permanent magnet of the polarized relay, switches it Measuring into one of the stable equilibrium positions, while the transistors 20 and 1 are in the state of the collector current cut-off, because a low logic level is generated from the output of the discharge control pulse generator 9 (Fig. 5; 39). As a result, the capacitor 14 is charged during the period of the clock pulse of the multiplexer 6. When the clock pulse of the multiplexer 6 ends, the transistor 15 switches to the collector current cut-off mode and the charged capacitor 14 retains its charge.

When a pulse is detected on the base of the transistor 20, which controls the discharge of the capacitor 14, the transistor 20 switches to the collector current saturation mode and through the impressed transistor 20

and V, block

ABOUT

resistor 19 and V LEDs

18 photodiode optocouplers from the second

The busses 22 are flowing current, as a result of which the LEDs Vj and V emit light, which charge and pulse generator. This transforms photodiodes V into a doubled photo-emf, and Vc, which opens the n-p - p - p transistor 17 and converts it to the n-stage mode.

As a result, a time-20 discharge circuit and inputs of the periode multiplexer capacitor 14 through the transistor 17 and the relay coil 13 are formed. When the electrolytic capacitor 14 is discharged through the resistance of the relay coil 13 in the last 25, direct and inverse outputs

negative exponential pulses of voltage and current are formed, the electromagnetic force changes sign and the relay 13 relay switches to its original stable equilibrium position. When using matched n - p - n transistors 15 and 17 in a transistor-optic circuit, we achieve the equality of the resistance of the charge and discharge 35 transistors 15 and 17, and therefore the charge-discharge current modules of the capacitor 14, as well as electromagnetic forces switching the switch of the relay 13 with equal times into stable equilibrium conditions.

The technical effect of using the proposed switching device is to reduce the consumption of electrical energy while simultaneously expanding the functionality by reducing the constant power dissipation and enabling automatic change of the periods, charge -50 of the capacitor discharge and the switching period.

Claims (3)

Invention Formula 1. A switching device containing a crystal oscillator, the output of which is connected to the input of the N-bit Frequency divider, transistor-optocoupler of galvanic isolation with output control bus, о T -. Likewise with that in order to reduce the consumption of electrical energy while expanding the functionality, a charge-discharge period multiplexer, a switching period multiplexer, a period code setpoint generator, a trigger, and a home-control charge driver generator unit, made of two identical-former, were introduced into the device. of the control pulses of the control of the discharge of the capacitor, the outputs of the N-bit splitter are connected to the corresponding inputs of the multiplexer of the switching charge period, inputs of Ko; the second ones are connected to the output of the target code of the period code, the trigger input is connected to the output of the multiplexer period overlap 30 35 0 0 5 the trigger is connected to the signal inputs of the charge and discharge control pulse driver units of the charge-discharge control pulse driver units, the clock inputs of which are connected to the output of the charge-discharge period multiplexer, and the outputs to the inputs of a transistor-opto-galvanic isolation unit, which consists of three transistors, three resistors, a series circuit of a capacitor and a relay winding, a photodiode optocoupler unit, the emitter of the first transistor connected to the first power supply bus, base, - with the first output of the first resistor, the collector with the emitter of the second transistor, the first output of the photodiode optocouple unit and the first output of the successive circuit from the capacitor and the relay coil, the second output of which is connected to the second power supply bus and to the collector of the second transistor, the base of which is connected to the second output of the unit photodiode optocouplers, the first input of which is connected to the second power supply bus, and the second input through the second resistor to the collector of the third transistor, the emitter of which is connected to the first bus power supply, and the base with the first output of the third resistor, the second outputs of the first and The third resistors are the inputs of the transistor-opto-module, and the normally-closed, normally-open, and flip-over relay contacts are the control bus. 2. A device according to claim 1, which is based on the fact that the driver for charge control pulses or driver for control pulses contains two triggers, two, AND-NES elements, an inverter, a resistor, and the direct and inverse outputs of the first trigger connected respectively to the information input of the second trigger and to the first input of the first NAND element, the output of which is connected to the zeroing input of the second trigger, and the second input to the zeroing input of the first trigger, the input of the inverter and the output of the second NAND element, first and second in Which are connected respectively to the direct output and to the synchronization input of the second trigger, the information and installation inputs of the first and installation inputs of the second trigger are combined and through, the resistor is connected to the third bus of the power source, and the inputs of the synchronization of the first and second triggers are respectively the signal and clock inputs, and the output is an inverting output of the charge or discharge control pulse generator. | 3. The device according to Claims 1 and 2, t - characterized by the fact that the driver for charge control pulses or the driver for control pulses contains two flip-flops, two OR-NOT elements, an inverter, and the direct output of the first flip-flop is connected to the information input the second trigger and the first input of the first element OR NOT, the output of which is connected to the zeroing input of the second trigger, and the second input - to the zero input of the first trigger and the output of the second element OR NOT, the first and second inputs of which are connected respectively to the inverse The output of the second trigger and the output of the inverter, whose input is connected to the synchronization input of the second trigger, the setup inputs of the first and second triggers and the information input of the first trigger, respectively, are connected to the first and third power supply buses, and the synchronization inputs of the first and second triggers are respectively the signal and the clock inputs, and the output of the second element OR NOT — by the output of the charge or discharge control pulse generator. Fig.Z sixteen 29 Since you move Chitp fc trigger J} / f From the multiplier of the multiplexer of the period of the salary-razl a / gdendena satora. - Fig.It 8.f Not fxfi tram optor optrvno - to block 3f Q On the course of the transistor ft o optocoupler ff / roKu 306 Jj g fr EH lll TlJ-lJlJ J-lJ J lJ l.J