JPS61116422A - Analog-digital converting circuit - Google Patents

Abstract

PURPOSE:To make a response time highly speedy by connecting a modulating signal to a measured analog signal input terminal side of the first switch, and changing over the first switch by the output of the frequency dividing circuit. CONSTITUTION:A frequency dividing circuit 7 divides the output clock phi of a clock pulse generating device 5, generates a modulating signal voltage + or -Ec, and the output of the frequency dividing circuit 7 is inputted through a resistor Rc via a switch SW1 to an integrating device 2. A switch change-over signal INT from the frequency dividing circuit 7 controls to change over the switch SW1. When a measured analog signal Ex is inputted from an input terminal TM1, the integrator 2 executes the integrating action including the measured analog signal Ex besides the modulating signal voltage + or -Ec and a reference voltage +Es. Thus, an analog digital converting circuit does not increase a clock frequency and the response characteristic is made highly speedy. The frequency of the synchronizing clock may be the low one to the extent that the frequency is accommodated several times during the integrating time, and the analog digital converting circuit can easily be made highly speedy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the configuration of an analog-to-digital conversion circuit. In particular, it relates to improvements in analog-to-digital conversion circuits using feedback pulse width modulation.

[Conventional technology]

In conventional feedback pulse width modulation analog-to-digital conversion circuits, an input voltage is applied to an integrator along with a square wave clock voltage and a reference voltage switched at the comparator output. The comparator compares the integrator output with the zero level,
When it is positive, a switch is switched so that the reference voltage is negatively fed back to the integrator. The period during which the switch is in contact with the reference voltage side varies depending on the magnitude of the input voltage.
Equilibrium is reached when the average value over the period just cancels out the input voltage.

Analog signals using conventional feedback pulse width modulation
The problem with digital conversion circuits is that the analog-to-digital conversion system exhibits first-order lag characteristics in response to changes in input, requiring a long response time.

In order to solve this problem, one proposal has already been made and put into practical use. By increasing the frequency of the synchronous clock, inserting a D-type flip-flop circuit in the feedback loop, and making one sample a product of several times of this synchronous clock, it is possible to achieve a certain degree of speed without reducing resolution. (Japanese Patent Application No. 55-125009, ``Analog-digital converter and digital voltmeter'').

[Problem that the invention seeks to solve]

However, in such a conventional analog-to-digital conversion circuit using feedback pulse width modulation, the delay time cannot be reduced to zero, and it is necessary to wait for several synchronization clock cycles.

Furthermore, if the frequency of the synchronization clock was increased in order to shorten this time, the high-frequency characteristics of the integrator deteriorated, which caused problems such as frequency limitations.

The present invention has been made by focusing on these conventional problems, and is an analog/digital system using feedback pulse width modulation that can speed up the response time of input response characteristics without increasing the frequency of the synchronization clock. The purpose is to provide a conversion circuit.

[Means for solving problems]

The analog-to-digital conversion circuit of the present invention includes an analog signal input terminal to be measured, a clock pulse generator, a frequency divider that receives the output of the clock pulse generator and generates a modulation signal for operating the system, and a reference resistor. a reference voltage input terminal connected to the reference voltage input terminal, the modulation signal having a rectangular waveform having an amplitude larger than the reference voltage;
an integrator that integrates the added voltage of the modulation signal and the analog signal under test; and an integrator provided between the input terminal of the integrator and the input terminal of the analog signal under test, and the analog signal under test is connected to the integrator. a first switch that selectively connects to the input terminal of the integrator, a second switch that opens and closes the connection between the input terminal of the integrator and the reference voltage input terminal, and a comparison that compares the output of the integrator with zero potential. The output of this comparator is taken as one input, the output of the above clock pulse generator is taken as the other input, the output of this comparator is synchronized by this clock pulse, and when the output of the above comparator is inverted, a synchronization circuit that generates a signal for opening and closing the second switch; an AND circuit in which one of the outputs of the synchronization circuit and the output of the clock pulse generator are connected to two inputs; In the digital-to-analog conversion circuit, the modulation signal is connected to the analog signal input terminal under test of the first switch, and the analog-to-digital conversion output terminal is connected to the output of the AND circuit. The first switch is characterized in that it includes means for switching by the output of the frequency divider.

[For production]

The present invention switches the input signal that enters the integrator input of an analog-to-digital conversion circuit using feedback pulse width modulation and the modulation signal in synchronization with the integration time to create two operating states. It is possible to eliminate the lag characteristic and speed up the response of the analog-to-digital conversion circuit without increasing the frequency of the synchronization clock. In other words, analog-to-digital conversion is completed after each conversion, and there is no influence from the previous stage, so the response to the input is a quick-response analog-to-digital conversion circuit that has no effect even if there is a change immediately before the start of analog-to-digital conversion. Can be configured.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of an analog-to-digital conversion circuit using feedback pulse width modulation.

In FIG. 1, an input terminal TM to which two analog signals to be measured E are input is an input resistor R and a switch SW.
It is connected to the negative input terminal of operational amplifier 1 via I. A capacitor C3 is connected between the negative input terminal and output terminal of the operational amplifier 1 to form a feedback circuit. The positive input terminal of operational amplifier 1 is grounded. Therefore, the circuit consisting of the operational amplifier 1 and its associated input circuit and feedback circuit forms an integrator 2. Similarly, the negative input terminal of the operational amplifier 1 receives a modulation signal voltage ±EC1 and a switch SW via a switch SW.

A reference voltage element E, is applied through each.

Here, the resistor Rs connected between the switch SW2 and the reference voltage element E is a reference resistor for keeping the current flowing into the integrator 2 constant. The switch SW2 is
For example, an electronic switch using an FET is used.

The output of integrator 2 is connected to the negative input terminal of comparator 3.

The positive input terminal of comparator 3 is grounded. Therefore, comparator 3 compares the output of integrator 2 with zero potential.

The output of the comparator 3 is connected to the D input terminal of the D-type flip-flop circuit 4.

The output clock φ of the clock pulse generator 5 is connected to the clock input terminal CK. The d output of the D-type flip-flop circuit 4 controls "on/off" of the switch SWZ. Here, when the d output of the D-type flip-flop circuit 4 is rHJ, the switch SW2 is turned on, and r
It is assumed that the switch SWg is "off" when the current is LJ. Note that the d output is an inverted output of the Q output. The Q output of the D-type flip-flop circuit 4 is connected to one input of the AND circuit 6. The output clock φ of the clock pulse generator 5 is applied to the other input.

The output of this AND circuit 6 is an analog-to-digital conversion output, and is output to the output terminal TM2.

The frequency divider 7 receives the output clock φ of the clock pulse generator 5.
is frequency-divided to generate a modulation signal voltage ±Ec. The output of the frequency divider 7 is transmitted through the resistor Re to the switch SW as described above.
The signal is input to the integrator 2 via the integrator 2. A capacitor C2 is inserted between the resistor Rc and the switch SW1 as necessary. The switch switching signal INT from the frequency divider 7 controls switching of the switch SW1. For example, when the switch switching signal TNT is rHJ, the analog signal under test E8 and the modulation signal voltage EC are input to the input of the integrator 2. connected, and when r I-J, the input of the integrator 2 is disconnected from the analog signal under test EX and the modulated signal voltage E.

When the measured analog signal EX is input from the input terminal T M r, the integrator 2 performs an integration operation including the measured analog signal EX in addition to the modulation signal voltage ±Ec and the reference voltage element E.

When the switch SWI is on the input side of the integrator 2, it is an analog-to-digital conversion circuit using normal feedback pulse width modulation. An integrator 2, a comparator 3, a D-type flip-flop circuit 4, and a switch SWg constitute a closed loop, and the pulse width proportional to the input is synchronized with the frequency of the modulation signal voltage E from the frequency divider 7. Output from the output terminal. Furthermore, when the switch SWI is set to the ground side, the integrator output V is applied to the capacitor C1 at d- "H". When there is a positive charge, the switch SW2 closes and the capacitor CI
Current flows in the direction of discharging.

FIG. 2 is a time chart explaining the operation of the circuit of this embodiment. In FIG. 2, INT is a switch switching signal, ±Ec is a modulation signal voltage, EX is an analog signal to be measured, V is an integrator output, and Q is a waveform of a Q output of a D-type flip-flop circuit.

A switch changeover signal INT is connected to the negative input terminal of the integrator 2.
While rHJ, the analog signal to be measured EX and the modulated signal voltage Ec are applied.

When the switch switching signal INT is "H", the circuit becomes an analog-to-digital conversion circuit using feedback pulse width modulation, so the switch SW2 is turned on by the d output of the D-type flip-flop circuit 4, and the modulation signal voltage ±E , outputs an output Q proportional to the analog signal under test EX. At this time, the modulation signal voltage ±Ec and the analog signal under test EX
is input to the integrator 2 in a stepwise manner, so the entire waveform rises slowly and settles down due to the first-order lag characteristic of the system. The pulse width of the Q output at this time is exactly an integral multiple (A times) of the clock ψ.

Next, when the switch switching signal INT is set to "■7" in synchronization with the modulation signal voltage ±Ec, the switch SW is switched to the ground side, and the modulation signal voltage regulator Ec is also connected to the measured analog signal at the input of the integrator 2. The signal Ex is also no longer input. Also, integral! it2 output V.

becomes "+", the capacitor CI remains charged, and the d output of the D-type flip-flop circuit 4 becomes [I]]. Therefore, the switch SW2 remains "on", the reference voltage element E is applied to the input of the integrator 2, and the integrator output ■.

moves toward "0". Integrator output V.

When the signal crosses "0", the comparator 3 is inverted and the Q output becomes "I," at the next rising edge of the clock φ. Therefore, switch SW2 is turned "off" and closed loop operation stops.

At this time, the integrator output ■. becomes almost "0", and the next analog-to-digital conversion can also start from "0". The time it takes for the switch switching signal rNT to become "I," and for the switch SW to turn "off" is also an integer multiple (B times) of the clock φ. Therefore, ;, I, oc A0B, and by counting A and B, the input voltage can be found.

In reality, since the Q output is A + B, it is only necessary to measure the time width of the Q output, and by calculating the AND of the Q output and the clock φ, the pulse width of the Q output can be calculated. can be measured.

The input resistor RX functions as a voltage-to-current conversion circuit for the analog signal to be measured EX, and therefore the present invention can be implemented using an active element such as an arithmetic 1'1 amplifier.

〔Effect of the invention〕

The analog-to-digital conversion circuit of the present invention has faster response characteristics without increasing the clock frequency. Therefore, auto zero when applied to measuring equipment,
Auto-calibration becomes easier, and application to scanners where input changes in steps becomes possible.

The frequency of the synchronization clock of the present invention may be as low as a frequency that can be used several times during the integration time. Therefore, the integrator does not need to have particularly excellent high-frequency characteristics. It is possible to easily speed up the process.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a time chart explaining the operation of the circuit of the present invention. DESCRIPTION OF SYMBOLS 1... Operational amplifier, 2... Integrator, 3... Comparator, 4... D-type flip-flop circuit, 5... Clock pulse generator, 6... AND circuit, 7... ...Frequency divider, TM. ...Input terminal, 7M2...Output terminal, SW +
, S W z...switch, EX...analog signal to be measured, "-E3...reference voltage, ±Ec...modulation signal voltage, TNT...switch switching signal, V.・・・
・Integrator output.

Claims (1)

[Claims] (1) An analog signal input terminal to be measured, a clock pulse generator, a frequency divider that receives the output of this clock pulse generator and generates a modulation signal to operate the system, and a reference voltage connected to a reference resistor. an input terminal, the modulation signal has a rectangular waveform with an amplitude larger than the reference voltage, and an integrator that integrates the added voltage of the reference voltage, the modulation signal, and the analog signal under test; a first switch provided between the input terminal of the integrator and the input terminal of the analog signal to be measured and selectively connecting the analog signal to be measured to the input terminal of the integrator; and the input terminal of the integrator and the reference. a second switch that opens and closes the connection with the voltage input terminal; a comparator that compares the output of the integrator with zero potential; the output of the comparator is used as one input, and the output of the clock pulse generator is used as one input; a synchronization circuit that synchronizes the output of the comparator with the clock pulse and generates a signal that opens and closes the second switch when the output of the comparator is inverted; A digital/analog circuit comprising an AND circuit in which one of the outputs and the output of the clock pulse generator are connected to two inputs, and an analog-to-digital conversion output terminal to which the output of this AND circuit is connected. In the conversion circuit, the modulation signal is connected to the measured analog signal input terminal side of the first switch, and the first switch is provided with means for switching by the output of the frequency divider. Digital to analog conversion circuit.