JPS648494B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the configuration of an analog-to-digital conversion circuit. In particular, it relates to improvements in analog-to-digital conversion circuits using feedback pulse width modulation.

[Conventional technology]

In conventional feedback pulse width modulation analog-to-digital conversion circuits, the input voltage is applied to an integrator along with a square wave clock voltage and a reference voltage switched at the comparator output. The comparator compares the integrator output with the zero level, and when it is positive, switches so that the reference voltage is negatively fed back to the integrator. The period during which the switch is in contact with the reference voltage side varies depending on the magnitude of the input voltage.
Equilibrium is reached when the average value over the period cancels out the input voltage.

In such conventional Ahallog-to-digital conversion circuits using feedback pulse width modulation, the analog-to-digital conversion system exhibits a first-order lag characteristic in response to changes in input, and the problem is that it takes time to respond.

In order to solve this problem, one proposal has already been made and put into practical use. By increasing the frequency of the synchronous clock, inserting a D-type flip-flop circuit in the feedback loop, and making one sample the product of several times of this synchronous clock, a certain degree of speed-up was achieved without reducing the resolution. (Japanese Patent Application No. 55-125009, ``Analog-digital converter and digital voltmeter'').

[Problem that the invention seeks to solve]

However, in such a conventional analog-to-digital conversion circuit using feedback pulse width modulation, the delay time cannot be reduced to zero, and it is necessary to wait for several synchronization clock cycles. Furthermore, if the frequency of the synchronous clock was increased in order to shorten this time, the high frequency characteristics of the integrator deteriorated, resulting in problems such as frequency limitations.

The present invention has been made in view of these conventional problems, and is an analog clock using feedback pulse width modulation that can speed up the response time of the input response characteristic without increasing the frequency of the synchronous clock.
The purpose is to provide a digital conversion circuit.

[Means for solving problems]

The analog-to-digital conversion circuit of the present invention is connected to an analog signal input terminal to be measured, a clock pulse generator, a frequency divider that receives the output of the clock pulse generator and generates a modulation signal to operate the system, and a reference resistor. a reference voltage input terminal, the modulation signal has a rectangular waveform with an amplitude larger than the reference voltage, and an integrator for integrating the added voltage of the reference voltage, the modulation signal, and the analog signal under test; , a first switch provided between the input terminal of the integrator and the input terminal of the analog signal to be measured and selectively connecting the analog signal to be measured to the input terminal of the integrator; a second switch that opens and closes the connection between the terminal and the reference voltage input terminal; a comparator that compares the output of the integrator with zero potential; and the output of the comparator as one input of the clock pulse generator. a synchronization circuit which takes the output of the comparator as the other input, synchronizes the output of the comparator with the clock pulse, and generates a signal to open and close the second switch when the output of the comparator is inverted; An analog/digital circuit comprising an AND circuit in which one of the outputs of the circuit and the output of the clock pulse generator are connected to two inputs, and a digital conversion output terminal to which the output of the AND circuit is connected. In the conversion circuit, the modulation signal is connected to the analog signal input terminal to be measured of the first switch, and the first switch is provided with means for switching by the output of the frequency divider. .

[Effect]

The present invention switches the input signal entering the integrator input of an analog-to-digital conversion circuit using feedback pulse width modulation and the modulation signal in synchronization with the integration time to create two operating states. It is possible to eliminate the lag characteristic and speed up the response of the analog-to-digital conversion circuit without increasing the frequency of the synchronous clock. In other words, analog-to-digital conversion is completed after each conversion, and there is no influence from the previous stage, so the response to the input is a quick-response analog-to-digital conversion circuit that has no effect even if there is a change immediately before the start of analog-to-digital conversion. Can be configured.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of an analog-to-digital conversion circuit using feedback pulse width modulation.

In FIG. 1, an input terminal _TM1 to which an analog signal under test _EX is input is connected to a negative input terminal of an operational amplifier 1 via an input resistor _RX and a switch _SW1 . A capacitor C1 is connected between the negative input terminal and output terminal of the operational amplifier ₁ to form a feedback circuit. The positive input terminal of operational amplifier 1 is grounded. Therefore, the circuit consisting of the operational amplifier 1 and its associated input circuit and feedback circuit forms an integrator 2. Similarly, a modulation signal voltage ±E _C is applied to the negative input terminal of the operational amplifier 1 via a switch SW ₁ , and a reference voltage +E _S is applied via a switch SW ₂ . Here, the resistor R _S connected between the switch SW ₂ and the reference voltage +E _S is a reference resistor for keeping the current flowing into the integrator 2 constant. As the switch SW ₂ , for example, an electronic switch using an FET is used.

The output of integrator 2 is connected to the negative input terminal of comparator 3. The positive input terminal of comparator 3 is grounded. Therefore, comparator 3 compares the output of integrator 2 with zero potential. The output of the comparator 3 is connected to the D input terminal of a D-type flip-flop circuit 4. The output clock φ of the clock pulse generator 5 is connected to the clock input terminal CK. D
The output of type flip-flop circuit 4 is switched
Controls the “on/off” of SW ₂ . Here, it is assumed that when the output of the D-type flip-flop circuit 4 is "H", the switch SW ₂ is "on", and when the output is "L", the switch SW ₂ is "off". In addition,
The Q output is an inverted output of the Q output. The Q output of the D-type flip-flop circuit 4 is connected to one input of the AND circuit 6. The output clock φ of the clock pulse generator 5 is applied to the other input.
The output of this AND circuit 6 is an analog-to-digital conversion output, and is output to the output terminal _TM2 .

A frequency divider 7 divides the output clock φ of the clock pulse generator 5 to generate a modulation signal voltage ± _EC . The output of the frequency divider 7 is input to the integrator 2 via the resistor R _C and the switch SW ₁ as described above. A capacitor _C2 is inserted between the resistor R _C and the switch _SW1 as necessary. The switch switching signal INT from the frequency divider 7 is the switch SW ₁
For example, switch switching signal
When INT is "H", the _analog signal under test _E Decoupled from _EX and modulation signal voltage ±E _C.

When the analog signal under test _EX is input from the input terminal _TM1 , the integrator 2 performs an integration operation including the analog signal under test _EX in addition to the modulation signal voltage ± _EC and the reference voltage ± _ES .

When switch SW ₁ is on the input side of integrator 2, the analog
It is a digital conversion circuit. Integrator 2, comparator 3, D-type flip-flop circuit 4 and switch
SW ₂ constitutes a closed loop, and in synchronization with the frequency of the modulation signal voltage ± _EC from the frequency divider 7, a pulse width proportional to the input is output from the Q output terminal. Furthermore, when the switch SW ₁ is set to the ground side, if there is a charge in the capacitor C ₁ that makes the integrator output V ₀ positive with = "H", the switch SW 1 is turned off until the next rising edge of the clock φ when the output of the comparator 3 is inverted. When SW ₂ closes, current flows in the direction that discharges capacitor C ₁ .

FIG. 2 is a time chart explaining the operation of the circuit of this embodiment. In FIG. 2, INT is the switch switching signal, ±E _C is the modulation signal voltage, _EX is the analog signal to be measured, V ₀ is the integrator output, and Q is the waveform of the Q output of the D-type flip-flop circuit. A switch switching signal is connected to the negative input terminal of integrator 2.
While INT is "H", the analog signal to be measured _EX and the modulation signal voltage ±E _C are applied.

When the switch switching signal INT is "H", the circuit becomes an analog-to-digital conversion circuit using feedback pulse width modulation, so the switch SW ₂ is turned "on" by the output of the D-type flip-flop circuit 4, and the modulation signal voltage ±E _C Analog signal under test in synchronization with
EX Outputs an output Q proportional to _X. At this time, the modulation signal voltage ±E _C and the analog signal to be measured _EX are input to the integrator 2 in a stepwise manner, so that the entire waveform settles down with a slow rise due to the first-order lag characteristic of the system. The pulse width of the Q output at this time is exactly an integral multiple (A times) of the clock φ.

Next, when the switch switching signal INT is set to "L" in synchronization with the modulation signal voltage ± _EC , the switch
SW ₁ is switched to the ground side, and neither the modulation signal voltage ± _EC nor the analog signal under test _EX is input to the input of the integrator 2. Further, the output _V0 of the integrator 2 becomes "+" and remains charged in the capacitor _C1 , and the Q output of the D-type flip-flop circuit 4 becomes "H". Therefore, the switch
SW ₂ remains “on”, the reference voltage ±E _S is applied to the input of integrator 2, and the integrator output V ₀ is “0”
The integrator output V ₀ moving in the direction of is "0"
When the clock φ is crossed, the comparator 3 is inverted and the φ output becomes "L" at the next rising edge of the clock φ. Therefore, switch SW ₂ is turned off and closed loop operation stops.

At this time, the integrator output V ₀ becomes almost "0", and the next analog-to-digital conversion can also start from "0". This switch switching signal INT becomes "L" and switch SW ₂ becomes "off"
The time it takes to reach φ is also an integer multiple (B times) of clock φ.
becomes. ^Therefore _{, ∫} ^INT _{( E _ _} ^_ _{_ _} ^_ _{_ C} ⁾ _dt ⁼ _{0 ∴∫} ^INT _{( E _ _} The input voltage can be determined by counting the .

In reality, the Q output is A+B, so
It is sufficient to measure the time width of the Q output, and by performing a logical product of the Q output and the clock φ and counting, the pulse width of the Q output can be measured.

The input resistor R _X functions as a voltage-to-current conversion circuit for the analog signal to be measured _EX , and therefore, the present invention can also be implemented using an active element such as an operational amplifier.

[Effects of the Invention] The analog-to-digital conversion circuit of the present invention has faster response characteristics without increasing the clock frequency. Therefore, auto-zero and auto-calibration when applied to measuring instruments are facilitated, and application to scanners where input changes in a step-like manner is also possible.

The frequency of the synchronous clock of the present invention may be as low as it can be accommodated several times during the integration time. Therefore, the integrator does not need to have particularly excellent high-frequency characteristics. It is possible to easily increase the speed of the conversion circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a time chart explaining the operation of the circuit of the present invention. 1... operational amplifier, 2... integrator, 3... comparator, 4... D-type flip-flop circuit, 5... clock pulse generator, 6... AND circuit, 7...
Frequency divider, TM ₁ ... input terminal, TM ₂ ... output terminal,
_{SW 1} , _{SW 2} ...Switch _{, E}

Claims (1)

[Claims] 1. An analog signal input terminal to be measured, a clock pulse generator, a frequency divider that receives the output of the clock pulse generator and generates a modulation signal for operating the system, and a reference resistor connected to the input terminal. a reference voltage input terminal, the modulation signal has a rectangular waveform with a larger amplitude than the reference voltage, and an integrator that integrates the added voltage of the reference voltage, the modulation signal, and the analog signal under test; a first switch provided between the input terminal of the integrator and the input terminal of the analog signal to be measured and selectively connecting the analog signal to be measured to the input terminal of the integrator; a second switch that opens and closes the connection to the reference voltage input terminal; a comparator that compares the output of the integrator with zero potential; the output of the comparator is used as one input, and the output of the clock pulse generator is is the other input, synchronizes the output of the comparator with the clock pulse, and generates a signal to open and close the second switch when the output of the comparator is inverted; An analog-to-digital conversion circuit comprising an AND circuit to which one of the outputs and the output of the clock pulse generator are connected to two inputs, and a digital conversion output terminal to which the output of the AND circuit is connected. The modulated signal is connected to the analog signal input terminal under test of the first switch, and the first switch is provided with means for switching by the output of the frequency divider. Digital conversion circuit.