JPS6255733B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to analog-to-digital converters.
More specifically, the present invention relates to improvements in feedback pulse width modulation type analog-to-digital converters.

Conventionally, feedback pulse width modulation (hereinafter simply PWM)
An analog-to-digital converter (hereinafter simply referred to as an A/D converter) is known. 1st
The figure is an electrical connection diagram showing one embodiment of such a PWM type A/D converter. In the same figure,
1 is an input terminal for the signal under test _E.sub.X. The input terminal is connected to the negative input terminal of the operational amplifier 2 via an input resistor R ₁ . Similarly, one of the positive and negative reference voltages .+-. _E.sub.S is selected by a changeover switch SW and applied to the negative input terminal of the operational amplifier via a resistor _R3 . Further, a driving pulse _P1 for driving the system is applied via a capacitor _C2 and a resistor _R2 . Here, as the switch SW, an electronic switch such as FET is used because high-speed response is required.

Between the negative input terminal and output terminal of operational amplifier 2,
A capacitor _C1 is connected to form a feedback circuit. The positive input terminal of operational amplifier 2 is grounded. The circuit 10 composed of the above-described operational amplifier 2 and its associated input circuit and feedback circuit constitutes an integrator.

3 is a comparator which receives the output of the integrator 10 at its negative input terminal. On the other hand, its positive input terminal is grounded. Therefore, the comparator 3 compares the output of the integrator 10 with zero potential. This comparator 3
The output of the switch SW is controlled by the output of the switch SW. 4 has the output of the comparator as one input, and the counting pulse P ₂
It is an AND gate that receives the other input. 5
is a counting operation circuit that counts the output pulses of the gate 4 and outputs a digital value corresponding to the voltage to be measured _Ex . Reference numeral 6 indicates an input terminal for the drive pulse _P1 , and 7 indicates an input terminal for the drive pulse _P2 . The operation of the circuit configured as described above will be explained below with reference to the timing chart shown in FIG.

A state in which the voltage to be measured _Ex is positive and the system is balanced will be explained. FIG. 2a is a timing chart showing the waveforms of various parts when _Ex is positive.
The drive pulse P ₁ described above is a pulse with a period T that changes from a constant positive value + _EC to a constant negative value _-EC with a duty of 50. Now, assume that at time t=0, the output V ₁ of the integrator 10 is positive and the changeover switch SW is set to the + _ES side. The driving pulse _P1 is
When switching from -E _C to +E _C at t=0, integrator 1
The input voltage of 0 is +E _x , +E _C , +E _S , all of which are positive. Therefore, the output V ₁ of the integrator 10 rapidly goes from positive to negative and then decreases as shown in FIG. 2a.
At time t ₁ when V ₁ falls below the zero level, the output V ₂ of the comparator 3 rises from 0 to 1.

At the moment the output _V2 of the comparator 3 rises from 0 to 1, the switch SW is switched to _{the -ES} side. In this state, the input voltages of the integrator 10 are + _EX , + _EC , -
It becomes _ES . The sum of these input voltages remains positive as long as E _C >E _S . However, since the reference voltage is reduced by an amount corresponding to the inversion from + _ES to _-ES , the output _V1 of the integrator 10 falls with a gentle slope as shown in the figure.

At time _t2 , the drive pulse _P1 is reversed from + _EC to _-EC . At this time, the input voltage of the integrator is + _EX , -
E _C , +E _S , and the sum becomes negative. Then,
The output V ₁ of the integrator 10 changes from the previous downward slope and begins to rise as shown in the figure. When this rising slope crosses the zero level at time _t3 , the output of comparator 3 is inverted from 1 to 0. Comparator 3 is 1
Let T ₁ be the period of time at the level. When the output of comparator 3 is inverted from 1 to 0, the reference voltage switches from _-ES to + _ES . In this state, the inputs to the integrator 10 become + _EX , _-EC , and + _ES . The sum of these input voltages is still negative, but its absolute value is reduced by the inversion of the reference voltage from _-ES to + _ES . Therefore, the output V ₁ of the integrator 10 rises with a slower slope than before.

At time _t4 , the drive pulse _P1 switches from _-EC to + _EC . At this time, the inputs of the integrator 10 are + _EX ,
+E _C and +E _S and return to the state at time t=0.
The output V ₂ of comparator 3 is again inverted from 0 to 1.
If the period during which V ₂ is at 0 level is T ₂ , then T ₁
The relationship +T ₂ =T holds true. T ₁ is the time during which the reference voltage - E _S is applied, T ₂ is the reference voltage +
This is the time during which E _S is applied. When the system is in equilibrium, the values of resistances R ₁ and R ₃ are R ₁ , R ₃
If we decide to use as is, the following equation holds.

E _X /R ₁ T-E _S /R ₃ T ₁ +E _S /R ₃ (T-T ₁ )
=0...(1) Note that since the integral value of the driving pulse _R1 in the period T is 0, it does not appear in equation (1). When equation (1) is solved for E _X , the following equation holds true.

_EX = (2T ₁ -T/T) R ₁ /R ₃ E _S (2) That is, the voltage to be measured _EX is proportional to (2T ₁ -T). If the gate ₄ is opened only during the period T1 when the output of the comparator 3 is at the 1 level and the counting clock _P2 is passed through, the output _V3 of the gate 4 corresponds to _T1 . Therefore, the counting calculation circuit 5 receives the V ₃ output and calculates (2T ₁ -T). Since the value when the counting clock P ₂ passes for the period T is known in advance, (2T ₁ -T) can be easily calculated. Next, (2T ₁ -T) is multiplied by a value corresponding to (R ₁ E _S /R ₃ ) to obtain the voltage to be measured _Ex as a digital value.

Although the case where the measured voltage _Ex is positive has been described above, the operation is the same when the measured voltage _Ex is negative, so the explanation will be omitted. FIG. 2b shows a timing chart when E _X is negative. In addition, E
When _X is 0, T ₁ =T ₂ .

The accuracy of such a PWM type A/D converter depends only on the reference voltage ±E _S and the resistors R ₁ and R ₃ and is not affected by the performance of other circuit components. It also has excellent features that other A/D converters do not have, such as the sensitivity and dead zone of the comparator 3 do not affect its accuracy. However, since this A/D converter is a feedback type, the response is generally slow. For example, if a step input is to be measured with an accuracy of 5 digits, at least 6 A/D conversion cycles are required. on the other hand
If the filter has characteristics to eliminate both 50Hz and 60Hz power supply noise, the integration period T needs to be 100mSEC. Therefore, the response time is 100x6=600
(mSEC) is required.

The present invention has been made in view of these points, and it performs N cycles of PWM, does not count the conversion data of M cycles (M<N) until the PWM stabilizes, and calculates the remaining (N -M) times of conversion data to obtain a digital value corresponding to the voltage to be measured _Ex , thereby realizing a PWM type A/D converter faster than the conventional one. Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is an electrical connection diagram showing one embodiment of the present invention. Components that are the same as those in FIG. 1 are designated with the same numbers. The drive pulse P ₁ is applied to the integrator 10 and is also input to the ANDOT 11 . 12
is a 1/5 frequency divider that receives the output of the gate.
13 is a 1/2 frequency divider that receives the output of the 1/5 frequency divider 12. Frequency dividers 12 and 13 constitute a 1/10 frequency divider. In FIG. 3, the frequency is divided into 1/5 and 1/2, but one 1/10 frequency divider may be used. 14 is
This is an inverter that receives the output Q _A of the 1/2 frequency divider 13. 15 is a D type flip-flop which receives the output of the inverter at its clock pulse input terminal cp. The flip-flop (hereinafter simply referred to as F/F)
A power supply voltage V _CC is connected to the D input terminal of the (abbreviated as ). A value of 5 volts is typically used as the value for V _CC . Further, the output of the F/F is the gate 1
1 is connected to the other input of 1.

4' is an AND gate that receives the output V ₂ of the comparator 3, the counting pulse P ₂ and the output Q _A of the 1/2 frequency divider. 16 is a counting circuit that receives the output of the gate. 17 is an arithmetic circuit that receives the output of the counting circuit. 18 is an input terminal to which the start pulse _P3 is input. The start pulse P ₃ is input to the frequency dividers 12 and 13, the counting circuit 16, and the F/F 15. The operation of the circuit configured in this way will be explained below.

FIG. 4 is a timing chart showing operating waveforms of each part of the circuit shown in FIG. 3. When start pulse _P3 is input, frequency divider 12, 13, F/F1
5 and counting circuit 16 are reset. F/F1
5 is reset, the output becomes 1 and gate 11 opens. When the gate 11 opens, the driving pulse P ₁
passes through the gate and is input to the 1/5 frequency divider 12.
The output of the 1/5 frequency divider 12 is input to the following 1/2 frequency divider 13. As shown in FIG. 4, the output Q _A of the 1/2 frequency divider 13 is configured to rise in synchronization with the fifth rise of the _P1 pulse. On the other hand, P ₁ pulse is
Since the voltage is constantly applied to the integrator 10, the integrator 1
A PWM cycle of 0 is constantly being performed. Therefore, even from the first pulse to the fourth pulse of P ₁ ,
PWM operation is being performed. However, PWM
Since the system has not yet reached an equilibrium state from around the first to fourth cycles, the conversion operation during this period is ignored. Note that the PWM cycle is the same as that explained in FIG. 1, so the explanation will be omitted.

When the output Q _A of the 1/2 frequency divider 13 becomes 1, the gate 4' opens and the AND of the count pulse P ₂ and the output V ₂ of the comparator 3 is output. Therefore, the output of gate 4'
V ₃ will be as shown in Figure 4. In synchronization with the rise of the 10th _P1 pulse, the output Q _A of the 1/2 frequency divider 13 is inverted from 1 to 0. When the Q _A output is reversed from 1 to 0, the gate 11 closes and the system stops operating. The counting circuit 16 receives the output V ₃ of the gate 4'
Count. The arithmetic circuit 17 receives the output of the counting circuit 16, performs arithmetic operations, and converts it into a digital value corresponding to the signal under test _Ex . Here, if the period T of the P ₁ pulse is set to 20 mSEC, the rising period T _A of the Q _A pulse becomes 100 mSEC, which can have an integral effect on both 50 Hz and 60 Hz power supply noise. . During this T _A , the pulses counted are after the system has reached an equilibrium state, so accurate measurements can be made. Furthermore, as is clear from the above explanation and the timing chart in Figure 4, the time for one A/D conversion is approximately 200 mSEC, which is approximately 200 mSEC, which is longer than the 600 mSEC of the conventional circuit described above.
It is possible to realize an A/D converter with a short conversion time of 400 mSEC.

By the way, in the circuit shown in FIG. 3, since each count value in 5 PWM cycles is all equal, the output of the counting circuit 16 always changes by 5 counts, resulting in poor resolution. In order to eliminate this drawback, random noise or a triangular wave with period T _A is applied to the integrator. When such an operation is added, the output V ₂ of the comparator 3 changes every PWM cycle, the quantization error during counting is averaged out, and the resolution is substantially improved.

FIG. 5 is an electrical connection diagram showing an embodiment of an A/D converter in which the above resolution improvement measures have been taken. Comparing FIG. 3 and FIG. 5, the only difference is that a series circuit consisting of a signal input terminal 19, a capacitor C ₃ , and a resistor R ₄ is added as an input circuit to the integrator 10, and the other circuits are the same. It is. Random noise and triangular wave signals are input from the input terminal 19.

The method of applying random noise or the like to the input of the integrator 10 in order to improve resolution has been described above, but a similar effect can also be achieved by applying phase modulation to the count pulse _P2 . Figure 6 shows
FIG. 3 is a diagram showing a count pulse waveform subjected to phase modulation.

As described above in detail, according to the present invention, an A/D converter with high response speed and high resolution can be realized.

[Brief explanation of the drawing]

FIG. 1 is an electrical connection diagram showing a conventional example of a PWM type A/D converter, and FIG. 2 is a timing chart showing waveforms at various parts. FIG. 3 is an electrical connection diagram showing one embodiment of the present invention, and FIG. 5 is an electrical connection diagram showing another embodiment. FIG. 4 is a timing chart showing operating waveforms of each part of the circuit shown in FIG. FIG. 6 is a diagram showing a count pulse waveform subjected to phase modulation. 1, 6, 19...Input terminal, 2...Operation amplifier, 3
... Comparator, 4, 4', 11... Gate, 5... Counting operation circuit, 10... Integrator, 12, 13... Frequency divider, 1
4...Inverter, 15...D type flip-flop, 16...Counting circuit, 17...Arithmetic circuit.

Claims (1)

[Claims] 1. An integrator that integrates the respective added voltages of a pair of positive and negative reference voltages that are alternately switched via a switch, a drive pulse for operating the system, and a voltage to be measured, and the output of the integrator. a comparator that compares the voltage and zero potential, a frequency divider that divides the frequency of the drive pulse in response to a start signal and outputs a pulse with a constant duty, and the respective outputs and counting pulses of the frequency divider and the comparator. a counting circuit that receives the output of the gate, and an arithmetic circuit that counts the output of the counting circuit and outputs a digital value according to the voltage to be measured. Analog to digital converter for output. 2. The analog-to-digital converter according to claim 1, wherein a phase modulation pulse is used as the counting pulse. 3 A pair of positive and negative reference voltages that are alternately switched via a switch, a drive pulse for operating the system, an integrator that integrates the summed voltage of each of the measured voltage and external signal voltage, and the output of the integrator and zero. a frequency divider that divides the frequency of the drive pulse in response to a start signal and outputs a pulse with a constant duty; and a frequency divider that receives the respective outputs and counting pulses of the frequency divider and the comparator. It consists of a gate, a counting circuit that receives the output of the gate, and an arithmetic circuit that counts the output of the counting circuit and outputs a digital value according to the voltage to be measured. Analog-to-digital converter. 4. The analog-to-digital converter according to claim 3, wherein random noise is used as the external signal voltage. 5. Claim 3, characterized in that a triangular wave whose period is the period during which the output pulse of the frequency divider is at a high level is used as the external signal voltage.
Analog-to-digital converter as described in section.