JP2000004123A - Phase difference arithmetic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To calculate and obtain the value of the absolute phase difference between two digital pulse signals which vary in frequency synchronously with each other by inputting those signals. SOLUTION: A digital pulse signal 21 inputted to an input terminal 20 is obtained as a voltage 24 representing the time for which the digital pulse signal 21 rises through an integrator 7 and held by a sample holding circuit 9. A digital pulse signal inputted to an input terminal 30 is converted by a phase difference detecting circuit 14 into a pulse signal 31 representing a phase difference, obtained as a voltage 34 representing the time for which the pulse signal 31 rises through an integrator 8, and held by a sample-and-hold circuit 10. A divider 11 divides the voltage 35 by the voltage 25 and a sample-and-hold circuit 12 holds the arithmetic result 41 and outputs the value of the phase difference to an output terminal 40 in the form of a voltage in every cycle of the input pulse signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase difference calculating circuit for calculating a phase difference between two synchronized pulse signals.

[0002]

2. Description of the Related Art Conventionally, a digital PLL (Phase
In the field of Locked Loop (PC) circuits, many phase comparators have been devised for detecting a phase difference between two digital pulse input signals (for example, Japanese Patent Application Laid-Open No. 9-28).
No. 4058). However, the purpose is to detect the phase difference between two digital pulse input signals whose frequencies are fixed, and to calculate the phase difference value for two digital pulse input signals whose frequencies fluctuate synchronously. And not.

[0003]

In recent years, in various information recording or reproducing apparatuses typified by a CD-ROM apparatus or the like, a servo technique using an optical system composed of a semiconductor laser and a photodetector has been actively used. . In the process of adjusting and assembling these optical systems to the apparatus, and in the inspection process after the assembly, two digital pulse signals generated from a signal from the photodetector indicating the relative positions of the plurality of optical system spots on the information recording medium with respect to the servo tracks are used. Calculation of the phase difference is required.

Since these two digital pulse signals are, for example, signals obtained from reflected light of two optical system spots on the information recording medium, their frequencies fluctuate irregularly and synchronously with each other. However, it is required to adjust the value of the phase difference between the two digital pulse signals so as to be the specified value, or to check that the value is the specified value.

An object of the present invention is to provide a circuit capable of calculating an absolute phase difference value irrespective of fluctuation in the frequency of two synchronized input digital pulse signals. Aim.

[0006]

In order to achieve the above object, the present invention provides a first integrator which takes two digital pulse signals as input signals and integrates a first input pulse signal, and a result of the integration. , A second integrator for integrating a second input pulse signal representing a phase difference generated from the two digital pulse signals, and a second integrator for holding the integration result. And a third sample-and-hold circuit that calculates the division of the outputs of the first and second sample-and-hold circuits and holds the result of the division. The third sample-and-hold circuit outputs the value of the phase difference for each cycle of the input pulse signal described above to form a phase difference calculation circuit.

The first integrator converts the time during which the first input pulse signal rises into a voltage, and sets the potential at the same time as the first input pulse signal falls, at the same time as the first sample.・ Holds are held every cycle by the hold circuit.

On the other hand, the second integrator converts the time during which the second input pulse signal rises into a voltage,
The potential is held by the second sample-and-hold circuit every period at the same time when the second input pulse signal falls.

The output of the first sample and hold circuit and the output of the second sample and hold circuit are input to a divider, and the output of the second sample and hold circuit is output to the output of the first sample and hold circuit. , And the result is held by the third sample-hold circuit.
The result of the division is output as a voltage every cycle of the input signal.
Represents the value of the phase difference.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the phase difference calculation circuit according to the present invention, and FIG. 2 is a time chart showing the operation of each part of the phase difference calculation circuit of FIG. In FIG. 1, 1, 2 and 13 are mono-multi vibrators,
3 and 4 are OR circuits that take a logical sum, 5 and 6 are switches,
7, 8 are integrators, 9, 10, 12 are sample and hold circuits, 11 is a divider, 14 is a circuit for generating a pulse signal representing a phase difference from two digital pulse signals, 20, 30 are input terminals, and 40 is an input terminal. Indicates an output terminal.

As shown in FIG. 1, the input terminal 20 is connected to the integrator 7, the mono-multivibrator 1, and the OR gate 3. As a result, each time the digital pulse signal 21 input to the input terminal 20 falls, a pulse signal 22 is generated from the monomultivibrator 1, the logical sum is calculated in the logical sum gate 3, and a pulse signal 23 is obtained. In the integrator 7, the switch 5 is turned off only while the pulse signal 23 is rising, and the input pulse signal 21 of the integrator 7 is integrated only while the switch 5 is off, and the voltage 24 representing the time during which the pulse signal 21 rises. Is obtained. Assuming now that the time during which the pulse signal 21 rises is T (sec) and the proportional coefficient determined by the resistor and the capacitor forming the integrator 7 is C, the potential at the time shown in the voltage 24 is CT
(V). The voltage 24 is supplied to the sample hold circuit 9.
Is input, and the potential of the CT (V) is held by the rise of the pulse signal 22. Pulse signal 22
Is synchronized with the pulse signal 21, the output signal 25 of the sample and hold circuit 9 always converts the time during which the pulse signal 21 rises into a voltage and outputs it. Hold that voltage.

On the other hand, the digital pulse signal input to the input terminal 30 is converted from the two input digital pulse signals into a pulse signal 31 representing a phase difference by the phase difference detection circuit 14, and each time the pulse signal 31 falls. The pulse signal 32 is generated from the mono-multi vibrator 2 and the logical sum is calculated in the logical sum gate 4 to obtain the pulse signal 33. In the integrator 8, the switch 6 is turned off only while the pulse signal 33 is rising, and the input pulse signal 31 of the integrator 8 is integrated only while the switch 6 is off, and the voltage 34 representing the time when the pulse signal 31 is rising. Is obtained. Now, assuming that the time during which the pulse signal 31 rises is t (sec) and the proportional coefficient determined by the resistance and the capacitor constituting the integrator 8 is C, the potential at the time shown in the voltage 34 is Ct.
(V). A voltage of 3 is applied to the sample hold circuit 10.
4 is input, and the potential of the Ct (V) is held by the rise of the pulse signal 32. Pulse signal 32
Is synchronized with the pulse signal 31, the output signal 35 of the sample and hold circuit 10 always converts the time during which the pulse signal 31 rises into a voltage and outputs it. Hold that voltage.

The outputs 25 and 35 of these two sample and hold circuits are input to the divider 11 and the potential Ct (V)
Is divided by the potential CT (V). The calculation result is output as Ct / CT at a voltage 41 and input to the sample and hold circuit 12. A pulse signal 42 generated by the monomultivibrator 13 is input to the sample and hold circuit 12 every time the pulse signal 22 falls. The sample and hold circuit 12 holds the voltage 41 at the rise of the pulse signal 42 and A value representing the phase difference, ie, t
/ T is output as a voltage for each cycle of the input pulse signal.
At this time, for example, T = 500 (μsec), t = 25
If 0 (μsec), t / T = 0.5, and the phase difference between the two input digital pulse signals is 90 °.
Therefore, t / T × 180 ° = 90 °, and by multiplying 180 to convert t / T into an angle, input terminal 2
The value of the phase difference between the two signals input to 0 and 30 is obtained.

If the frequencies of the two digital pulse signals 20 and 30 fluctuate twice in synchronization,
Time T2 (sec) during which the pulse signal 21 rises
And the voltage 34 indicating the time t2 (sec) when the pulse signal 31 rises, the pulse signal 21
And 31 rise times are each one-half as compared to before the frequency fluctuates twice, so that the output voltages 25 and 35 of the sample and hold circuits 9 and 10 are reduced.
Are Ct2 (V) and CT2 (V), respectively. At this time, Ct2 = Ct / 2 (V), CT2 = CT / 2
(V). The outputs 25 and 35 of these two sample and hold circuits are input to the divider 11 and the potential Ct2
(V) is divided by the potential CT2 (V). The calculation result is output at the voltage 41, and Ct2 / CT2 = t / T. That is, when the frequency fluctuates in synchronization with each other, the divider 11
Is the same as before the frequency fluctuates, and even if the frequencies fluctuate in synchronization with each other, the value of the absolute phase difference can be calculated and obtained.

[0015]

As described above, according to the present invention, two digital pulse signals whose frequencies fluctuate in synchronism with each other are used as input signals, and the absolute phase difference value is calculated for each cycle. You can ask.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a phase difference calculation circuit according to the present invention.

FIG. 2 is a time chart showing the operation of each part of the phase difference calculation circuit of FIG. 1;

[Explanation of symbols]

 1,2,13 Mono multivibrator 3,4 OR circuit 5,6 Switch 7,8 Analog integrator 9,10,12 Sample hold circuit 11 Analog divider 14 Phase difference detection circuit 20,30 Input terminal 40 Output terminal

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Shoji Tanaka 8-1, Koshinmachi, Takamatsu City, Kagawa Prefecture F-term in Matsushita Hisashi Denshi Kogyo Co., Ltd. (Reference) 2G030 AA01 AC05 AD04 5J060 AA05 CC01 DD00 DD02 DD08 DD43 EE15 JJ02 KK00 KK01

Claims (1)

[Claims] 1. A phase difference calculating circuit which receives two digital pulse signals as input signals and calculates a value of a phase difference between them, wherein a first integrator integrates the first input pulse signal every period. A first sample and hold circuit for holding the integration result, and a second integrator for integrating a second input pulse signal representing a phase difference generated from the two digital pulse signals for each period. A second sample-and-hold circuit that holds the result of the integration, and a third sample-and-hold circuit that calculates the division of the outputs of the first and second sample-and-hold circuits and holds the result of the division. A phase difference calculating circuit, wherein the third sample-and-hold circuit outputs a value of a phase difference for each cycle of the two digital pulse signals.