JPH0456493B2 - - Google Patents

Info

Publication number
JPH0456493B2
JPH0456493B2 JP57047854A JP4785482A JPH0456493B2 JP H0456493 B2 JPH0456493 B2 JP H0456493B2 JP 57047854 A JP57047854 A JP 57047854A JP 4785482 A JP4785482 A JP 4785482A JP H0456493 B2 JPH0456493 B2 JP H0456493B2
Authority
JP
Japan
Prior art keywords
signal
circuit
pulse
state
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57047854A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58164326A (ja
Inventor
Keiichi Suzuki
Shinji Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Ten Ltd
Original Assignee
Denso Ten Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Ten Ltd filed Critical Denso Ten Ltd
Priority to JP57047854A priority Critical patent/JPS58164326A/ja
Publication of JPS58164326A publication Critical patent/JPS58164326A/ja
Publication of JPH0456493B2 publication Critical patent/JPH0456493B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
JP57047854A 1982-03-24 1982-03-24 フエイズロツクル−プ周波数シンセサイザ Granted JPS58164326A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57047854A JPS58164326A (ja) 1982-03-24 1982-03-24 フエイズロツクル−プ周波数シンセサイザ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57047854A JPS58164326A (ja) 1982-03-24 1982-03-24 フエイズロツクル−プ周波数シンセサイザ

Publications (2)

Publication Number Publication Date
JPS58164326A JPS58164326A (ja) 1983-09-29
JPH0456493B2 true JPH0456493B2 (index.php) 1992-09-08

Family

ID=12786950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57047854A Granted JPS58164326A (ja) 1982-03-24 1982-03-24 フエイズロツクル−プ周波数シンセサイザ

Country Status (1)

Country Link
JP (1) JPS58164326A (index.php)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2941284B2 (ja) * 1988-04-27 1999-08-25 株式会社日立製作所 読み出し／書き込み回路
JP2788797B2 (ja) * 1991-06-13 1998-08-20 日本電気株式会社 位相同期ループ回路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5850054B2 (ja) * 1978-01-13 1983-11-08 沖電気工業株式会社 Ｐｌｌ回路
JPS55154808A (en) * 1979-05-22 1980-12-02 Mitsubishi Electric Corp Phase difference detecting circuit

Also Published As

Publication number Publication date
JPS58164326A (ja) 1983-09-29

Similar Documents

Publication Publication Date Title
US5285483A (en) Phase synchronization circuit
CA1282465C (en) Phase-locked loop
EP0140042A2 (en) Digital phase lock loop circuit
CA1198180A (en) Phase-locked loop having improved locking capabilities
EP0952669B1 (en) Phase comparison circuit
KR100190032B1 (ko) Efm 데이타 복원용 클럭 발생방법 및 그 방법을 수행하는 위상동기 루프
US4354124A (en) Digital phase comparator circuit
EP0376847B1 (en) PLL synthesizer
US5224086A (en) Spindle servo system for magneto-optical recording/playback apparatus
US5170135A (en) Phase and frequency-locked loop circuit having expanded pull-in range and reduced lock-in time
JPH0456493B2 (index.php)
KR970002948B1 (ko) 비트 클럭 재생 장치
US3870900A (en) Phase discriminator having unlimited capture range
US4184122A (en) Digital phase comparison apparatus
US5260841A (en) Clock extracting circuit
US4614912A (en) FM demodulator with temperature compensation
JP2533518B2 (ja) 位相同期回路
US3293555A (en) System for controlling the sampling of serially received signal elements
EP0164806A2 (en) PLL-circuit
JPH0379888B2 (index.php)
JPH04215338A (ja) Ｐｌｌ回路
JPH0363249B2 (index.php)
JP2972294B2 (ja) 位相同期回路
KR940006093Y1 (ko) 디지탈 위상 동기 회로
JPH0763148B2 (ja) 位相同期回路