JPH0456493B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a phase comparator circuit used in a phase lock loop frequency synthesizer or the like. NRZI (Not Return to
The Zero Indicating) signal will be explained with reference to FIG. The NRZI signal shown in FIG. 1 corresponds to logic "1" at its rise and fall, and corresponds to logic "0" when connected at high level and low level. like this
The NRZI signal is generated based on the signal representing the information shown in FIG. In order to read the NRZI signal, obtain the synchronization signal shown in Fig. 1 from this NRZI signal, and read the NRZI signal every period of this synchronization signal.
The level of the signal must be detected and whether there is a change in that level. FIG. 2 is a typical prior art block diagram for receiving an NRZI signal and obtaining a synchronization signal.
The frequency of the synchronization signal is the least common multiple of the frequency components included in the NRZI signal. The NRZI signal is input to a differentiating circuit 1, differentiated, and waved by a bandpass filter 2. This waveformed output from the bandpass filter 2 is waveform-shaped by a waveform shaping circuit 3 to obtain a rectangular synchronizing signal as shown in FIG. 1. FIG. 3 is a graph showing frequency components of the NRZI signal. In order to detect only frequency component 1 of the synchronization signal to be sought, bandpass filter 2 has a passband including frequency 1 and frequencies 2 to 3.
If the pass band covering frequencies 2 and 3 of band pass filter 2 is widened, there is a risk of erroneously detecting the remaining frequency components contained in the NRZI signal, so this pass band cannot be unnecessarily widened. . However, when the fluctuation of the frequency component of the NRZI signal becomes large, the frequency 1 of the synchronization signal to be determined becomes
is out of the passband of the bandpass filter 2, making it impossible to obtain a synchronizing signal. An object of the present invention is to provide a phase comparator circuit that can follow a pulse signal whose synchronization frequency fluctuates significantly, such as an NRZI signal. The present invention is a phase comparison circuit that compares the phases of a first pulse signal and a second pulse signal and derives an output for synchronizing the phase of the first pulse signal with the second pulse signal. , a first state detection means for detecting that the first pulse signal has switched from the first state to the second state; and a first state detection means for detecting that the first pulse signal has switched from the first state to the second state. a second state detecting means for detecting that the second pulse signal is in the second state at the time when the first state detecting means detects a change in the state of the first pulse signal; a first logic gate that generates an output; and a first logic gate that generates an output when the first pulse signal is in a second state when a change in state of the second pulse signal is detected by the second state detection means. a first flip-flop which is set by the output from the first logic gate and reset when the second pulse signal is in the first state; and by the output from the second logic gate. and a second flip-flop that is reset when the first pulse signal is in the first state, the first flip-flop configured such that the phase of the first pulse signal lags the phase of the second pulse signal. and the second flip-flop outputs a signal when the phase of the first pulse signal is ahead of the phase of the second pulse signal. . FIG. 4 is a block diagram showing the overall configuration of an embodiment of the present invention. In this example, motor 5
The digital audio disk 6 is rotationally driven by the digital audio disk 6.
The NRZI signal is read from. FIG. 5 is a simplified perspective view showing the motor 5 and digital audio disk 6. FIG. The signal recorded on the digital audio disk 6 is read by the detection element 7. This detection element 7 can be moved along the arm 8 in the radial direction of the digital audio disk 6. In order to keep the linear velocity of the detection element 7 with respect to the digital audio disk 6 constant, the motor 5
The speed of is changed. When the detection element 7 is located radially outward of the digital audio disk 6 compared to when it is located radially inward, the motor 5
is driven at a lower speed. The signal detected by the detection element 7 from the digital audio disk 6 is an NRZI signal. The pulse edge of this NRZI signal is detected by the detection circuit 1.
0 is detected and applied to a processing circuit 11 and also applied to a phase lock loop frequency synthesizer 12. FIG. 6 is an electric circuit diagram showing a specific configuration of the pulse edge detection circuit 10 and the phase comparison circuit 13.
FIG. 7 is a waveform diagram for explaining the operation. The detection element 7 outputs the signal as shown in FIG. 7 by the reading operation of the digital audio disk 6.
A NRZI signal is derived. Pulse edge detection circuit 1
0 includes a delay circuit 14 and an exclusive OR gate 15. The delay circuit 14
The NRZI signal is delayed as shown in FIG. 7 and output. Therefore, from the exclusive OR gate 15, when the pulse edge of the NRZI signal occurs,
In other words, at the rising and falling times, FIG.
A second pulse, a transition pulse, is derived. On the other hand, the phase lock loop frequency synthesizer 12 includes a phase comparison circuit 13, a charge pump 16, a low pass filter 17, and a voltage controlled oscillation circuit 18 which are connected in series.
From the voltage controlled oscillation circuit 18, an oscillation pulse shown in FIG. 7, which is the first pulse, is derived,
The signal is input to the first input terminal 20a of the phase comparison circuit 13 via the line 19. The transition pulse from the pulse edge detection circuit 10 is applied to the second input terminal 20b of the phase comparison circuit 13. In the phase comparison circuit 13, pulses from the first and second input terminals 20a and 20b are applied to first and second differentiating circuits 22 and 23, respectively. The first differentiating circuit 22 and the inverting delay circuit 24
AND gate 25. Therefore, the input terminal 20a shown in FIG.
The phase of the oscillation pulse from the inverter is changed in the inverting delay circuit 24 as shown in FIG. As a result, an output obtained by differentiating the rising edge of the oscillation pulse is derived from the AND gate 25, as shown in FIG. 7. The output from this first differentiating circuit 22 is
is applied to one input of the 1NAND gate 28, and the other input of the first NAND gate 28 is
The transition pulse is input. Therefore,
As shown in FIG. 7, the first NAND gate 28 is configured such that the transition pulse applied to the second input terminal 20b is at a high level, and
When the rising edge of the oscillation pulse applied to a is detected, the negative differential pulse is sent to the first flip-flop 3.
0 set terminal. The reset terminal of the first flip-flop 30 is supplied with a transition pulse from the second input terminal 20b, and therefore, as shown in FIG. 7, during the period when the transition pulse is at a high level, The set output set by the output from the first NAND gate 28 is input to the first input terminal 32a of the charge pump 16. Similarly, the second differentiating circuit 23 includes an inverting delay circuit 26
and an AND gate 27,
By the inversion delay circuit 26, the transition pulse shown in FIG. 7 is changed in phase as shown in FIG.
7, as shown in FIG.
It is applied to one input of the 2NAND gate 29. The oscillation pulse shown in FIG. 7 is input to the other input of the second NAND gate 29. Therefore, when the oscillation pulse is at a high level and the falling edge of the transition pulse is detected, the second NAND gate 29 generates a negative differential pulse as shown in FIG. It is input to the set terminal of flip-flop 31. An oscillation pulse is input to the reset terminal of the second flip-flop 31, and therefore, as shown in FIG. 7, the oscillation pulse is at a high level. The set output set by the output from the second NAND gate 29 is derived and applied to the second input terminal 32b of the charge pump 16. Therefore, as shown by period W1 in FIG. 7, when the phase of the oscillation pulse shown in FIG. 74 lags behind the phase of the transition pulse shown in FIG. The set output is derived from . For this period
A set output is derived from the second flip-flop 31 when the phase of the oscillating pulse leads the phase of the shifting pulse, as indicated by W2. The charge pump 16 has two input terminals 32.
a, 32b, and the set output of the first flip-flop 30 is applied to an input terminal 32a. Second
The set output from flip-flop 31 is applied to input terminal 32b. The set output waveforms of the first flip-flop 30 and the second flip-flop 31 are shown in FIGS. 7-8 and 12, respectively. The charge pump 16 has input terminals 32a, 32
In response to the pulse applied to b, the operation shown in Table 1 is performed and a signal is derived from the output terminal 33. First and second flip-flop 3
It is impossible for both set outputs of 0 and 31 to become high level.

[Table] A signal from the output terminal 33 of the charge pump 16 is applied to the voltage-controlled oscillation circuit 18 via the low-pass filter 17. As indicated by the above-mentioned period W2, one input terminal 2 of the phase comparison circuit 13
When the phase of the oscillation pulse applied to the input terminal 0a is in a leading phase than the transition pulse applied to the second input terminal 20b, the set output shown in FIG. 7 is applied from the second flip-flop 31 to the input terminal 32b. As a result, the output terminal 33 of the charge pump 16 becomes the ground level, and the low-pass filter 17
Since then, the level of the signal applied to the voltage controlled oscillation circuit 18 becomes low. Therefore, the oscillation frequency of the voltage controlled oscillation circuit 18 changes to become lower. In this way, the phases of the oscillation pulse and the transition pulse match. Further, as shown in the above-mentioned period W1, when the oscillation pulse has a delayed phase compared to the transition pulse, the first flip-flop 30 of the phase comparison circuit 13 provides the set output shown in FIG. 7. As a result, charge pump 16 generates a positive voltage +V1 at output terminal 33. Therefore,
From the low pass filter 17 to the voltage controlled oscillator circuit 1
The level of the signal applied to 8 becomes high. The voltage-controlled oscillation circuit 18 changes the oscillation frequency to a higher level as the level of the input signal becomes higher, so that the phases of the oscillation pulse and the transition pulse match. In this way, the phases of the oscillation pulse applied to the first input terminal 20a of the phase comparison circuit 13 and the shift pulse applied to the second input terminal 20b match, and the phase lock loop frequency synthesizer 12 is locked. achieved. The oscillation pulses from such voltage-controlled oscillator circuit 18 are also transmitted to processing circuit 11 via line 34.
given to. The processing circuit 11 uses the oscillation pulse from the voltage-controlled oscillation circuit 18 as a synchronization signal to decode the digital information represented by the NRZI signal. The first input terminal 41a of the phase comparator circuit 40 has
A reference frequency signal from a reference frequency signal generation circuit 42 is provided. This reference frequency signal generation circuit 4
2 has a crystal oscillator 43 and derives a signal having a constant and stable frequency. Phase comparison circuit 40
The oscillation output from the voltage-controlled oscillation circuit 18 of the phase lock loop frequency synthesizer 12 is applied to the other input terminal 41b of the phase lock loop frequency synthesizer 12. The phase comparison circuit 40 has a configuration similar to that of the phase comparison circuit 13 described above, and an input terminal 44a of a charge pump 45 having a configuration similar to that of the charge pump 16 described above.
44b. Subscripts a and b related to the phase comparison circuit 40 and charge pump 45 refer to the phase comparison circuit 13 and charge pump 16 described above.
correspond to each. The output from the charge pump 45 is given to a low pass filter 46. The output from this low-pass filter 46 is passed through a phase compensation circuit 47 for stabilizing the operation of the motor drive device.
It is applied to one individual contact 49 of the changeover switch 48. The other individual contact 50 of the changeover switch 48
is connected to the sliding terminal 53 of the variable resistor 51.
The output from the common contact 54 of the changeover switch 48 is
The signal is applied to the drive circuit 55. When the oscillation frequency of the voltage controlled oscillation circuit 18 becomes low, the phase comparator circuit 40
A ground level potential is applied to the input terminal 44a of.
As a result, the level of the signal applied to the drive circuit 55 via the low-pass filter 46, the phase compensation circuit 47, and the changeover switch 48 becomes high. The drive circuit 55 is connected to the drive circuit 5 from the changeover switch 48.
When the level of the signal given to 5 becomes low,
The motor 5 is driven at a low speed, and when the level of the signal given from the changeover switch 48 to the drive circuit 55 becomes high, the motor 5 is driven at a high speed accordingly. The synchronization detection circuit 60 is a voltage controlled oscillation circuit 18
The output from the reference frequency signal generating circuit 42 and the output from the reference frequency signal generating circuit 42 are received to detect whether synchronization is performed. The output from the synchronization detection circuit 60 is given to a control circuit 61. This control circuit 61 conducts the common contact 54 of the switch 48 to the individual contact 49 for switching when synchronization is established. When synchronization is not achieved, the control circuit 61 conducts the common contact 54 of the changeover switch 48 to the individual contact 50. One fixed terminal 62 of the variable resistor 51 is grounded, and the other fixed terminal 63 is applied with a positive voltage +V2. When the detection element 7 is displaced to the center of the digital audio disk 7, the sliding terminal 53 is displaced toward the grounded fixed terminal 62, and as the detection element 7 is moved outward in the radial direction of the digital audio disk 6. In conjunction with the detection element 7, the sliding terminal 53 moves toward the fixed terminal 62. In this way, a low voltage is derived from the sliding terminal 53 when the sensing element 7 is radially inward of the digital audio disk 6, and a high voltage is derived when the sensing element 7 is radially outward. When the common contact 54 of the changeover switch 48 is electrically connected to the individual contact 50, the drive circuit 55 is connected to the variable resistor 51.
In response to the output from the detecting element 7, the motor 5 is driven so that the linear velocity is constant regardless of the position of the detecting element 7. At the initial stage of starting the motor 5, the phase lock loop frequency synthesizer 12 cannot be synchronized, so the synchronization detection circuit 60 uses the control circuit 61 to change the common contact 54 of the changeover switch 48 to the individual contact 5.
Make it conductive to 0. This allows the motor 5 to reach steady operation. After the motor 5 reaches steady operation, the phase lock loop frequency synthesizer 1
2 can achieve accurate lock status.
At this time, the synchronization detection circuit 60 derives a synchronization detection signal. As a result, the control circuit 61 switches the common contact 54 of the changeover switch 48 to the individual contact 49, thereby making it conductive. In this way, at the position of the digital audio disk 6 detected by the detection element 7,
The motor 5 is driven so that a constant linear velocity corresponding to the oscillation frequency of the reference frequency signal generation circuit 42 is obtained. Furthermore, the resulting synchronization signal for reading the NRZI signal is always accurately detected by the phase lock loop frequency synthesizer 12 as described above. As described above, according to the present invention, it is possible to accurately detect a synchronization signal from a pulse signal whose frequency component fluctuates greatly, such as an NRZI signal, without error. Furthermore, according to the present invention, since the configuration is such that the comparison is performed when the pulse ends to be compared are present in both of the two input signals, periodic "1" and "0" signals are input. It can also be applied without problems to signals such as NRZI signals where "1" or "0" may be input continuously. Furthermore, the phase comparison circuit according to the present invention achieves locking between the oscillation pulse, which is the first pulse signal from the voltage controlled oscillator, and the transition pulse, which is the second pulse signal from the outside, and the phase of the two pulse signals. When the first and second flip-flops match, the first and second flip-flops do not generate any signals. Therefore, the voltage controlled oscillator controlled by the signal from the phase comparator circuit has an oscillation frequency that does not change in its locked state and can stabilize its operation. Furthermore, in the locked state, it is possible to reduce the possibility that noise in the signal from the phase comparator circuit will cause malfunctions in adjacent semiconductor circuits.

[Brief explanation of the drawing]

Fig. 1 is a waveform diagram for explaining the NRZI signal which is the background of the present invention, Fig. 2 is a block diagram of the prior art, Fig. 3 is a graph for explaining how to obtain the synchronization signal of the NRZI signal, and Fig. 4 is a waveform diagram for explaining the NRZI signal which is the background of the present invention. The figure is a block diagram showing the overall configuration of an embodiment of the present invention, and FIG.
6 is a block diagram showing the specific configuration of the pulse edge detection circuit 10 and the phase comparison circuit 13, and FIG. 7 is a perspective view showing the pulse edge detection circuit 10 and the phase comparison circuit 13. 5 is a waveform diagram for explaining the operation of the circuit 13. FIG. 5... Motor, 6... Digital audio disk, 7... Detection terminal, 10... Pulse edge detection circuit, 11... Processing circuit, 12... Phase lock loop frequency synthesizer, 13, 40...
Phase comparator circuit, 16, 45...charge pump,
17, 46...Low pass filter, 18...Voltage controlled oscillation circuit, 20a...First input terminal, 20
b...Second input terminal, 22...First differentiation circuit, 2
3... Second differentiation circuit, 28... First NAND gate, 29... Second NAND gate, 30... First flip-flop, 31... Second flip-flop, 47... Phase compensation circuit, 48... Changeover switch, 51 ...Variable resistance, 60...Synchronization detection circuit,
61...Control circuit.

Claims (1)

[Claims] 1. A phase comparison circuit that compares the phases of a first pulse signal and a second pulse signal and derives an output for synchronizing the phase of the first pulse signal with the second pulse signal. 13, wherein the first pulse signal changes from a first state L to a second state L.
a first state detection means 22 for detecting that the state H has changed from the first state L to the second state H; and
When a change in the state of the first pulse signal is detected by the second state detection means 23, which detects that the state has been switched to state H, and the first state detection means 22, the second pulse signal changes to state H. When a change in the state of the second pulse signal is detected by the first logic gate 28 which generates an output when the state is H, and the second state detection means 23, the first pulse signal changes to the second state. is set by the output from the second logic gate 29 and the first logic gate 28, and is reset when the second pulse signal is in the first state L. 1st flip-flop 30
and a second flip-flop 31 that is set by the output from the second logic gate 29 and reset when the first pulse signal is in the first state L, and the first flip-flop 30 The second flip-flop 31 outputs a signal when the phase of the first pulse signal lags the phase of the second pulse signal, and the second flip-flop 31 outputs a signal when the phase of the first pulse signal is ahead of the phase of the second pulse signal. A phase comparator circuit characterized in that it outputs a signal when