JPS58164326A - Phase-locked loop frequency synthesizer - Google Patents

Abstract

PURPOSE:To detect an NRZI signal accurately, by controlling a charge pump by signals obtained by differentiating the NRZI signal and the output signal of an oscillator, respectively. CONSTITUTION:The NRZI signal detected from a digital audio disk is inputted to a circuit 10 to detect its rising and falling points. The output signal of the voltage-controlled oscillator is inputted to a terminal 20a of a phase comparing circuit 13. The phase comparing circuit 13 has differentiating circuits 22 and 23 for differentiating signals from terminals 20a and 20b. When output pulses of the differentiating circuits and the signals from the terminals 20a and 20b are present concurrently, flip-flops 30 and 31 are set and reset. By the output of the flip-flop 30, the charge pump outputs ''0'' and by the output of the flip-flop 31, it outputs ''1'' to control the voltage-controlled oscillator, generating a synchronizing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a 7-Aids PtskV-p frequency synthesizer.
rnto Zero Indicating) signal (Fig. 1 test, te a light tA, Fig. 11 (1) f
NRZI @ No. #'i indicated by C, its rise and fall corresponds to logic "1" KN, and the duration of high νpeV and lowrepeV corresponds to logic "0"K. . Such an NRZ I signal is generated based on a signal representing information shown in FIG. 1(2). In order to read the NRZ I signal, the synchronization signal shown in FIG. 1 (3) is obtained from the NRZ I signal, and the NRZ
It is necessary to detect whether or not there is a change in the level of the A/ft ejection of No. I(, V).

FIG. 2 is a ten-step diagram of a typical advance technique for receiving Fi, NRZ I signals and obtaining synchronization signals.

The frequency of the synchronization signal is the least common multiple of the frequency components included in the NRZI signal. The NRZI signal is input to the # component circuit IK, differentiated, and converted into a P wave by bandpass filter 2. The P-wave output from the bandpass filter 2 is waveform-shaped by a waveform shaping circuit 8,
A rectangular synchronous signal as shown in FIG. 1 (3) is obtained.

@Figure 8 Ti is a graph showing the frequency components of the NRZI signal. In order to detect only the frequency component /1 of the synchronization signal to be sought, a bandpass filter 20 has a passband of frequencies f2 to f8 called frequency fit, and if the bandpass filter 20 widens the passband spanning frequencies 72 to f8, There is a risk of erroneously detecting the remaining frequency components contained in the NRZI signal, so it is best not to make this passband too wide! However, if the fluctuations of the same wave number components of the NRZI signal become large, the 0 frequency f1 of the synchronization signal to be obtained will be out of the passband of the bandpass filter 20, making it impossible to obtain the synchronization signal II! ! Become.

The purpose of the zero-starter is to provide a phase-locked sheep frequency sensor that allows the NRZI signal to be detected accurately.

FIG. 4 is a block diagram showing the overall configuration of an embodiment of the present invention. In this embodiment, the motor 5
The digital V-audio disc 6 is driven to rotate, and the NRZI signal is read from the digital V-audio disc 6.

Figure 6 shows the motor 6 and the digital audio disc 6.
FIG. The signal recorded on the digital V audio disk 6 is read by the detection element 7. This detection element 7 has arms 8iC1&
The digital V-audio disk 6 can be moved backward in the radial direction.

In order to keep the linear velocity of the detection element 7 with respect to the digital V audio disc 6 constant, the velocity of the motor 5 is changed. When the detection element 7 is radially outward of the digital audio disk 60 compared to when it is radially inward, the motor 5 is driven at a higher speed.

The signal detected by the detection element 7 from the digital V audio disc 6 is an NRZI signal. This NRZ
The path edge of the I signal is detected by a detection circuit 10 and provided to a processing circuit 11 and also to a 7A logic loop 1iil & number synthesizer 12.

Referring to FIG. 6, a concrete configuration of the bus end rut detection circuit 10 and the phase comparator circuit 18 included in the 7-speed lock V-p frequency synthesizer 12 is shown. The NRZI signal shown in FIG. 7 (1') is derived from the ejection element 7 by multiple reading operations of the digital V audio disc 6. The path V path edge detection circuit 10 consists of a delay circuit 14 and an exclusive OR gate 15, and when the path edge track of the NRZI signal occurs, that is, at the rising edge and falling edge, the ) is derived.

In the phase-locked V-de frequency synthesizer 12, a phase comparator circuit 18, a charge pump 16, a low-pass filter, and a voltage-controlled oscillation circuit 18 are connected in cascade. The oscillation output from the voltage controlled Il type oscillation circuit 18 is
The signal is input to the first input terminal 204 of the phase comparison circuit 110 via the fin 19t.

The output from the path V path edge detection circuit 10 is 1 phase comparison circuit 1
8 to the other input terminal 20b.

In the phase comparator circuit 111, first and second differentiating circuits 22 and 28 are provided to differentiate the signals from the first and second input terminals 26a and 20b, respectively. This first differentiating circuit 22 is composed of a 1-inverting circuit 24 and an AND gate 25. Similarly, the second differentiating circuit 28F! , an inverting circuit 26, and an AND gate 27. The output from the first differentiating circuit 22 and the signal from the @2 input terminal 20b are respectively input to the first NAND gate 28.

The output from the second differentiating circuit 23 and the signal from the first input weak signal 20 are input to @2NANI)'r'-to 29, respectively. In this way, from the first NAND gate 28,
The displacement pulse applied to the second input terminal 20b is at a high level and the voltage-controlled oscillator circuit 18 outputs the displacement pulse as shown in FIG.
At the falling edge of the oscillation signal shown in 3), a negative differential /%7L' is obtained as shown in FIG. 7(4). Also, from the second NAND gate 29, the voltage controlled oscillator circuit 1
During the period when the @oscillation output from 8 is at a high level, at the falling edge of the signal, V is derived by a negative differential as shown in FIG. 7 (5). @1 flip-flop 80 is set by the negative differential voltage (cis) from the first NAND gate 28 and reset by the displacement pulse from the second input terminal 20b.
Tsu f 7 a Tsubu att engineer, @2NAND gate 2
set by the negative differential pulse from 9.

The signal from the first input terminal 20a performs 13 separations.

Charge pump 16 has two input terminals 82a.

82b, and the set output of the first flop 80 is applied to an input terminal 82a. The set output from the second flip 70 and 81 is applied to an input terminal 82bK. The set output waveforms of the 17th lip-flop 8G and the 27th lip-flop 81 are shown in FIG. 7(6) and FIG. 7(7), respectively. The charge pump 16 performs the operations shown in Table 1 in response to pulses applied to the input terminals 82a and 82b, and
The signal from output terminal 88 is derived. 11!1 and the 27th lip-flop 80. It is impossible for any of the °set outputs of Ill to become high level J4/.

Table 1 A signal from the output terminal 8B of the charge pump 16 is applied to the voltage controlled oscillation circuit 18 via the low pass filter 17. Line 1 from the voltage controlled fIIJ type oscillator circuit 18 applied to one input terminal 20a of the phase comparison circuit 18
When the phase of the oscillation output via 9 is ahead of the transition pulse applied to the second input terminal 20b, the oscillation output from the 17th lip flop 180 as shown in FIG.
The set output shown is given. As a result, the output terminal 88 of the charge pump 86 becomes the ground level, and the frequency of the signal applied from the low-pass filter 17 to the voltage-controlled oscillation circuit 18 becomes low. Therefore, the oscillation frequency of the voltage controlled oscillation circuit 18 changes to become lower. This causes the oscillation output and the displacement pulse to match in phase.

Further, when the oscillation output has a delayed phase compared to the transition pulse, the set output shown in FIG. This K causes charge pump 16 to generate a positive voltage +vl at output terminal 88. The level of the signal applied from the rounding low-pass filter 17 to the voltage controlled oscillation circuit 18 becomes high. The voltage-controlled oscillation circuit 18 changes the oscillation frequency to a higher level as the level of the input signal becomes higher, so that the oscillation output and the transition pulse match in phase. In this way, the phase of the oscillation output applied to the first input terminal 20a of the phase comparison circuit 18 and the displacement pulse applied to the second input terminal 20b match, and the phase lock loop frequency V synthesizer 12 is locked. is achieved.

The output from such a voltage controlled oscillation circuit 18 is t9,
It is applied to processing circuit 11 via line 84. The processing circuit 11 uses the oscillation output from the voltage controlled oscillation circuit 18 as a synchronization signal to decode the digital information represented by the NRZI signal.

A first input terminal 41 a of the phase comparison circuit 40 is supplied with a reference frequency signal from a reference frequency signal generation circuit 42 . This reference frequency signal generation circuit 42 includes a crystal oscillator 48
The excavated output from the voltage-controlled oscillator circuit 18 of the phase-locked loop frequency synthesizer 12 is given to the other input terminal 41b of the 0-phase comparator circuit 40 which derives a signal that develops a constant and stable frequency. . The phase comparison circuit 40 has a configuration similar to that of the phase comparison circuit 18 described above, and is an input terminal 44a of a charge pump 45 having a configuration similar to that of the charge pump 16 described in item 1.

44b. Subscripts a and b related to phase comparison circuit 40 and charge pump 45 correspond to phase comparison circuit 13 and charge pump 16 described by Ail. Output dc+-pass fill from charge pump 45 46
given to. The output from this i-pass filter 46 is applied to one individual contact 49 of a changeover switch 48 via a phase compensation circuit 47 for stabilizing the operation of the motor drive device. The other individual contact 50 of the changeover switch 48 is connected to a sliding terminal 58 of a variable resistor 51. The output from the common contact 54 of the changeover switch 48 is
The signal is applied to the drive circuit 55. When the oscillation frequency of the voltage controlled oscillation circuit 18 becomes low, the phase comparison ti11@40.4
8 provides a potential of the ground level V to the charge pump 450 input terminal 44aK. Is this KA-)? Low pass filter 4
6. The repetition μ of the signal applied to the drive circuit 55 via the phase compensation circuit 47 and the changeover switch 48 becomes high.

The drive circuit 56 connects the changeover switch 48 to the drive circuit 55.
When the level of the signal given to motor 5 becomes low,
is driven at low speed, and the changeover switch 48 drives the drive circuit 6.
When the level of the signal applied to the motor 5 becomes high, the motor 6 is driven at high speed accordingly.

The synchronization detection circuit 60 receives the output from the voltage controlled oscillation circuit 18 and the output from the reference frequency signal generation circuit 42, and detects whether synchronization is performed. The output from the synchronization detection circuit 60 is given to a control circuit 61. The O9IM control circuit 61 conducts the common contact 54 of the changeover switch 48 to the individual contact 49 when synchronization is established.

When synchronization is not achieved, the control 11 circuit 61 conducts the common contact 64 of the changeover switch 48 to the individual contact 50.

One fixed terminal 6g of the variable resistor 51 is grounded, and the other fixed terminal 68 is applied with a positive voltage element v2. When the detecting element 7 is located at the center Ki of the digital audio disc 6, the sliding terminal 58 is placed in the position of the long stator 62@, and the detecting element 7 is positioned outward in the radial direction of the digital audio disc 6. As it moves, the sliding @ terminal 58 moves in conjunction with the detection element 7 and the fixed element 68i1
Move to 11I. In this way, a low voltage is derived from the sliding terminal 58 when the detection element 7 is located radially inward of the digital audio disc 60, and a high voltage 1[8:] is derived when the detection element 7 is located radially outward. Changeover switch 4
In the case where the common contact 54 of 8 is electrically connected to the individual contact 5o, the drive circuit 55 responds to the output from the variable resistor 51 to drive the motor so that the linear velocity is constant regardless of the position of the detection element 7. Drive 5.

At the initial stage of starting the motor 5, the phase lock lure 1 frequency synthesizer 12 cannot be synchronized, so the - period detection circuit 60 is controlled by the control circuit 614C to
8 common wire points 64 are electrically connected to the individual contacts 50. This allows the motor 5 to reach steady operation.

After the motor 6 reaches steady-state operation, the phase-locked loop frequency synthesizer 12 can achieve a precise locking state. This color synchronization detection circuit 6
0 derives the synchronization detection signal.

Therefore, the w control circuit 61 switches the common contact 54 of the changeover switch 48 to the individual contact 49 to make it conductive.

The motor 5 is driven so that a linear velocity corresponding to the oscillation frequency of the reference frequency signal generation circuit 42 is obtained at the position of the digital audio disk 60 detected by the detection element 7 in this manner.

The ninth synchronization signal for reading the NRZ I signal obtained by this K can always be accurately detected by the phase-locked loop frequency synthesizer 12.

As described above, according to the present invention, even if the frequency component of the NRZI signal varies greatly, it is possible to accurately detect the synchronization signal without error.

[Brief explanation of the drawing]

Figure 1 is a waveform diagram explaining the NRZI signal, which is the background of the present invention, Figure 2 is a 10-step diagram of the prior art, and Figure 8 is a graph explaining how to obtain the NRZI signal synchronization signal. , FIG. 4 is a block diagram showing the overall configuration of an embodiment of the present invention, FIG. 5 is a perspective view showing the motor 5 and the digital audio disk 6, and FIG. 6 is a pulse @ edge detection circuit lO. A concrete example of 1! and the phase comparator circuit 18! FIG. 7 is a waveform diagram for explaining the operation of the phase comparator circuit 18. 5...%-9, 6... Digital audio disk, 7... Detection element, 10... Pulse edge detection circuit, 11... Processing circuit, 12... Phase lock loop 1 frequency synthesizer , 18.40... Phase comparator circuit, 16.45... Charge pump, 17.46...
Low-pass filter, 18... Voltage controlled oscillation circuit, 2
0b...first input terminal, 20b...second input terminal,
22...First differentiator circuit, 28...Second differentiator circuit, 2
8...1st NAND gate, 29...2nd NAND gate
Gate, 80...First flip-flop, 81...
@2 flip-flop, 47...phase compensation circuit, 48
... Selector switch, 61... Cute resistor, 60...
・Synchronization detection circuit, 61...Control circuit agent Patent attorney Kei Nishi

Claims (1)

[Claims] The phase comparison circuit, the charge pump, the low-pass filter, and the @-type oscillation circuit are continuously connected in this order, and the oscillation output from the voltage side-type oscillation circuit is phase-compared. applied to the first input terminal of the circuit. The second input terminal trap of the phase comparator circuit is given an external signal, and the phase comparator circuit includes @1 and 211th dividing circuits that differentiate the signals from the first and second input terminals, respectively, and a $1 differentiating circuit. a first logic gate that generates a signal when simultaneously receiving an output from the second differentiating circuit and a signal from the second input terminal; a second logic gauge that generates a signal; 1 Set by the output from the lfi intensifier gate. The first input terminal is reset by a signal from the second input terminal.
7 lip flops 1 and. a second flip-flop set by the output from the second logic gauge and reset by the signal from the first input terminal; derives corresponding signals with different reps ν, and responds to the outputs from the voltage-controlled oscillation circuit Fi and the low-pass filter V, and matches the phase of the signal input to the second input terminal of the phase comparator circuit. A 7-engine IZROTSU CREW 1-frequency synthesizer IZER is characterized in that it derives an oscillation output having a nine-fold phase in a direction.