JPH01274516A - Encoder/decoder circuit - Google Patents

Abstract

PURPOSE:To obtain an encoder/decoder of one chip structure coping with a transfer speed of 15Mbps or over whose total power consumption is nearly 700mW by providing a circuit using the Bi-CMOS process in mixture of a bipolar and CMOS transistors for the encoder/decoder. CONSTITUTION:A data separator section comprising a VCO 1, a T-I converter 2, a charge pump 3, a phase comparator 4, a frequency comparator 5 and a synchronizing circuit 6 is formed to an IC incorporating a 2-7 encoder/decoder and a synchronizing data synchronously with the VCO clock generated by the circuit 6 is converted into an NRZ data by a 2-7 decode circuit section comprising a phase synchronizing circuit 7 and a 2-7 decoder 8. The circuit converting the NRZ data into the 2-7 code consists of the 2-7 encoder 9, an AM generation circuit 10 and a write compensation circuit 11 and the input stage of the VCO 1 consists of a MOS TR with a high input impedance and the output is given to a VCO oscillation section comprising a bipolar TR via a current mirror circuit.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a read/write circuit of a small magnetic disk device 1/L or an optical disk device, and is particularly applicable to a low power consumption, highly integrated electronic circuit. The present invention relates to an encoder/decoder circuit suitable for configuring an encoder/decoder circuit.

[Conventional technology]

The conventional device is 32D5 manufactured by 881 Company described in the above-mentioned known example.
As shown in 52, the data separator, (2,7) encoder, and decoder circuits are all composed of Bibo2 transistors, so the total power consumption is close to IW. was there.

WD (Western Digital Co., Ltd.)
nDigital) all have a 0MO8 configuration, so they can only support data separators up to 10Mbps.

[Problem to be solved by the invention]

The above conventional technology does not take into account low power consumption, has problems with reliability when it is packaged in a small package, and requires a data separator on the same chip.
However, it has been impossible to implement a write compensation circuit on the chip, since the implementation of an encoder/decoder circuit is the limit.

Also, WD's 1DC22B CMOf! In order to construct a data separator of 10 Mbps or more in a circuit with an li configuration, there is a problem with the operation speed of the transistor, so please be aware that it is not possible to construct a data separator of 15 Mbps or more according to the present invention.

The object of the present invention is to be configured on one chip and to achieve a speed of 15 Mbps.
The object of the present invention is to provide a data separator, an encoder/decoder, and a write compensation circuit that can handle the above transfer speed.

[Means to solve the problem]

The above purpose is to use bipolar transistors and MOS transistors in response to high speed, large current drive, and low power consumption in the analog circuit section of the data separator, as well as phase comparison circuits, synchronous circuits, code encoder circuits, and code decoders. The logic section of the circuit, write compensation circuit, etc. is R-configured by using a B i CMOS gate with a MOS configuration in the input stage and a Bibo, 7#f configuration in the output stage.

In other words, the VCO output f;RS of the data separator is
Since the output requires high-speed operation, it is configured with two bibor transistors. Regarding the input stage of the VCO, a MOS transistor with high input impedance is used because leakage current in the input stage deteriorates the performance of the VCO.

Next, in the large g-flow catonto-mirror circuit in the charge bong circuit, the bipolar Constructed mainly using transistors.

The other analog circuits are constructed with MOS transistors, taking advantage of the low power consumption of MOS transistors, which are required for voltage drive, compared to bipolar transistors, which are driven by current.

Next, in the phase comparator and the synchronization circuit which are the logic parts in the data separator, since there is a large difference in the operating speed of the two 1d numbers, a difference in heat generation occurs in the extreme part of the transmission path w1 of the two signals. The gate on this path is connected to the input stage by cM
By using at least one BiCMOS gate whose output stage is bipolar in OS, the influence of the gate propagation delay time due to the difference in heat generation at the poles is reduced, and the number of gate stages in the propagation paths of the two signals is equalized. The phase shift due to the delay time difference between gate propagation of two signals is minimized as much as possible.

Furthermore, the clock supply gates of the code encoder and code decoder circuits have a large output load, which causes deterioration in high-speed operation. This clock supply gate (the above-mentioned BiCMOS gate whose operating speed is less dependent on the output load) is used.

Next, the write compensation circuit detects a pattern of the encoded write code data and adds a delay amount corresponding to the pattern to the write code data. High-speed detection of the pattern is required, and high accuracy is required over a wide temperature range for the amount of delay added to the written code data. The above two requirements are satisfied by using the constituent gate KBicMOs gate in the write compensation circuit.

[Effect]

The propagation delay time of the BiCMOf9 gate is expressed by equation (1).

tpd = t, + (1/β) * (VLtsCt, /
ID) (t) t・; Delay time that does not depend on load capacitance CL ID t MOS ) Drain current VLS of poor transistor
I logic threshold voltage β; current amplification factor of pieborad 2 transistor (β-100
) On the other hand, the CMOS gate has the configuration shown in Figure 14.
, its propagation delay time is expressed by equation (2).

'p' = it + (Vl, TIICL/ID)
(2)t, ! Therefore, the propagation delay time of the BiCMOS gate is 0 MO
Compared to 8 gates, it is less affected by load capacity ich by (1/β). On the other hand, the VLT and ID mentioned above are affected by temperature! #
the propagation delay time is affected. In this case, even if there are 8 BiCMOS gates, only (1/β)
Less susceptible to shadow 4i than MOS gates.

Furthermore, since the BiCMOS gate has the configuration shown in FIG. 15, the time during which the KA current flows between the NPN transistors (76, 77) in the output stage is short (and even if the output stage uses a gate circuit with a bipolar configuration, The input stage to which the output stage is connected is
Since it has a MOM transistor configuration (7 to 7172°73), the current is almost zero. Therefore, even if a gate circuit in which the output stage has a bipolar configuration is used, the power consumption is much smaller than a gate circuit in which all bipolar transistors are configured.

Also, if the drive load of the output stage is small, 0M as shown in Figure 14.
O8) By using a gate circuit having a transistor (79.8G, 8% 82) configuration, power consumption can be reduced.

As a result of the above, BiCMO8 with bipolar and 0MO3 mixed
By providing a circuit using the 7' process, it is possible to provide a single-chip encoder/decoder circuit that consumes less than 700 mW of power and can support a transfer rate of more than 15 Mbps.

〔Example〕

An example of the present invention (example of 2-7 endeck) will be described below.
This will be explained using figures. In the figure, the area surrounded by the thick solid line is a single-chip IC (integrated circuit).

In this embodiment, (2-7) In the encoder decoder,
IE IC, VCOl, T-I conversion 2, f+-jibomp 3, phase comparator 4, frequency change comparator 5, and synchronization circuit 6
From the data separator section consisting of the phase synchronization circuit 7 and (2, 7), the synchronization data (SRD) synchronized with the VCo clock generated by the synchronization circuit 6 in the data separator section
Decoder 8 converts (2-7) f-i tNRZRD to NRZ data (2-7) Decode circuit section, then when writing data N) NfLZ data input from LZWD (2-7) Convert to code (2.7
) Encoder 9. It is composed of a λM generation circuit 10 and a write compensation circuit (write pre-competition circuit) 11.

The specific circuit configuration of the VCOl of this embodiment will be explained with reference to FIG. The input stage 12 of the vcot is composed of a MOS transistor with high input impedance, and its output is transmitted to the VCO oscillation section 14 via a current mirror circuit 15. Since the VCO oscillator 14 is required to operate at high speed,
Consists of Biborad 2 transistors.

Next, the phase comparator 4, which becomes effective when reading data, has the configuration shown in Fig. 5, and the gate with the M line and the 7-band pass filter (PF) are designed so that the output stage is Bi composed of bipolar transistors
It uses CMOS gates.

This phase comparator 4 detects the phase difference between two signals, the RAWRD signal, which is data read from the magnetic disk, and the vcooυT signal, which is the output of the VCO 1, and generates a pulse iTc with a time width corresponding to the phase difference. A sampling pulse Ts is outputted from the TD to be generated at all subsequent stages with a time difference of the pulse Tc+To.

Next, the T-I conversion (time → current conversion) 2 is as shown in FIG.
The BiCMO8 gates 32 to 54 receive the pulse of c, the 3rd integration circuit converts the TD and T'c pulse difference f:'tlt pressure, and the 3rd division circuit 5 receives the pulse of Ts.
A sample and hold circuit 3t that samples and holds the output of 0 is comprised of a voltage-current conversion circuit 65 that converts the output of the sample and hold circuit 31 into a 11E current.

The output of this T-I conversion charge pump 2 is fed to a loop filter 56 provided outside the IC, as shown in FIG.
Here, the voltage is again converted into a voltage and applied to the VCO section 1. The above is a closed loop, and finally, negative feedback is activated so that the phase difference between the two signals RAWRI and VCOOUT becomes zero.

However, when the read data RAWRJ from the disk is a synchronous pattern, the synchronous field detection circuit 67 detects that it is a synchronous field, the synchronous field counter circuit 58 confirms that it is a synchronous field, and , continue to accept N for a certain period of time. Using this confirmation time as a pulse, the synchronous field counter 58 outputs 8YNCi.
)gTEcT, 5YNCDE'l:CT
The flaw signal is connected to the PhASnSYNC input external to this IC.

Therefore, when the read data (AWRJ) from the disk is a synchronous pattern, a pulse of a certain time is input to PHASE 5YNC, and during this period, the phase comparator 4 and T-I
fifi charge pump 2 stops operating, and instead, frequency comparator 5 and charge pump 5 operate, and the frequency
Perform a number pull-in.

The frequency comparator 5 is a Bi0MO87! whose output stage has a bipolar configuration as shown in FIG. Jtsupf a tsubu 4 store 4
1 and BiCMOS gates 42 to 44, here, when the 8YNC pattern input from RAWRI) has a frequency of 1/4 of the vCO clock, the VCO
The frequency and phase differences between the 1/4 frequency divided clock and the 5YNC pattern signal input from the RAW processor are detected, and if the VCO clock is ahead, the pulse is output from the DEC output by that difference. If the vCO clock is delayed, a pulse corresponding to the difference is output from the INC output.

Next, the charge pump circuit 3 shown in FIG. 6 receives the INC (No. 6) and DEC signals.
I) E
At the time of C pulse, perform the pull-in and loop filter 6.
6. Change the magnetic pressure. The reason we used NPN bipolar transistors in the current mirror circuit is because the amount of current drawn by CPOUT is very large, so if we configure it with MOi9, the size of the transistor will be very small because gm (lance conductance) is small. This is because it becomes bigger. However, since the ti amplification rate of a bipolar PNP type transistor is extremely small, a PMOS transistor was intentionally used for the outflow.

Next, through the above loop, the cycle mantissa pull-in and phase pull-in are completed, and in the synchronization circuit 6, RAWkLD is changed to vco.
The signal DtlC synchronized with the clock is changed and inputted to the (2,7) decoder circuit 8 shown in FIG.

(2,7) The decoder circuit 8 executes the 12-bit shift register and the decoding rule shown in FIG.
) BiCMOS gates 49.50 that clock the decoder 47 and the slip-flops and shift registers.
It consists of The reason why BiCMOS gates are used here is that the load is large.

Next, when writing, the 11-bit shift register 55 as shown in FIG. 9 and the NRZ → (2, 7
) to the 2-7 encoder 5 which executes the code conversion rules;
Consisting of MOs3/05454.

The output of the 2-7 encoder 9 is input to a write compensation circuit 11 shown in FIG.

The write compensation circuit 11 includes a shift 60, a write pre-competition pattern detection circuit 61 shown in FIG. 11, and a phase shift circuit 61.

In the write compensation circuit 11, the phase shift pattern shown in FIG. One of them is detected and its phase is shifted. The timing of the phase shift is shown in FIG.

Here, N is the standard timing, El is a timing signal f whose phase is earlier than the standard timing, El is a timing signal whose phase is even earlier, and conversely, Ll is a timing signal whose phase is later than the standard timing. -L12 indicates a later timing signal. Again, shift register 6
In consideration of the large load, a BiCMO8 gate is used as the clock supply gate of 1, and a BCMOS gate is used as the gate of the route that can overcome the delay 1.

As mentioned above, by using the f3ic MO8 gate, bipolar transistor, and MO8 transistor properly for each purpose, it is possible to support high-speed transfer speeds (2-7).
) Encoder/decoder built-in data separator can be realized with low power consumption.

Here, the encoder and decoder are shown for the case of the (2-7) code, but in the case of other codes such as the (1-7), they can be similarly implemented by using the J3i CMOS gate.
It can support high-speed transfer speeds and achieve low power consumption.

Supplementary explanation of the terminals of the IC of the embodiment shown in FIG. 1 will be given below. <%1NtOUT following the terminal name represents an input/output terminal. Functional explanations are attached to each terminal name.

WRiTg (3ATff(iN); When writing, set this terminal to 1 day. This sets the 4F write state, that is, the state where the N2 signal written to the disk is converted to a 2-7 code and output. Soft selector When the address mark is written, it is set to d'', and when it is detected, it is set to @L''.

P output, 5E8Y (iN); By setting this signal to @L''' at the beginning of reading, P L is High Ga1n for input data written with a 4T (1000) sync pattern. Start frequency phase comparison.

- After synchronization, the PLL enters the phase comparison mode with normal gain by setting @H''' to this terminal.
6゜Pf3EL (iN); Shijakuω and DLYk
Match the polarity of the 2-7 code read from the disk input to the iD terminal.

VCOi N (i N) IVCOOUT4 child'fc
, connect the personal power terminal φ. The input clock to this terminal is the feedback signal of the PLL, and is synchronized with the data read from the disk.

VCOiN (iN) + ycooo'ra child i, connect to the person's power 44 child.

Shifted by the input clock of this pin. Lock synchronization circuit, decoder circuit works.

RAW 几D (iN); 2 read from the disk
At the input terminal of −7 sign, the leading edge of the input signal is the magnetization reversal timing. PiILI uses this leading edge to perform phase synchronization.

MF CLIK (iN) 1 IC (D'1kBI
il ay No. 71M.

When reading data (when reading) Other than this standard clock vCO is synchronized. Also day When writing data (at the time of writing), Also used as a write clock.

Double the data transfer rate Give the clock.

Hiro Saranori Tg (iN) + When reading, connect this terminal.
By setting H1, the read state is set, that is, the state in which the 2-7 code read from the disk is changed to an NRZ signal and output.

Also, according to the Saranohiro TE signal, Counter circuit, internal circuit clock Toggle the switch and enable the output of the Nd signal. Enable and PLL to 2-7 code Start phase synchronization for the target.

When the DLYRD (iN) + separate volume terminal is set to 1L'', the 2-7 code input from this terminal is input to the synchronous read data generation circuit.

This terminal is different from PbI2. Therefore, the phase can be adjusted using an external delay element, etc. By adjusting PJ, L Steady phase error and gate delay error Wind center due to differences etc. This can be corrected.

L (iN) to kLD8! Switch the number to input 1 to the synchronous read data generation circuit.

RESgT (iN) i Initializes the internal circuit by setting @L'' when the power is turned on.

Also, the output clock frequency of the VCO is fixed at the center frequency.

During normal operation, it is held at @h”.

C8YNC1N (iN) + 4T (1000) pattern, "f-1"'i is input to all output terminals of the external sink field detection circuit. (Soft sector/external is valid only in circuit mode). After checking the bad condition of the output @H+'' for 2 Byte period 1fj, 5YNCDETfT m is L”, NK)
After the period @L″ set in DE8MLh2 continues, ″″H
” 8YNCDH: rltcT message 4ij Ka@L'
During the period K EX 5YNCiN signal @L"K If Natsuta, the 5YNCDETEcvr signal returns to @i-1"m.

NK) DB 5hJLo(tN) + MDDE8BL
O~2 O3 terminal pMol) E 5hLt (i
N) Set the operation mode of this IC.

MODE II, 2 (iN) ell19DC erase method This IC-C- can also use hard sector mode.

*In the case of 1 hard sector, after 7 assertions of the Hiroshi TE signal, the first 1 (AwRDJrM's tray y / x y
Shite8YNC1) jiThcT No. 41 will be active@L”.

*Two frequency phase comparison modes be.

% -)” 1r RAWRJ)
Outputs only the phase difference of the signal.

Mote 2 + RAW RID (11,!=VCOi
Outputs a pulse whose time is extended by half to one cycle of VCO CLK based on the phase difference of the N signal.

When writing address mark and This terminal is activated when address mark is detected. to 1H”.

When writing an address mark, erasing continues for a period when both the input signal to this terminal and the WkLITE GATEi signal are 1H" (.

In addition, when detecting an address mark, when the main signal is @H" and the signal is @L", and the erase period is longer than 30MF CLK cycle, AMFC All 漉porgy MA&i'' is completed after the erase is completed. oυ (branch)) signal is output.

When the AMF (ADj) section S8 Hato &Tayama's) signal is output, the disk controller outputs the N's signal to 1L.

AMaRL (IN) s The sear address mark generation and detection method can be selected from the following two modes using the personal blade terminal.

*7-2 illegal pattern 2-7 Patterns that deviate from the sign rule in the Use warehouse.

LCLK2 (iN) 19 i) Fu! This is the clock used when performing J compensation, and a clock whose phase is delayed with respect to NCLK (normal clock) can be input, however, it will have a phase delay ratio higher than that with respect to Ij::IA1 (late clock 1).

This terminal becomes the TJi8T pin in the internal gate delay mode (■n signal is 1H''4λμs island signal @4''), and becomes the mode shown below.

Just in case, the internal gate delay mode When outside, the input signal to this terminal is Internal logic regardless of level The road will be in normal mode.

LCLKI (iN) JORW is the clock used when writing light bricon pensage.

A phase delay with respect to CLK Enter the tsuku.

This clock selects table 2. Use only when selected.

NCLK (iN) + 9 a) 7' jJ Input the reference phase clock used when convening 1.

Built-in gate delay CLK in upper mode Connect to the O terminal.

ECLKt(iN) This is the clock used during I2ite precompensation, and a clock whose phase is advanced relative to NI::LK is manually input. However, the phase is delayed with respect to the CLKOUT signal.

TABI9j? Ja(iN) i TAB8BL ToW
BPEIII child K! n, lH included WE (iN
) Time Of-/Phase compensation (WRITjCPMCX1MI
'EN-8TATiON) mode.

(Book 1 has two types of Glycon Bensage Cason tables.) NBZV [(iN) r Gives the parent signal to be written to the disk to this terminal. When inputting this signal, it is necessary to synchronize it with this ICO[LK. This IC inverts the input signal of this terminal once and performs 2-7 conversion.

2 (O[71'); Output terminal of the result of converting the 2-7 code read from the disk into a mouse signal.

This signal is synchronized with the IIIELK signal.

acLK (OUT) + NRZ converted when reading
A terminal that outputs a clock synchronized with RD, and when writing, divides uFOLK and outputs a t clock.

Disk controller when reading This clock captures the ancestor's nothing. When writing, use this corner glue Input in synchronization with lock. In addition The clock output from this pin is Remove the bridge when switching a be.

VCOOUT (OUT): Connect this output terminal directly to the VCOiN terminal using the VCOo output terminal.

vcoOUT (OUIIl); Connect this output terminal directly to VCOiN31 with the vcO output terminal! ! Connect to child. In addition,
This output signal is an inverted signal of VCOOU'I', but it is generated independently by the same circuit as the VCOOUT signal generation circuit using the symmetry of the internal 700 circuit.

8YNCRJ) (OUT) s VCOp o y
pte97 + sita2-7 code. This terminal is DLYkiD
When not using V4 adjustment, use DLL as a monitor pin for wind margin test. When A4 adjustment, use it as a monitor pin for wind center adjustment and adjust the phase of DLYa to 6I4.

5YNCDgrEcTcoanr soft sector mode;
Built-in 8ync field detection times.

When the output or the 5YNCiN input becomes active 1H'' for a 2-byte period, this terminal becomes 1L'' (MUD)! a Set by 8ELO~2, followed by 9 period review 1L'', then 1h''9.

Hard sector mode; RJiAD (When ATE becomes active @H'', M
At the pulse timing of WRD, this terminal becomes 'L', and the period @L" set by MODE 8EL and 2 continues, and then becomes 1H".

Note that this pin is set to 1 after RFAD GATE is asserted in both soft sector and )1-do sector modes.
It becomes active @L# only once and is then disabled until Dish 1 GIAfflE is asserted again.

Normally, connect to P'HASE 8YNC terminal.

LAT calm buttocks (otyr) + WTF at the start of writing
: A signal that is delayed by 16 FCLK cycles from the rising edge 9 of the Hiro Tg signal. During this period, the K2-7WRI'rg1) ATA output signal is in a normal signal form.

AMF (ADD section ss r/low erase mode; M
AL(K FOUND)(OU'i') AME
(M number is “H”, WRIT’E (3A
Th (No. 1 is @L” and 1) C erase period is 30 copies F
When CJ continues for more than a period, 1) this signal becomes ``H'' after C erase is completed. Also, when the M positive signal becomes L#, the main signal also becomes @L'''.

・7-2 illegal mode; When the draft Q bypass E signal becomes H" and the 7-2 illegal pattern (100000001001) is detected, this output terminal becomes @Hn and the pasting Q4E signal becomes @L" Then, the main signal also becomes @L'''.

2-7 WD (0(71') + Output terminal for the signal converted from the parent signal to the 2-7 code for writing to the disk.

CLKOUT (OUT) + 4 This is a clock output that serves as a reference when performing phase compensation (light glycan compensation) during input. This signal is used as an ECLK2 manual signal inside the IC.

Used to optimize the attenuation rate of FC and loop filters. By using this terminal, the attenuation rate can be set independently for high gain, normal gain, and high gain.

・At high gain; Built-in transistor connected to this terminal is saturated and this terminal is grounded.

- At normal gain, the built-in transistor connected to the Kayamoto terminal is cut off, and this terminal becomes a zero impedance state.

Resistor connection terminal for setting the charge pump output current during RCg high gain. This resistance value determines the Yoshi charge pump's gain.

RT: Resistance connection terminal for setting the sampling feed puff f of the C4 conversion circuit to 1 (ideal value). Determined by transfer rate.

CP OUT+ external terminal is the current input/output terminal to the loop filter. Normally, it is connected to the ViN terminal, and an external loop filter is also connected.

Built-in VCO (Voltage Con)
Trolled 0aci 1latar) control'1
Pressure input terminal. Depending on the voltage applied to this terminal, vcO
oscillation frequency changes.

Also, when the SET signal is enabled, the vCO bias voltage generated inside the IC is passed through the analog switch to the ViN
14]7x to the terminal, and vCO oscillates at the center station tlL ridge.

Usually connected to the CPOUT terminal.

RVCOs Resistor connection terminal for setting the center circumference of the VCO. Determined by transfer rate.

1) VCC + power supply terminal for digital circuit; ground terminal for digital circuit AVCC + power supply terminal for analog circuit AGND i ground terminal for analog circuit [Effects of the invention] According to the present invention, a high-speed ENDEC data separator with low consumption Since it can be realized using electricity, it can be contained in a package as a single IC, and it can be said to be an essential invention for data storage for small disks.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of the present invention. FIG. 2 is an internal configuration diagram of the vCO shown in FIG. 1. FIG. 6 is an internal configuration diagram of the frequency comparator shown in FIG. FIG. 4 is a circuit diagram of the T-I conversion charge pump shown in FIG. 1. FIG. 5 shows the s#f configuration of the frequency comparator shown in FIG. 1. FIG. 6 shows the internal configuration of the charge pump shown in FIG. FIG. 7 is a configuration diagram of the FF31IK of the 2-7 decoder shown in FIG. The Na diagram is a diagram showing the NfLZ←27 conversion table. FIG. 9 is a circuit diagram of the 2-7 encoder shown in FIG. 1. FIG. 10 is an internal configuration diagram of the write compensation circuit shown in FIG. 1. FIG. 11 is a diagram showing a write compensation pattern table. FIG. 12 is a diagram showing write compensation timing. FIG. 16 is a circuit diagram showing a Hi CM)S gate. FIG. 14 is a circuit diagram showing a CMOS gate. <・VCO12-T-I conversion? Yashhoynia', 5
- Charge pump, 4... Phase comparator, 5- Frequency comparator, 6... Clock synchronization circuit, 7- Phase synchronization, 8
-2-7 decoder,?・2-7 encoder, 11・
・Write compensation circuit, 12-・VCO input stage, 15-
force vn) i ra-a[), ta・VCOQ5i1S,
15fS-25, -BiCMD8ri-), 26-29
・Bi(M)87! j y, 27Q Tsubu, Sa-
・・Integrator circuit, 51−・Sample hold circuit, 52−
34.-B I CMOS gate, 36... Lughui kl, 57-8/nc field detection circuit, 38-
8ync field force': F/) circuit, 4G, i to B
iCM) 87sy Fu7otsu7”, 42-44 ・BiC
M) 8 gates, 45 - current construction circuit, 46...
・Shift register, 47-2-7 decoder, 48-7 lip 7Q7 gate, 49.5O-BiCND8 gate, 51
~54..., BICM) f9 gate, 55...shift register, 57...2-7 encoder.

Claims (1)

[Claims] 1. A data separator that extracts a clock synchronized with the encoded data from the encoded data reproduced from the disk, and a code that creates demodulated data from the synchronized clock output from the data separator and the encoded data. An encoder/decoder circuit comprising a decoder circuit, a code encoder circuit for modulating data from a host or disk controller into code data using a write clock having the same frequency as the synchronization clock, and a write compensation circuit for dealing with peak shifts. . An encoder/decoder circuit characterized in that at least the four circuit blocks are constructed on one chip using a BiCMOS process in which bipolar transistors and CMOS transistors can be mixed. 2. VCO (Voltage) in the data separator
2. The encoder/decoder circuit according to claim 1, wherein in the controlled oscillator, the input stage is composed of a MOS transistor having a very high input impedance, and the oscillation section is composed of a bipolar transistor capable of high-speed operation. 3. The current flowing out of the large current current mirror circuit that constitutes the charge pump circuit in the data separator is P.
2. The encoder/decoder circuit according to claim 1, wherein the encoder/decoder circuit is composed of MOS transistors, and the current drawing is composed of an NPN type bipolar transistor having a small transistor size. 4. The encoder/encoder according to claim 1, wherein in the phase comparison circuit and the synchronization circuit in the data separator, the input stage is constructed using at least one BiCMOS gate in which the CMOS output stage is constructed of bipolar.
encoder decoder circuit. 5. The encoder/decoder circuit according to claim 1, wherein the code decoder circuit, code encoder circuit, and write compensation circuit are constructed using at least one BiCMOS gate.