JP2003188683A - Analog filter circuit and disk device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a challenge in which a frequency tuning circuit with high tuning accuracy and by a simple method is desired without increasing a filter degree of a VCF (voltage-controlled filter) serving as a master VCF. <P>SOLUTION: A reference signal f<SB>0</SB>is made to pass through a digital pre-phase shifter 11 first, thereby generating clock signals of two systems having a relation of a desired phase difference (π/2 in this embodiment). One of the clock signals is input into a PFD (phase/frequency detector) 14 through a zero cross comparator 13A via the master VCF 12, and the other is input into the PFD 14 through a zero cross comparator 13B not via the VCF 12. In this way, the clock signals of the two systems in an input of the PFD 14 are made to be in phase. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog filter circuit and a disk device using the analog filter circuit, and more particularly to an analog filter circuit having a frequency tuning circuit for suppressing variations in filter characteristic values due to variations in elements and temperature characteristics of elements. The present invention relates to a filter circuit and a disk device using the filter circuit as an equalization filter circuit for a digital recording data reproducing system.

[0002]

2. Description of the Related Art Conventionally, an SCF (Switched-Capacitor) has been used as an analog integrated filter circuit mainly using active elements.
A discrete time filter circuit typified by a tor filter) and a continuous time filter circuit typified by a transconductance-C (Gm-C) filter are widely applied.

The discrete-time analog filter circuit is basically based on a sampling operation by a clock, and its characteristic frequency varies, and it is determined by a reference clock frequency with a very small variation and a ratio of capacitance element values with good matching. As a result, there is an advantage that a highly accurate filter characteristic frequency can be easily obtained. On the other hand, a pre-filter circuit is essential to prevent aliasing due to sampling operation,
Since a wide-band operational amplifier is required to achieve circuit settling within a clock cycle, power consumption tends to increase, especially in high-frequency filter circuits.

On the other hand, the continuous time filter circuit is G
Like the m-C filter, it is basically based on open loop operation, can be configured without using an operational amplifier, is suitable for speeding up, and naturally has no problem of aliasing. For this reason, the Gm-C filter and M
It can be said that an OSFET-C filter or a series of continuous time filter circuits derived from the OSFET-C filter are suitable.

However, in these continuous-time filter circuits, the basic parameter that determines the characteristic frequency is, for example, g _m / C, and in the normal manufacturing process, both transconductance g _m and capacitance C have a large variation range, and these are As a result of variation without correlation, variation in filter characteristic frequency and fluctuation range are about ± 30%. In many filter applications, this range of variation is unacceptable. Therefore, it is essential to have an automatic tuning circuit for some filter characteristic frequency.

From such a requirement, for the first time, an automatic tuning circuit which does not require an external adjusting mechanism is provided by KSTan and
Proposed by PR Gray. That is, “Fully Inte
grated Analog Filters Using Bipolar-JFET Technolog
y, ”IEEE JSSC, Dec., 1978, VCO (Voltage-C
PLL (Phase-Locked Loo) including ontrolled Oscillator)
A master / slave type automatic frequency tuning circuit by p) circuit is introduced.

FIG. 10 shows the configuration of a master / slave type automatic frequency tuning circuit using a PLL circuit including a VCO. A main filter circuit (slave) 101, which wants to tune a filter characteristic frequency such as a cutoff frequency to a desired value, controls a parameter (here, Gm) that determines the characteristic frequency in common with the master VCO 102. The master VCO 102 has a proportional relationship between the integrator that constitutes the main filter circuit 101 and its frequency characteristic, and the oscillation frequency thereof is determined by the Gm control signal as shown in the figure.

Further, the master VCO 102 is provided with a phase frequency comparator (PFD; Phase / Frequency Detector) 10
PL with 3 and low pass filter (LPF) 104
It constitutes an L circuit. This PLL circuit is a master V
In order to match the oscillation frequency of the CO 102 with the reference signal frequency, a feedback loop that controls a parameter that determines the characteristic frequency of the master VCO 102 is formed.

The frequency tuning circuit having such a configuration is
It utilizes that the parameters on the semiconductor device have low absolute value precision but very high inter-device matching precision. After all, the characteristic frequency of the main filter circuit 101, which is a slave, accurately tracks the reference signal frequency of the PLL circuit.

The Tan / Gray method described above is an excellent tuning method capable of automatically adjusting the characteristic frequency of the filter circuit with high accuracy. On the other hand, practical problems include the following points.

For example, a main filter circuit 101 and a master VCO 102 each having a Gm-C integrator as a constituent element.
In the case of, first, the filter input signal amplitude of the main filter circuit 101 is limited to a dynamic range that can satisfy the distortion characteristic allowed as a system. However, since the master VCO 102 is free-running oscillation, its amplitude is determined by the circuit gain and band of the VCO 102, and normally the oscillation is maintained in a distorted state.

As a result, the average Gm during large amplitude operation is
It is much smaller than the small signal-like Gm at the operating point (when there is no distortion), and the equivalent Gm value of the master VCO 102 and the Gm value of the main filter circuit 101 are separated.
Specifically, in the PLL circuit, the Gm control signal is obtained so that the average oscillation Gm of the master VCO 102 is equivalently lowered to obtain a desired oscillation frequency. Therefore, the characteristics of the main filter circuit 101 to which the same Gm control signal is supplied are supplied. The frequency will be much higher than the desired value.

Therefore, in the frequency tuning circuit composed of the master VCO and the PLL circuit described above, some kind of VCO oscillation amplitude limiting mechanism, that is, a mechanism for self-oscillating without distorting the waveform is indispensable. This is a big obstacle.

As a method without such a problem, H. Khor
ramabadi and PRGray are “High-Frequency CMOS Co
DLL including VCF (Voltage-Controlled Filter) in ntinuous-Time Filters, "IEEE JSSC, Dec., 1984
We have proposed a master / slave type automatic frequency tuning circuit using a (Delay-Locked Loop) circuit.

FIG. 11 shows the configuration of a master / slave type automatic frequency tuning circuit using a DLL circuit including a VCF. Similar to the Tan / Gray method, the main filter circuit (slave) 111, which wants to tune the filter characteristic frequency such as the cutoff frequency to a desired value, uses a master VCF (Voltage-Controlled) parameter (Gm here) that determines the characteristic frequency. Filter) 112 is controlled in common. The difference from the Tan / Gray method is that the master side is V
The point is not VCO but VCF.

The VCF 112 itself is also the main filter circuit 1.
Similar to 11, the filter circuit is composed of an integrator, for example. This VCF 112 is a phase comparator (PD) 113.
A DLL circuit is constructed with the low-pass filter 114. That is, in the circuit example of FIG. 11, the characteristic frequency of the VCF 112, for example, when the VCF has a low-pass filter configuration, the pole frequency changes due to control by the Gm control signal.

A known single-frequency reference signal is input to the master VCF 112. The phase comparator 113 at the next stage compares the phases of the input signal and the output signal of the VCF 112 and outputs a phase error signal according to the phase difference. After passing through the low-pass filter 114, this phase error signal determines the characteristic frequency of the master VCF 112 and the main filter circuit 111 as a Gm control signal.

As an example, the case where the master VCF 112 has a biquad configuration will be described. Its phase characteristics show that the phase delay gradually approaches 0 in the low frequency range and the phase at the pole frequency f ₀ as shown in FIG. Is delayed by π / 2,
The characteristic is such that the phase delay approaches a π in the high range.

Therefore, assuming that the reference frequency is f ₀ , a feedback loop is formed so that the phase difference between the input signals of the phase comparator 113 is exactly π / 2, so that the pole frequency of the master VCF 112 is set to f ₀ and the master VCF 112 is further set. The characteristic frequency of the main filter circuit 111, which is supplied with the same Gm control signal as the above, also tracks the reference frequency f ₀ .

As is apparent from the configuration of FIG. 11, the advantage of this method is that the problem of amplitude control for avoiding distortion is greatly alleviated because the VCO is not used. That is, since the VCF is used instead of the VCO, the amplitude of the reference signal f ₀ which is the input signal may be limited in advance.

What is important in considering the practical performance of this system is the frequency comparison in the PLL system including VCO by Tan / Gray, and as a result, the phase relationship between the VCO oscillation clock and the reference signal affects the tuning accuracy. Since there is no need to pay particular attention to the phase relationship, DLL including VCF by Khorramabadi / Gray
The method is phase comparison, and the offset of the phase comparator that causes a phase error directly affects the tuning accuracy. This will be described in detail later.

As an example of the phase comparator in the configuration of FIG. 11, for example, "Design Considerations for High-Fre" by V. Gopinathan, YPTsividis, KSTan and RK Hester.
quency Continuous-Time Filters and Implementation
of an Antialiasing Filter for Digital Video, ”IEEE
A simple XOR (exclusive OR) gate as shown in JSSC, Dec., 1990 can be used. Figure 13 Gopinathan
FIG. 14 shows an example of a frequency tuning circuit using an XOR gate as a phase comparator, and the input / output characteristics of an XOR-phase comparator (hereinafter, referred to as XOR-PD).

The reason why XOR-PD is suitable is shown in FIG.
As can be seen from the above, the error signal output when the input phase difference is π / 2 is zero. For this reason,
As shown in FIG. 12, a filter whose phase is delayed by π / 2 at a pole frequency is used as the VCF 121, and a signal passing through the filter and a signal having a phase delay of 0 bypassed are XOR-PD122 in the same phase relationship. Can be entered in. The phase error signal output from the XOR-PD 122, after passing through the low-pass filter 123, determines the characteristic frequency of the master VCF 121 and the main filter circuit as a Gm control signal.

The XOR-PD 122 operates with a waveform amplitude of digital logic level. Therefore, XOR-
A zero cross comparator 124A is provided in front of the PD 122.
124B is installed to convert the analog small-amplitude signal into a digital logic level and then input it to the XOR-PD 122.

The frequency tuning circuit having the configuration using the XOR-PD 122 has an advantage that it is simpler than any other. On the other hand, there is a practical problem in terms of frequency tuning accuracy. That is, as described above, the DLL method including the VCF is phase comparison, and the accuracy of phase lock directly affects the tuning accuracy. The DC component of the output clock of the XOR-PD 122, in other words, the clock duty becomes the phase error signal. For this reason, the symmetry of the rise and fall times is required, but it is generally difficult to manage this accurately.

The frequency tuning circuit of FIG. 13 has a finite DC gain in its feedback loop.
That is, when the input of the XOR-PD 122 has a steady phase difference (that is, corresponding to the DC input), the feedback loop becomes stable while leaving a constant input phase error. As a result, it becomes difficult to improve the phase comparison accuracy, and thus the frequency tuning accuracy.

[0027]

As a promising method capable of eliminating the above-mentioned phase comparison accuracy and the reduction in tuning accuracy due to the DC gain of the feedback loop, 3
A charge pump DLL circuit configured by an integrator using a value (UP, DOWN, HiZ) PFD and a charge pump circuit can be considered.

FIG. 15 shows the configuration of a frequency tuning circuit using this charge pump DLL circuit. In addition,
15, the same parts as those in FIG. 13 are designated by the same reference numerals. As a three-valued PFD having a small phase error, which is a constituent element, a configuration including D flip-flops 131 and 132 and an AND gate 133 is widely used because of its high performance, as shown in FIG. . FIG. 17 shows the input / output characteristics of the ternary PFD of FIG.

The charge pump circuit 126 includes a PFD 12
The phase error signal is integrated by charging / discharging the capacitance C with an output current according to the phase error signal output from 5. Therefore, if there is a slight stationary phase difference at the input of the PFD 125, the phase error is (in principle) integrated infinitely. This means that the DC gain of the feedback loop is infinite, which is a great advantage over the loop configuration that does not use the charge pump circuit 126. Therefore, the phase comparison accuracy,
As a result, it is suitable for improving frequency tuning accuracy.

Charge pump DL having such advantages
It has already been described that the three-valued PFD shown in FIG. 16 is optimal when combined with the L circuit, but as is clear from the input / output characteristics of FIG. 17, this PFD 125 is
Unlike the R-PD 122, the error signal output when the input phase difference is 0 becomes zero. Therefore, as described above, the master VC has a phase characteristic as shown in FIG. 12, that is, a filter having a phase delay of π / 2 at the pole frequency.
When used for F121, it is necessary to delay the phase of the reference signal Ref bypassed by the master VCF 121 by π / 2. Therefore, as shown in FIG. 15, it was necessary to provide the digital phase shifter 127 in the bypass path.

As is clear from the above description, the reference signal Ref on the bypass path needs to have exactly a fixed phase delay (π / 2 in the above example). That is, the digital phase shifter 127 needs to be a delay line having an accurate delay time. However, it is very difficult to achieve this in a simple way,
As a result, there is a problem in that good phase lock accuracy cannot be obtained and the frequency tuning accuracy cannot be improved even though the three-value PFD and the charge pump DLL with high phase comparison accuracy are adopted.

As a possible solution to this problem, for example, the master VCF 121 is configured to have a phase delay of 2π at the pole frequency, or in general, the filter has a differential configuration, Master VC
The phase delay at the pole frequency of F121 is π, and the digital phase shifter 127 is unnecessary by inverting the positive and negative phase terminals of its input and output.
A method in which 1 is also provided on the bypass side and one phase is advanced and the other phase is delayed so that the phase at the PFD input is in phase can be considered. However, in both cases, it is necessary to increase the total filter order of the master VCF 121, and there is a problem that the power consumption and circuit scale of the frequency tuning circuit are increased.

Therefore, the present invention is a simple method in the frequency tuning of an active filter circuit, particularly a programmable filter circuit typified by a Gm-C filter or a MOSFET-C filter, without increasing the filter order of a master VCF. It is an object of the present invention to provide an analog filter circuit having a frequency tuning circuit with high tuning accuracy and a disk device using the same.

[0034]

SUMMARY OF THE INVENTION An analog filter circuit according to the present invention comprises a tuning circuit for setting a characteristic frequency of a continuous time analog filter circuit, the tuning circuit comprising a first and a second tuning circuit based on a reference clock signal. A digital phase shifting means for outputting the second clock signal, an analog phase shifting means for shifting the first clock signal, a first clock signal passing through the analog phase shifting means, and a second phase not passing through the analog phase shifting means The phase comparison means for comparing the phases with the two clock signals and outputting the phase error signal according to the phase difference, and the characteristic frequency of the analog phase means according to the phase error signal output from the phase comparison means are controlled. Control means for controlling the first clock signal to the second clock signal, and the phase delay amount at the characteristic frequency of the analog phase shifting means. And has a configuration to have almost the same phase difference. An analog filter circuit including this tuning circuit is used in a disk device, for example, as a reproduction signal processing of high-density magnetic recording data, that is, as a continuous time equalization filter circuit which is a main element of a read channel.

In the above-structured analog filter circuit or a disk device using the analog filter circuit as an equalization filter circuit, first, in the digital phase shift means, the phase delay amount at the characteristic frequency of the analog phase shift means is substantially the same as the reference phase clock signal. Two systems of clock signals having a phase difference relationship are generated. Then, one of the clock signals of these two systems is input to the phase comparison means via the analog phase shift means, and the other is input to the phase comparison means without passing through the analog phase shift means. The phase of the clock signal becomes in-phase (just phase). As a result, good phase lock accuracy can be obtained.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a frequency tuning circuit according to an embodiment of the present invention, which is used as an automatic tuning of the characteristic frequency of a continuous time analog filter circuit as a main filter circuit.

The frequency tuning circuit according to the present embodiment comprises a front digital phase shifter 11, an analog phase shifter 12,
It has a comparator 13, a phase comparator 14, and a Gm control signal generation circuit 15 that form a DLL circuit together with the analog phase shifter 12 as basic constituent elements, and the element variation and the element with respect to the main filter circuit (slave). In order to suppress the fluctuation of the filter characteristic value due to the temperature characteristic of the above, the frequency of the characteristic frequency of the main filter circuit is automatically tuned by the analog phase shifter 12, which is a master filter circuit operating as a phase shifter in the DLL. Has become.

In this frequency tuning circuit, the reference signal f ₀ is input to the front digital phase shifter 11. The reference signal f ₀ is, for example, a crystal oscillator or a known frequency signal obtained by frequency division / multiplication based on the crystal oscillator, which is a digital logic level signal,
That is, it is a clock signal. Front digital phase shifter 11
Divides the input reference signal f ₀ into two systems of clock signals having a desired fixed phase difference relationship (0 and π / 2 in this example). A specific configuration example of the front digital phase shifter 11 will be described later.

The two clock signals output from the front digital phase shifter 11 are first of all the amplitude limiting circuit 1 having the same configuration.
Input to 6A and 16B respectively. Amplitude limiting circuit 16
A and 16B limit the two clock signals within the input signal amplitude that can satisfy the input dynamic range of the analog phase shifter 12 in the next stage, that is, the distortion performance determined by the system requirement. As described at the beginning of the prior art, these amplitude limiting circuits 16A and 16B reduce the equivalent Gm due to distortion and the Gm matching shift between the master filter circuit (analog phase shifter 12) and the main filter circuit (slave) due to it. It is installed to prevent tuning and improve tuning accuracy.

Normally, the filter circuit is made to have a differential structure to improve the power supply rejection ratio and the S / N ratio by increasing the signal amplitude. In the case of this frequency tuning circuit, the amplitude limiting circuit 16A, 16B also has a single-to-differential conversion function. Note that generally, the amplitude limiting circuits 16A and 16B and thereafter may be square waves. This is possible by configuring the filter circuit so that the harmonic component of the square wave is out of the band of the master filter circuit. If this is not the case, band limitation is applied in advance so that the input signal of the master filter circuit is composed only of the fundamental without harmonics.

The two systems of signals, whose amplitudes are limited by the amplitude limiting circuits 16A and 16B, equally pass through a differential conversion circuit, a band limiting circuit, etc., which are installed as necessary, and then one of them is converted into an analog phase shifter 12. Via the analog phase shifter 12 and the other is directly input to the comparator 13 without passing through the analog phase shifter 12. Analog phase shifter 12
Is used as the VCF (hereinafter referred to as VCF12).
Note).

The comparator 13 is composed of two zero-cross comparators 13A and 13B, and converts the input two-system signals into digital logic level signals (clock signals) again. Where VCF
As for the bypass path not passing through 12, the amplitude limiting circuit 16B and a band limiting circuit (not shown) added as necessary are installed in order to eliminate the phase difference between the two systems other than the VCF 12. However, it can be omitted depending on the required degree of required phase accuracy.

The two systems of signals passed through the comparator 13 are input to the subsequent phase comparator, for example, the PFD 14.
Specifically, a signal that has passed through the VCF 12 (hereinafter, referred to as VCF
A signal) is input to the PFD 14 as a compared signal, and a signal that does not pass through the VCF 12 (hereinafter, referred to as a Ref signal) is input to the PFD 14 as a comparison reference signal.
From here, according to the well-known operation of the charge pump DLL, the phase error is integrated by the loop filter (capacitor C), and the master filter circuit VCF12.
And a Gm control signal that determines the characteristic frequency of a main filter circuit (not shown) that is a slave filter circuit.

That is, the PFD 14 outputs a phase error signal that takes three values (UP, DOWN, HiZ (high impedance)) according to the phase error of the signals of the two systems (VCF signal and Ref signal). This phase error signal is input to the Gm control signal generation circuit 15. As the Gm control signal generation circuit 15, a charge pump (CP)
Circuit is used. A capacitor C is connected between the output end of the charge pump circuit and the ground to form a loop filter.

The charge pump DLL is configured as described above. Then, by the operation of the charge pump DLL, a Gm control signal corresponding to the phase error between the two systems of signals, that is, the VCF signal and the Ref signal is generated. This Gm control signal is VCF1 which is a master filter circuit.
2 and a main filter circuit which is a slave filter circuit.

In the frequency tuning circuit according to the present embodiment having the above-mentioned configuration, the phase of the Ref signal on the bypass path side, that is, the path side not passing through the VCF 12, passes through the VCF 12 due to the action of the front digital phase shifter 11. It is delayed from the VCF signal on the route side by π / 2 in advance. Here, the master filter circuit VCF1
2 has a phase characteristic of π / 2 at the pole frequency as shown in FIG.
When the pole frequency becomes f ₀ under the control of the Gm control signal, the input phase difference of the PFD 14 becomes zero.

As can be seen from the input / output characteristics shown in FIG.
Highly accurate phase comparison, suitable for tuning loops 3
The value PFD14 has an output of zero at this time. As a result, the tuning loop is locked. For example,
When the pole frequency is smaller than f ₀ , as shown in FIG. 12, the f ₀ frequency component signal in the VCF 12 has a phase delay of π / 2 or more, the UP signal is output from the PFD 14, and the pole frequency becomes high. Direction feedback is applied. In the opposite case, correct feedback control is similarly performed.

Compared with the conventional example, the characteristic of the frequency tuning circuit according to the present embodiment having the above-mentioned configuration is that the reference signal f ₀ is first passed through the pre-digital phase shifter 11, so that the desired phase difference (in this example, the phase difference) is obtained. , Π / 2) 2
Generating a clock signal for the system. Then, the charge pump DLL including the conventionally known three-valued PDF
By adopting the above configuration, it is possible to perform highly accurate phase comparison in the subsequent blocks. Therefore, the phase accuracy of the front digital phase shifter 11 determines the frequency tuning accuracy.

Next, the structure and operation of the front digital phase shifter 11 will be described. Front digital phase shifter 1
FIG. 2 shows a configuration example of No. 1 and FIG. 3 shows a timing chart for explaining the operation thereof. In addition, in FIG.
Waveforms A to E show signal waveforms of the respective parts A to E in FIG.

The front digital phase shifter 11 according to the present embodiment is
Three D flip-flops (hereinafter referred to as D-FF) 2
1 to 23, two AND gates 24 and 25, and four inverters 26 to 29. In the pre-digital phase shifter 11, a clock signal A having a frequency of 4f ₀ and a clock signal Ad delayed to secure a gate delay margin are used as the original clock signal.

The clock signal A becomes a clock input of the D-FF 21. The Q output of the D-FF 21 is the inverter 26
Is inverted and becomes its own D (data) input,
The inverter 2 is further connected to one input of the AND gate 24.
It is inverted by 7 and becomes one input of the AND gate 25.
The AND gates 24 and 25 both receive the clock signal Ad as the other input. The outputs B and C of the AND gates 24 and 25 become the clock inputs of the D-FFs 22 and 23, respectively.

The Q output of the D-FF 22 is the inverter 28.
It is inverted by the input signal to become its own D input, and further becomes a synchronous set input of the D-FF 23, and is derived as a clock signal D of phase 0 at frequency f ₀ . The Q output of the D-FF 23 is inverted by the inverter 29 to become its own D input, and is also derived as the clock signal E of phase π / 2 at the frequency f ₀ . That is, the clock signals D and E respectively derived from the D-FFs 22 and 23 are clock signals having a phase difference of π / 2 at the frequency f ₀ .

An important point in the front-end digital phase shifter 11 having the above structure is that the phase difference between the two clock signals D and E of the frequency f ₀ obtained as the output is the period of the clock signal Ad of the frequency 4f _0. It is a point that is accurately determined. By the way, the delay from the clock signal A to the clock signal Ad may be realized by a simple gate delay because only a timing margin is taken into consideration in consideration of the delay of the subsequent flip-flops or logic gates.

By the way, in actual design, in many cases,
An original clock is often generated from a PLL circuit using a ring oscillator VCO. In this case, a clock signal having a fixed phase difference can be directly generated by the phase difference between the phases of the multi-phase VCO. Another configuration example of the front digital phase shifter 11 utilizing this is shown in FIG.

The front digital phase shifter 11 according to the present embodiment is
For example, a ring oscillator VCO having a configuration in which four stages of differential delay cells 31 to 34 are cascaded in reverse phase and the output of the final stage differential delay cell 34 is returned in phase to the first stage differential delay cell 31.
Using the differential output of the first stage differential delay cell 31 and 3
By passing the differential output of the differential delay cell 33 at the stage through the comparators 35 and 36 for differential-single conversion, two systems of clock signals having a phase difference of π / 2 at the frequency f ₀ , as shown in FIG. The clock signals D and E in FIG.

In the front-end digital phase shifter 11 according to this other configuration example, a highly accurate fixed phase difference determined by the matching precision of the delay cells 31 to 34 constituting the VCO is provided by the cyclic property of the ring oscillator. It is possible to generate two systems of clock signals.

As the PFD 14, the ternary PFD already shown in FIG. 16 is suitable in terms of phase accuracy. However,
There are disadvantages when used in a charge pump DLL including the VCF 12. Hereinafter, this inconvenience point and the configuration of the three-value PFD for eliminating it will be described.

FIG. 5 shows the waveform of each part when the three-valued PFD according to the conventional example is operating correctly (in the correct operation sequence). The pole frequency of the main VCF is f
Higher than _0, VCF passing signal of frequency f ₀ is the phase lag is a lock point [pi / 2 or less, the PFD input with respect to the reference Ref, filter passing signal VCF is a relationship of phase lead. As a result, the PFD is DN (DOW
N) A signal is output and negative feedback is applied so as to lower the pole frequency of the main VCF.

However, as shown in FIG. 6, if the initial sequence is deviated for some reason, for example, the initial state at the time of power-on, or disturbance noise, the operation will be the opposite. Even if the frequency is higher than f ₀ , so to speak, positive feedback is applied so as to further increase the pole frequency.

When used in a VCO-PLL or in a DLL having a phase variable width of at least π / 2 or more, the conventional P
In DF, after moving in the opposite direction for one full cycle, the sequence returns to the correct sequence. However, as shown in FIG.
The phase characteristics of CF are limited to a much narrower range. As a result, the pole frequency of the filter circuit remains in a deadlock state at the lowest or highest frequency that can be set while malfunctioning.

In order to solve the above problems, the ternary PFD described below is used. In Figure 7,
The structure of the three-valued PFD concerning this example is shown. Three-valued P according to this example
The FD has two D-FFs 41 and 42 and a 4-input AND.
The gate 43 is provided.

The D-FF 41 has a VCF signal as a clock input and a logic high level (power supply voltage Vdd) as a D input. The Q output of the D-FF 41 is derived as it is as a DN signal and also becomes one input of the AND gate 43. The D-FF 42 has a Ref signal as a clock input and a logical high level as a D input. D-FF42
Q output of is directly derived as the UP signal and becomes the other input of the AND gate 43. The AND gate 43 receives the VCF signal and the Ref signal as the remaining two inputs, and supplies the output to the D-FFs 41 and 42 as an asynchronous reset signal.

The difference between the ternary PFD according to the present example and the ternary PFD according to the conventional example having the above configuration is as follows. That is,
In the three-valued PFD according to the conventional example (see FIG. 16), D is used as an input of the AND gate 43 that generates an asynchronous reset signal.
Only N and UP signals are used, and DN and UP signals are used.
When both signals are active, D-FF13
1, 132 are asynchronously reset. On the other hand, the ternary PFD according to the present example has a configuration in which the VCF signal and the Ref signal to be phase-compared are added to the input of the AND gate 43 that generates the asynchronous reset signal.
DF only when all four signals of VCF signal and Ref signal in addition to signal and UP signal become active.
F41 and 42 are asynchronously reset.

FIG. 8 shows an operation sequence of the ternary PFD according to this example. As is apparent from this operation sequence, in the three-valued PFD according to the present example, even in the initial sequence in which the malfunction mode is set, the phase is delayed among the two clock signals (VCF signal and Ref signal) to be subjected to the phase comparison. Since the reset is performed at the edge of the clock signal, the positive feedback is not applied due to the malfunction.

By adopting the above-mentioned configuration, in setting the characteristic frequency of the continuous-time analog integrated filter, it is possible to automatically set the characteristic frequency with high accuracy by a simple configuration, and to obtain a three-value PFD with high phase comparison accuracy. It is possible to realize a stable frequency tuning circuit that employs a DLL using a charge pump, has extremely few additional phase error factors, and has no possibility of malfunction.

Particularly, in the automatic tuning of the characteristic frequency of the master / slave system, the input signal amplitude of the master filter circuit can be matched with that of the slave side which is the main filter circuit, which is caused by the shift of the equivalent transconductance due to the distortion. The frequency setting error can be reduced.

Further, since the order of the master filter circuit is not unnecessarily increased and the phase comparator having the most general origin symmetry characteristic that the input phase error is zero and the error output is zero can be used. The advantages of the phase lock technology results in a wide range can be applied as they are, and as a result, it becomes possible to set the filter characteristic frequency with high accuracy and low power consumption. Since the initial phase difference of the phase comparison waveform is a reference clock with extremely high phase accuracy such as the period of the digital clock or the phase difference between the phases of the ring oscillator in the clock generation PLL, it is possible to set the filter characteristic frequency with high accuracy.

The frequency tuning circuit according to the present embodiment described above is, for example, in a high density disk device adopting the PRML system, selective gain enhancement (boost) of a high frequency signal which is indispensable for reproduction signal processing in its read channel. ) Used as a frequency tuning circuit of an equalization filter circuit having a function. FIG. 9 shows an example of the configuration of a high-density disk device adopting the PRML system.

In FIG. 9, the recording information of the disk 51 is read by the head section 52. The reproduction signal output from the head unit 52 is supplied to the equalization filter circuit 55 via the reproduction amplifier 53 and the AGC amplifier 54. The equalization filter circuit 55 performs selective gain enhancement (that is, boost) processing of the high frequency signal. For the equalization filter circuit 55, the frequency tuning circuit 56 automatically tunes the characteristic frequency in order to suppress variations in the filter characteristic value due to variations in the elements and temperature characteristics of the elements.

The reproduced signal passed through the equalization filter circuit 55 is A
It is supplied to the / D converter 57. In the clock recovery circuit 58, a clock synchronized with the output signal of the A / D converter 57 is generated based on the output signal. The generated clock is the A / D converter 57.
To the sampling clock.

The A / D converter 57 converts the reproduction signal into digital data by sampling the reproduction signal in synchronization with the sampling clock supplied from the clock recovery circuit 58. A with this A / D converter 57
The D / D-converted digital data is output to the Viterbi decoder 59.
Then, the Viterbi decoding is performed, and the demodulation circuit 60 further demodulates and outputs.

On the other hand, in the recording system (writing system),
The recording data (digital input sequence) is modulated by the modulation circuit 61, and then the writing compensation circuit 62 performs writing compensation, and then the head unit 5 is passed through the recording driver 63.
2 is supplied. Then, the head unit 52 writes (records) information on the disk 51.

In the high density disc device having the above structure,
As the equalization filter circuit 55, for example, a 7-pole 2-zero filter circuit having a Gm-C biquad filter as a constituent element is used. In addition, the equalization filter circuit 55
As the frequency tuning circuit 56 that automatically tunes the characteristic frequency, the frequency tuning circuit according to the above-described embodiment is used. Since this frequency tuning circuit is capable of setting the filter characteristic frequency with low power consumption and high accuracy, it is possible to provide a disk device with low power consumption and more excellent reproduction characteristics by using the frequency tuning circuit. Become.

[0075]

As described above, according to the present invention,
Two systems of clock signals having a desired phase difference are generated from the reference clock signal, one of them is used as the phase comparison means via the analog phase shift means, and the other is used as the phase comparison means without passing through the analog phase shift means. By inputting the respective signals, the phases of the two clock signals at the input of the phase comparison means become in-phase, and good phase lock accuracy can be obtained. Therefore, the characteristic frequency can be automatically set with a simple configuration and with high accuracy. Is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a frequency tuning circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a front digital phase shifter according to the present invention.

FIG. 3 is a timing chart for explaining the operation of the front digital phase shifter.

FIG. 4 is a block diagram showing another configuration example of the front digital phase shifter according to the present invention.

FIG. 5 is a timing chart showing a correct operation sequence of a three-valued PFD according to a conventional example.

FIG. 6 is a timing chart showing a malfunction sequence of a three-valued PFD according to a conventional example.

FIG. 7 is a block diagram showing a configuration example of a ternary PFD according to the present invention.

FIG. 8 is a timing chart showing an operation sequence of a three-valued PFD according to the present invention.

FIG. 9 is a block diagram showing an example of the configuration of a disk device according to the present invention that employs the PRML system.

FIG. 10 is a block diagram showing a configuration of a master / slave type automatic frequency tuning circuit including a PLL circuit including a VCO according to a conventional example.

FIG. 11 is a block diagram showing a configuration of a master / slave type automatic frequency tuning circuit using a DLL circuit including a VCF according to a conventional example.

FIG. 12 is a characteristic diagram showing a phase characteristic of a master VCF having a biquad configuration.

FIG. 13 is a block diagram showing a circuit example of a frequency tuning circuit using an XOR gate according to a conventional example as a phase comparator.

FIG. 14 is a characteristic diagram showing an input / output characteristic of an XOR-PD.

FIG. 15 is a block diagram showing a configuration of a frequency tuning circuit using a charge pump DLL circuit according to a conventional example.

FIG. 16 is a block diagram showing a configuration of a three-valued PFD according to a conventional example.

FIG. 17 is a characteristic diagram showing input / output characteristics of a three-valued PFD according to a conventional example.

[Explanation of symbols]

11 ... Digital phase shifter, 12 ... VCF (analog phase shifter), 13 ... Comparator, 13A, 13B ... Zero cross comparator, 14 ... Phase comparator (PFD), 15 ...
Gm control signal generation circuit (charge pump circuit), 16
A, 16B ... Amplitude limiting circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5D044 BC01 BC03 CC04 FG01 FG16                 5J098 AB15 AB16 AB32 AC02 AC09                       AC22 AD16 AD18 CA01 CA08                 5J106 AA04 CC27 CC41 CC59 DD06                       DD24 DD32 FF05 GG10 HH02                       KK05

Claims (7)

[Claims] 1. A tuning circuit for setting a characteristic frequency of a continuous-time analog filter circuit, wherein the tuning circuit outputs a first and a second clock signal based on a reference clock signal. An analog phase shift means for shifting the phase of the first clock signal; a phase of the first clock signal passing through the analog phase shift means and a phase of the second clock signal not passing through the analog phase shift means; And a phase comparison means for outputting a phase error signal corresponding to the phase difference, and a control means for controlling the characteristic frequency of the analog phase means according to the phase error signal output from the phase comparison means. The digital phase shift means includes the second clock signal with respect to the first clock signal, and the characteristic frequency of the analog phase shift means. An analog filter circuit characterized in that it has a phase difference substantially equal to the phase delay amount in. 2. The digital phase means receives a first reference clock signal as a clock input and a first D flip-flop which receives an inverted output of the first reference clock signal as a data input, and outputs the first D flip-flop as a first output. As the input of the first
A second AND clock having a second reference clock signal having a delay relationship with the second reference clock as a second input, and an inverted output of the first D flip-flop as a first input, A second AND gate having the reference clock signal as a second input, a second D flip-flop having the output of the first AND gate as a clock input, and an inverted output thereof as a data input; And a third D flip-flop having the output of the second D flip-flop as a clock input, the inverted output thereof as a data input, and the output of the second D flip-flop as a synchronous set input. Of the third D flip-flop as the phase 0 clock signal.
The analog filter circuit according to claim 1, wherein the analog filter circuit is derived as a clock signal of / 2. 3. The digital phase shift means outputs a clock signal of phase 0 and a phase π / 2 from two of the multiphase output terminals of a ring oscillator formed by connecting differential delay cells in a ring shape. 2. The analog filter circuit according to claim 1, wherein the clock signal and the clock signal are derived respectively. 4. The analog filter circuit according to claim 1, wherein the control means is composed of a charge pump circuit. 5. The continuous time analog filter and the analog phase shifter are configured by transconductance, and the control means controls transconductance values of the continuous time analog filter and the analog phase shifter. The analog filter circuit according to claim 1, wherein: 6. The first phase comparison means receives a signal to be compared as a clock input and a logic high level as a data input.
D flip-flop, a second D flip-flop having a comparison reference signal as a clock input and a logic high level as a data input, and outputs of the first and second D flip-flops, the compared signal and The comparison reference signal is input, and the gate output is input to the first and second D
AND for each asynchronous reset input of flip-flop
The analog filter circuit according to claim 1, further comprising a gate, wherein each output of the first and second D flip-flops is derived as a comparison result signal. 7. A head unit for reading recorded information from a disk, an equalization filter circuit for enhancing gain of a high frequency component of a reproduction signal output from the head unit, and a characteristic frequency of the equalization filter circuit are set. And a tuning circuit for adjusting the phase of the digital signal, wherein the tuning circuit includes a digital phase shifter for outputting first and second clock signals based on a reference signal, and an analog phase shifter for shifting the first clock signal. Means and the phase of the first clock signal that has passed through the analog phase shifting means and the phase of the second clock signal that does not pass through the analog phase shifting means, and outputs a phase error signal according to the phase difference. And a control means for controlling the characteristic frequency of the analog phase means in accordance with the phase error signal output from the phase comparison means. The digital phase shift means causes the second clock signal to have a phase difference substantially the same as the phase delay amount at the characteristic frequency of the analog phase shift means with respect to the first clock signal. Disk device.