CN115632655A - Multiphase sampling type proportional-integral double-path phase-locked loop - Google Patents

Multiphase sampling type proportional-integral double-path phase-locked loop Download PDF

Info

Publication number
CN115632655A
CN115632655A CN202211298099.9A CN202211298099A CN115632655A CN 115632655 A CN115632655 A CN 115632655A CN 202211298099 A CN202211298099 A CN 202211298099A CN 115632655 A CN115632655 A CN 115632655A
Authority
CN
China
Prior art keywords
paths
frequency
phase
path
sampling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211298099.9A
Other languages
Chinese (zh)
Inventor
徐豪杰
高翔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhejiang University ZJU
Original Assignee
Zhejiang University ZJU
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhejiang University ZJU filed Critical Zhejiang University ZJU
Priority to CN202211298099.9A priority Critical patent/CN115632655A/en
Publication of CN115632655A publication Critical patent/CN115632655A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Abstract

The invention discloses a multiphase sampling type proportional-integral two-way phase-locked loop, which comprises an n-way sampling type phase discriminator, a high-frequency parallel-serial high-pass filter, a transconductance amplifier, a filter capacitor, a voltage-controlled oscillator and a multiphase frequency divider, wherein the n-way sampling type phase discriminator is connected with the high-frequency parallel-serial high-pass filter; the high-frequency parallel-serial high-pass filter comprises n paths of switched capacitors and a bias resistor, and high-frequency information in n paths of phase discrimination information is converted into one path of parallel-serial conversion; the multiphase frequency divider divides the frequency of a high-frequency output signal of the voltage-controlled oscillator to generate n paths of sampling clocks and holding clocks which are used as the sampling clocks and the holding clocks of the n paths of sampling phase discriminators, carries out sampling type phase discrimination on n paths of reference clock signals to obtain n paths of phase discrimination results, and realizes a proportional control path in a high-frequency section through a high-frequency parallel-serial high-pass filter; meanwhile, one path of phase discrimination result passes through a transconductance amplifier with a load as a filter capacitor to realize an integral control path; the two control paths respectively control two control ends of the voltage-controlled oscillator. The invention can realize the expansion of loop bandwidth.

Description

Multiphase sampling type proportional-integral two-way phase-locked loop
Technical Field
The invention relates to the field of electronic circuits, in particular to a multiphase sampling type proportional-integral two-way phase-locked loop.
Background
The noise of a phase-locked loop is generally divided into two parts, one part being in-band noise and the other part being out-of-band noise. The in-band noise is mainly contributed by a phase detector, a charge pump and the like, and the in-band noise of the phase detector and the charge pump can be suppressed through a high-gain sampling type phase detector. The out-of-band noise is mainly contributed by the noise of the oscillator, and more oscillator noise can be suppressed by expanding the loop bandwidth of the phase-locked loop, so that lower out-of-band noise can be realized. But the maximum operating loop bandwidth that the phase locked loop can achieve is limited by the reference clock frequency. The direct use of high-frequency, expensive crystal oscillators can meet the requirements, but the cost of the system is greatly increased, so the on-chip reference clock frequency multiplication technology becomes more and more popular. However, in the existing reference clock frequency multiplication technology, the phase of the multiplied reference clock signal is often required to be very precise, otherwise the reference clock spurs of the output signal of the phase-locked loop are deteriorated. Therefore, the conventional reference clock frequency multiplication phase-locked loop can not avoid the need of calibrating the equivalent frequency multiplied reference clock.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a multiphase sampling type proportional-integral two-way phase-locked loop, which has the following specific technical scheme:
a multiphase sampling type proportional-integral two-way phase-locked loop comprises an n-way sampling type phase discriminator, a high-frequency parallel-serial high-pass filter, a transconductance amplifier, a filter capacitor, a voltage-controlled oscillator and a multiphase frequency divider; n is a positive integer;
the high-frequency parallel-serial high-pass filter comprises n paths of switched capacitors and a bias resistor, one end of each of the n paths of switched capacitors is used as an input end of n paths of phase discrimination information, and the other end of each of the n paths of switched capacitors is connected with one end of the bias resistor; the other end of the bias resistor is connected with a bias voltage; the n paths of switched capacitors are respectively started through n paths of non-overlapped holding clocks, so that high-frequency information in the n paths of phase discrimination information is converted into one path in a parallel-serial mode;
the multiphase frequency divider divides the frequency by using the high-frequency output signal of the voltage-controlled oscillator to respectively generate n paths of sampling clock signals and n paths of holding clock signals, and the n paths of sampling clock signals and the n paths of holding clock signals are respectively used as a sampling clock and a holding clock of the n paths of sampling type phase detectors to perform sampling type phase detection on n paths of reference clock signals to obtain n paths of phase detection results; the n-path phase discrimination result is filtered by the high-frequency parallel-serial high-pass filter to remove the direct-current mismatch in the n-path phase discrimination result, so that the high-frequency phase discrimination information with low loop delay is obtained, and the effect of a proportional control path is realized in a high-frequency section; meanwhile, one path of phase discrimination result passes through the transconductance amplifier with the load as the filter capacitor, so that the effect of an integral control path is realized; the proportional control path and the integral control path respectively control two control ends of the voltage-controlled oscillator.
Furthermore, the transconductance amplifier adopts a gain boosting technology.
Further, the sampling type phase detector is a switching current type sampling type phase detector.
The invention has the following beneficial effects:
(1) In the multiphase sampling type proportional-integral two-way phase-locked loop, the parallel-serial high-frequency filter combines high-frequency information in the multi-path phase discrimination information into one path, and the effect of a proportional control path is realized in a high-frequency section; one path of phase discrimination result passes through the transconductance amplifier with the load of the filter capacitor, so that the effect of an integral control path is realized; namely, the area of the loop filter is greatly reduced by adopting proportional integral type two-way control. And because the bias voltage of the high-frequency parallel-serial high-pass filter determines, the proportional path does not basically influence the locking point of the loop, and the locking point of the loop is determined by the integral path. Therefore, equivalent frequency multiplication of the phase demodulation frequency of the phase locked loop can be realized by using relatively inaccurate multiphase reference clock input signals, the loop bandwidth can be expanded, and meanwhile, the deterioration of the phase error of the input reference clock to the output reference stray is avoided.
(2) The invention reduces the requirement on the phase precision of the reference clock in the traditional reference clock frequency multiplication technology, thereby greatly simplifying the design of the multiphase reference clock circuit.
(3) The invention can expand the loop bandwidth of the phase-locked loop, thereby suppressing more noises of the oscillator.
(4) The invention adopts a multiphase sampling phase demodulation mode, so that the time sequence requirement and the power consumption of the multiphase sampling phase-locked loop are relatively reduced compared with the traditional phase-locked loop with high-frequency reference clock signal input.
Drawings
FIG. 1 is a system architecture diagram of the present invention.
Fig. 2 is a high frequency parallel-to-serial high pass filter.
Fig. 3 is a waveform diagram of a multiphase sampling phase-locked loop (four phases for example).
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments, and the objects and effects of the present invention will be more apparent, it being understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.
As shown in fig. 1, the multiphase sampling type proportional-integral two-way phase-locked loop of the present invention includes a multi-sampling type phase detector, a high frequency parallel-to-serial high pass filter, a transconductance amplifier, a filter capacitor, a voltage controlled oscillator, and a multiphase frequency divider. Wherein ck ref <n:1>For n multiphase reference clock signals, ck samp <n:1>For n multiphase sampling clock signals ck hold <n:1>Holding clock signals, V, for n multiphase non-overlapping clock signals C,I Control signal of path for integral control of voltage-controlled oscillator, V C,P Proportional control path control signal, ck, for voltage-controlled oscillator VCO For the voltage controlled oscillator to output the clock signal, n is a positive integer.
As shown in fig. 2, the high-frequency parallel-to-serial high-pass filter includes n-way switched capacitors and a bias resistor, one end of each of the n-way switched capacitors is used as an input end of n-way phase discrimination information, and the other end of each of the n-way switched capacitors is connected to one end of the bias resistor; the other end of the bias resistor is connected with a bias voltage; the n paths of switched capacitors are respectively started through n paths of non-overlapped holding clocks, and high-frequency information in the n paths of phase discrimination information is converted into one path in a parallel-serial mode.
As shown in fig. 1, the multiphase frequency divider divides frequency by using a high-frequency output signal of the voltage-controlled oscillator, generates n sampling clock signals and n holding clock signals, respectively, and performs sampling type phase discrimination on n reference clock signals as a sampling clock and a holding clock of the n sampling type phase discriminator to obtain n phase discrimination results; filtering direct-current mismatch quantity in the n-path phase discrimination results by the n-path phase discrimination results through a high-frequency parallel-serial high-pass filter to obtain high-frequency phase discrimination information with low loop delay, and realizing the effect of a proportional control path in a high-frequency section; meanwhile, one path of phase discrimination result passes through the transconductance amplifier with the load as a filter capacitor, so that the effect of an integral control path is realized; and the proportional control path and the integral control path respectively control two control ends of the voltage-controlled oscillator.
Preferably, the transconductance amplifier is a transconductance amplifier adopting a gain boosting technology. The sampling type phase discriminator is a switching current type sampling type phase discriminator.
This is exemplified by a four-phase clock input, although other numbers of multi-phase reference clock inputs are possible.
The waveforms of the nodes of the four-phase sampling phase-locked loop are shown in fig. 3, where falling edge sampling is taken as an example, and rising edge sampling is similar. As can be seen from fig. 3, in one reference clock cycle, the multi-path sampling type phase detector performs phase detection for multiple times, so that the phase detection frequency is increased. Meanwhile, after sampling of each sampling type phase discriminator is finished, the sampled signals are immediately held by the holding clock and are updated to the high-frequency parallel-serial high-pass filter, and therefore loop delay is avoided. However, due to the characteristics of the zero-order hold sampling, the phase shift of the loop increases with the increase of the hold time, so that the hold time in the multiphase sampling type phase-locked loop needs to be correspondingly reduced by using a parallel-to-serial manner, which is implemented by a high-frequency parallel-to-serial high-pass filter.
Ideally, the mismatch between the multiphase reference signals can be considered as a dc-to-low frequency offset and varies slowly with non-ideal factors such as temperature. Due to the characteristic of mismatch, the high-pass filtering can be used to filter out the low-frequency detuning amount, so that only the high-frequency useful signal is obtained. Generally, the output jitter of the phase-locked loop is mainly determined by the phase noise in the range from one tenth of the loop bandwidth to ten times of the loop bandwidth, so that the high-frequency phase discrimination information is the key. The deviation between the multi-path phase detection information of the low-frequency phase detection result can be ignored, so that the low-frequency signals of all the paths of phase detection results are considered to be the same in fact. And the bias voltage of each path of high-pass filter is the same, so that the resistors of the high-frequency filter can be shared, each path of high-pass filter multiplexes the same bias resistor, and high-frequency phase discrimination information is connected in parallel and in series through multi-path selection, so that the area of the bias resistor can be greatly reduced. Meanwhile, the phase-locked loop also needs to provide low-frequency loop gain to realize frequency locking and phase locking of the phase-locked loop, so that one of the multiphase phase discrimination results is taken out and passes through the transconductance amplifier to realize an integral path and provide low-frequency loop gain. Therefore, equivalent frequency multiplication of the phase demodulation frequency of the phase locked loop can be realized by using relatively inaccurate multiphase reference clock input signals, the loop bandwidth can be expanded, and the deterioration of the phase error of the input reference clock to the output reference stray is avoided.
Meanwhile, the design adopts proportional integral type two-way control, so that the area of the loop filter is greatly reduced. And because the bias voltage of the high-frequency parallel-serial high-pass filter determines, the proportional path does not basically influence the locking point of the loop, and the locking point of the loop is determined by the integral path.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and although the invention has been described in detail with reference to the foregoing examples, it will be apparent to those skilled in the art that various changes in the form and details of the embodiments may be made and equivalents may be substituted for elements thereof. All modifications, equivalents and the like which come within the spirit and principle of the invention are intended to be included within the scope of the invention.

Claims (3)

1. A multiphase sampling type proportional-integral two-way phase-locked loop is characterized by comprising an n-way sampling type phase discriminator, a high-frequency parallel-serial high-pass filter, a transconductance amplifier, a filter capacitor, a voltage-controlled oscillator and a multiphase frequency divider; n is a positive integer;
the high-frequency parallel-serial high-pass filter comprises n paths of switched capacitors and a bias resistor, one end of each of the n paths of switched capacitors is used as an input end of n paths of phase discrimination information, and the other end of each of the n paths of switched capacitors is connected with one end of the bias resistor; the other end of the bias resistor is connected with a bias voltage; the n paths of switched capacitors are respectively started through n paths of non-overlapped holding clocks, so that high-frequency information in the n paths of phase discrimination information is converted into one path in a parallel-serial mode;
the multiphase frequency divider divides the frequency by using the high-frequency output signal of the voltage-controlled oscillator, generates n paths of sampling clock signals and n paths of holding clock signals respectively, and performs sampling type phase discrimination on the n paths of reference clock signals to obtain n paths of phase discrimination results, wherein the n paths of sampling clock signals and the n paths of holding clock signals are respectively used as the sampling clock and the holding clock of the n paths of sampling type phase discriminators; the n-path phase discrimination result is filtered by the high-frequency parallel-serial high-pass filter to remove direct-current mismatching in the n-path phase discrimination result, so that high-frequency phase discrimination information with low loop delay is obtained, and the effect of a proportional control path is realized in a high-frequency section; meanwhile, one path of phase discrimination result passes through the transconductance amplifier with the load as the filter capacitor, so that the effect of an integral control path is realized; the proportional control path and the integral control path respectively control two control ends of the voltage-controlled oscillator.
2. The multiphase sampling type proportional-integral two-way phase-locked loop of claim 1, wherein the transconductance amplifier adopts a gain boosting technology.
3. The multiphase sampling type proportional-integral two-way phase-locked loop of claim 1, wherein the sampling type phase detector is a switched current type sampling type phase detector.
CN202211298099.9A 2022-10-21 2022-10-21 Multiphase sampling type proportional-integral double-path phase-locked loop Pending CN115632655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211298099.9A CN115632655A (en) 2022-10-21 2022-10-21 Multiphase sampling type proportional-integral double-path phase-locked loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211298099.9A CN115632655A (en) 2022-10-21 2022-10-21 Multiphase sampling type proportional-integral double-path phase-locked loop

Publications (1)

Publication Number Publication Date
CN115632655A true CN115632655A (en) 2023-01-20

Family

ID=84907265

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211298099.9A Pending CN115632655A (en) 2022-10-21 2022-10-21 Multiphase sampling type proportional-integral double-path phase-locked loop

Country Status (1)

Country Link
CN (1) CN115632655A (en)

Similar Documents

Publication Publication Date Title
US10855292B2 (en) Phase locked loop
Gao et al. Spur reduction techniques for phase-locked loops exploiting a sub-sampling phase detector
KR100884170B1 (en) Digital phase detector for phase locked loop
EP1216508B1 (en) Pll loop filter with switched-capacitor resistor
US8278984B2 (en) Phase-locked loop
US8274325B2 (en) Phase-locked loop
US6900675B2 (en) All digital PLL trimming circuit
US8284885B2 (en) Clock and data recovery circuits
US20150214966A1 (en) Charge Pump Calibration for Dual-Path Phase-Locked Loop
Nagam et al. A 0.008 mm 2 2.4 GHz type-I sub-sampling ring-oscillator-based phase-locked loop with a− 239.7 dB FoM and− 64dBc reference spurs
US9019016B2 (en) Accumulator-type fractional N-PLL synthesizer and control method thereof
US7940130B2 (en) Frequency generator and method of frequency generation with multiple sampling phase detectors
Jasielski et al. An analog dual delay locked loop using coarse and fine programmable delay elements
US20080191778A1 (en) Gm/c tuning circuit and filter using the same
US7598816B2 (en) Phase lock loop circuit with delaying phase frequency comparson output signals
CN113364457A (en) Quadruple frequency circuit
US8638141B1 (en) Phase-locked loop
US10666271B1 (en) Frequency synthesizer and method of operating the same
CN115632655A (en) Multiphase sampling type proportional-integral double-path phase-locked loop
CN116318127A (en) Auxiliary locking loop applied to dual-path sampling phase-locked loop
CN116032275A (en) Sampling phase discriminator and phase-locked loop system
US11171656B2 (en) Dividerless PLL with sampled lowpass filter structure
CN115149906A (en) Duty ratio correction frequency multiplier based on analog feedback
CN115632654A (en) Multiphase sampling type two-type phase-locked loop
KR101344893B1 (en) Phase locked loop circuit comprising voltage controlled oscillator having variable gain

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination