CN218920410U - Sampling phase discriminator and phase-locked loop system - Google Patents

Abstract

The utility model relates to a sampling phase detector and a phase locked loop system, wherein the sampling phase detector comprises: the input end of the ramp generator P1 is f _ref The output end is electrically connected with the grid electrode of M1, the source electrode of M1 is electrically connected with the drain electrode of M2, and the grid electrode of M2 is f _div The source of M2 is electrically connected with the drain of M3 and one end of C1 respectively, the grid of M3 is electrically connected with the output end of P2, and the input end of P2 is f _div The source electrode of M3 is electrically connected with the drain electrode of M4; the input end of the buffer1 is f _div The output end of buffer1 is electrically connected to the input end of buffer2, the input end of P3 and the grid electrode of M5,the drain electrode of M5 is electrically connected with one end of C1 and the drain electrode of M6 respectively, the grid electrode of M6 is electrically connected with the output end of P3, the source electrode of M6 is electrically connected with the source electrode of M5, one end of C2 and one end of R respectively, the other end of R is electrically connected with one end of C3, the output end of buffer2 is electrically connected with the input end of buffer3, and the output end of buffer3 is electrically connected with the grid electrode of M4. By the method and the device, the problem of poor linearity of the sampling phase discriminator in the related technology is solved.

Description

Sampling phase discriminator and phase-locked loop system

Technical Field

The present utility model relates to the field of phase-locked loop technology, and in particular, to a sampling phase detector and a phase-locked loop system.

Background

In the method for suppressing and canceling the phase noise of the PLL system of the phase-locked loop, there are two aspects of optimization of a module level and optimization of a system level, and in the scheme for optimizing the PLL system level, some architectures such as a sub-sampling phase-locked loop and a sampling phase-locked loop which are commonly adopted at present, wherein the sampling phase-locked loop has a good suppressing effect on the phase noise equivalent to output of other modules including a charge pump and an SPD in the system loop by increasing the gain of the sampling phase-locked loop, and for the integer sampling phase-locked loop, the larger the gain of the sampling phase-locked loop SPD is, the better the gain is, but at the same time, the good linearity is ensured under the condition that the gain is satisfied, and the integer sampling phase-locked loop structure is shown in fig. 1.

The sampling phase-locked loop has the principle that: as shown in fig. 1, the sampling phase-locked Loop includes a voltage-controlled oscillator (VCO), a frequency divider (divider), a Sampling Phase Detector (SPD), a Transconductance (Gm), a Loop Filter (Loop Filter), and a delta-sigma modulator that controls fractional frequency division. SPD is typically composed of a ramp Generator (Slope Generator) and a sample-and-hold circuit. The working mechanism of the sampling phase-locked loop is approximately as follows: first, reference clock frequency f _ref Generating a ramp signal with a certain gradient by a ramp generator in the SPD, and then outputting a signal f by a frequency divider _div Sampling the voltage V by a sampling hold circuit _sam Is converted into a current signal by a transconductance amplifier Gm, the phase error contained in the current signal is also converted into a current signal, and then a control signal V of the VCO is generated after the high-frequency signal is filtered by a low-pass filter LPF _ctrl . The VCO output signal is divided by the divider and fed back to the input to form a closed loop feedback.

The function of the sampling phase detector SPD in a sampling phase locked loop is: the sampling phase discriminator comprises a ramp generator and a sampling hold circuit, the sampling phase discriminator SPD is used for converting the phase difference between a feedback signal of a frequency divider and a reference signal into a voltage signal, the sampling phase discriminator generates a signal with a certain gradient on the rising edge or the falling edge of the reference signal through the ramp generator, the ramp is output by the frequency divider and sampled through the sampling hold circuit, and the magnitude of the phase difference of the two signals is represented by the magnitude of the phase difference of the sampled signal deviated from the midpoint of the ramp signal. In this way, the phase difference between the two is converted into a voltage.

The sampling phase detector structure currently used is shown in fig. 2, and comprises two parts, a Slope Generator (Slope Generator) and a sample-and-hold circuit. The ramp generator is composed of an inverter with RC delay, and is first referenced to signal f _ref The output signal will have a certain slope due to the RC delay of the output of the second inverter, which is fed to the inverter with the RC delay after passing through one inverter. Then generates a sampling voltage V through a two-order sampling hold circuit _sam In the sample-hold stage, two sampling switches are respectively formed from f _div F _div Is controlled by two non-overlapping clocks clk ₁ And clk ₂ To control the sample and hold phase. When clk is ₁ Clk when the controlled switch is on ₂ The controlled switch is turned off, and the first stage enters the sampling stage V _sam1 Sampling to obtain a voltage value, and keeping the output unchanged; when clk is ₂ Controlled switch on, clk ₁ The controlled switch is turned off, and the second stage samples and updates the output value voltage value V _sam 。

A timing waveform diagram of the sampling phase detector is shown in fig. 3. First, the ramp generator is analyzed, when f _ref At low level, i.e. clk _ref When the signal is=0, the NMOS tube of the second inverter is opened, the PMOS tube is closed, and the output of the ramp generator is low level; when f _ref At a high level, i.e. clk _ref At this time, the second inverter NMOS of the ramp generator is turned off, PMOS is turned on, and the level of the output point is connected to the power supply through the variable resistor and then slowly pulled up from the low level, thereby generating a certain ramp. The sample and hold circuit is then analyzed. The sample-and-hold circuit outputs f through a frequency divider _div To generate the sampling clock clk ₁ And clk ₂ Of clk, where clk ₁ Is clk ₂ And the two signals are non-overlapping clocks, the principle is as follows, when sampling f _div At a high level, i.e. clk _div =1, at this time clk ₁ ＝0,clk ₂ =1, the first switch is opened, the second switch is closed, the first switch enters the holding stage, the second switch samples the output node of the first switch to obtain V _sam The method comprises the steps of carrying out a first treatment on the surface of the When f _div At a low level, clk _div The first switch is closed, the second switch is opened, the first switch samples the ramp generator output, charges the first capacitor, the second switch is closed, the output enters the hold phase, and the two switches output voltage waveforms are shown in fig. 3.

The existing sampling phase discriminator has the following defects: 1. it is difficult to achieve high linearity, as can be seen from the above analysis, the ramp generation of the ramp generator is obtained by slowly charging the resistor and capacitor, and it takes a certain time to pull up, and at the same time it is difficult to achieve stable slope, because the change process is slow and the slope is slowly decreasing, so it is difficult to achieve very high linearity, which affects the common mode level of sampling to a great extent, so that the performance of the phase-locked loop is affected, for example, the loop cannot be locked due to a small linear range. 2. The obtained linear range is small, the gain is relatively low, the structure can only be used for scenes with low requirements on the linear range of the sampling phase discriminator, and when the requirements on the linearity, the linear range and the gain of a loop are high, the structure is not realized, because the RC delay of the structure is difficult to achieve a constant slope. 3. The sampled voltage contains higher ripple, which can be filtered by the loop filter, but when the ripple is given to the following voltage-to-current module, it will have a certain effect on the common mode input of the module.

At present, no effective solution is proposed for the problem of poor linearity of the sampling phase detector in the related art.

Disclosure of Invention

The present application is directed to overcoming the shortcomings of the prior art, and provides a sampling phase detector and a phase-locked loop system, so as to at least solve the problem of poor linearity of the sampling phase detector in the related art.

In order to achieve the above purpose, the technical scheme adopted by the application is as follows:

in a first aspect, an embodiment of the present application provides a sampling phase detector, including:

the input end of the first inverter P1 is a ramp wave generator for generating a clock signal f _ref The output end is electrically connected with the grid electrode of the first PMOS tube M1, the drain electrode of the first PMOS tube M1 is connected with a power supply, the source electrode of the first PMOS tube M1 is electrically connected with the drain electrode of the second PMOS tube M2, and the grid electrode of the second PMOS tube M2 is a control clock signal f _div The source of M2 is electrically connected to the drain of the first NMOS tube M3 and one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, the grid of M3 is electrically connected to the output end of the second inverter P2, and the input end of P2 is the control clock signal f _div The source electrode of M3 is electrically connected to the drain electrode of the second NMOS tube M4, the source electrode of M4 is grounded, the control clock signal f _div The first buffer1, the second buffer2 and the third buffer3 are electrically connected to the grid electrode of the M4;

the input end of the buffer1 is the control clock signal f _div The output end of the buffer1 is respectively and electrically connected to the input end of the buffer2, the input end of the third inverter P3 and the grid electrode of the third NMOS tube M5, the drain electrode of the M5 is respectively and electrically connected to one end of the C1 and the drain electrode of the third PMOS tube M6, the grid electrode of the M6 is electrically connected to the output end of the P3, the source electrode of the M6 is respectively and electrically connected to the source electrode of the M5, one end of the second capacitor C2 and one end of the resistor R, the other end of the C2 is grounded, the other end of the R is electrically connected to one end of the third capacitor C3, the other end of the C3 is grounded, the output end of the buffer2 is electrically connected to the input end of the buffer3, and the output end of the buffer3 is electrically connected to the grid electrode of the M4.

In some embodiments, the structures of buffer1, buffer2, and buffer3 are:

the input end is respectively and electrically connected to the grid electrodes of the fourth PMOS tube M7 and the fourth NMOS tube M8, the drain electrode of the M7 is connected with the power supply, the source electrode of the M7 is connected with the drain electrode of the M8, the source electrode of the M8 is grounded, the node between the source electrode of the M7 and the drain electrode of the M8 is electrically connected to the grid electrodes of the fifth PMOS tube M9 and the fifth NMOS tube M10, the drain electrode of the M9 is connected with the power supply, the source electrode of the M9 is connected with the drain electrode of the M10, the source electrode of the M10 is grounded, and the node between the source electrode of the M9 and the drain electrode of the M10 is an output end.

In a second aspect, an embodiment of the present application provides a phase locked loop system, including the sampling phase detector described in the first aspect.

Compared with the prior art, the sampling phase discriminator provided by the embodiment of the application is used for controlling the frequency divider output clock in the phase-locked loop to control the ramp generator to generate ramp waves, so that ramp signals are generated between two phases, linearity and gain of the ramp generator can be improved, meanwhile, the frequency divider clock also respectively controls the sampling capacitor to sample through different time delays, and controls the switch to pull down high level, and the sampling capacitor is connected with the resistor capacitor to form a low-pass filter so as to filter ripple waves on the sampled direct current level, thus, the linearity of the SPD is improved, meanwhile, the high gain and clean direct current level are obtained, meanwhile, the ramp is generated in a form of no resistor, the defect that the resistance value is large to PVT change is avoided, the problem of poor linearity of the sampling phase discriminator in the related art is solved, and the effect of improving the linearity of the sampling phase discriminator is achieved.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the other features, objects, and advantages of the application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

fig. 1 is a schematic diagram of an integer sampling phase-locked loop structure according to the related art;

fig. 2 is a schematic diagram of a sampling phase detector according to the related art;

fig. 3 is a timing waveform diagram of the operation of a sampling phase detector according to the related art;

fig. 4 is a schematic structural diagram of a sampling phase detector according to an embodiment of the present application;

fig. 5 is a schematic diagram of a buffer in a sampling phase detector according to an embodiment of the present application;

fig. 6 is a timing waveform diagram of the operation of the sampling phase detector according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described and illustrated below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden on the person of ordinary skill in the art based on the embodiments provided herein, are intended to be within the scope of the present application.

It is apparent that the drawings in the following description are only some examples or embodiments of the present application, and it is possible for those of ordinary skill in the art to apply the present application to other similar situations according to these drawings without inventive effort. Moreover, it should be appreciated that while such a development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as having the benefit of this disclosure.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly and implicitly understood by those of ordinary skill in the art that the embodiments described herein can be combined with other embodiments without conflict.

Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. Reference to "a," "an," "the," and similar terms herein do not denote a limitation of quantity, but rather denote the singular or plural. The terms "comprising," "including," "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to only those steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as used herein refers to two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The terms "first," "second," "third," and the like, as used herein, are merely distinguishing between similar objects and not representing a particular ordering of objects.

The present embodiment provides a sampling phase detector. Fig. 4 is a schematic structural diagram of a sampling phase detector according to an embodiment of the present application, and as shown in fig. 4, the sampling phase detector includes: the system comprises a ramp generator and a sample hold filter module, wherein the sample hold filter module comprises: the filter comprises a switch circuit consisting of a third NMOS tube M5 and a third PMOS tube M6, a resistor R, a second capacitor C2 and a third capacitor C3.

As shown in fig. 4, the input end of the first inverter P1 generates a clock signal f for ramp _ref The output end is electrically connected with the grid electrode of the first PMOS tube M1, the drain electrode of the first PMOS tube M1 is connected with a power supply, the source electrode of the first PMOS tube M1 is electrically connected with the drain electrode of the second PMOS tube M2, and the grid electrode of the second PMOS tube M2 is a control clock signal f _div The source of M2 is electrically connected to the drain of the first NMOS tube M3 and one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, the grid of M3 is electrically connected to the output end of the second inverter P2, and the input end of P2 is the control clock signal f _div The source electrode of M3 is electrically connected toThe drains of the two NMOS tubes M4 and the source of the M4 are grounded, the control clock signal f _div The first buffer1, the second buffer2 and the third buffer3 are electrically connected to the grid electrode of the M4; the input end of buffer1 is the control clock signal f _div The output end of the buffer1 is respectively and electrically connected with the input end of the buffer2, the input end of the third inverter P3 and the grid electrode of the M5, the drain electrode of the M5 is respectively and electrically connected with one end of the C1 and the drain electrode of the M6, the grid electrode of the M6 is electrically connected with the output end of the P3, the source electrode of the M6 is respectively and electrically connected with the source electrode of the M5, one end of the C2 and one end of the R, the other end of the C2 is grounded, the other end of the R is electrically connected with one end of the C3, the other end of the C3 is grounded, the output end of the buffer2 is electrically connected with the input end of the buffer3, and the output end of the buffer3 is electrically connected with the grid electrode of the M4.

In some embodiments, the structures of buffer1, buffer2, and buffer3 are shown in fig. 5, the input ends are electrically connected to the gates of the fourth PMOS transistor M7 and the fourth NMOS transistor M8, the drain electrode of M7 is connected to the power supply, the source electrode of M7 is connected to the drain electrode of M8, the source electrode of M8 is grounded, the node between the source electrode of M7 and the drain electrode of M8 is electrically connected to the gates of the fifth PMOS transistor M9 and the fifth NMOS transistor M10, the drain electrode of M9 is connected to the power supply, the source electrode of M9 is connected to the drain electrode of M10, the source electrode of M10 is grounded, and the node between the source electrode of M9 and the drain electrode of M10 is the output end.

In some embodiments, the ramp generator charges the capacitor with a clock signal to generate a ramp, the ramp generating clock being f _ref Signal, control clock f _div Signal (f) _divn Is f _div Is the inverse of) and simultaneously passes f _div To control the switch to sample the ramp. With reference to fig. 6, the specific operation mode of the ramp generator is as follows:

when f _ref And f _div At the same low level, M1, M4 are turned off, M2, M3 are turned on, and the output voltage V at one end of C1 _sample Remain unchanged;

when f _ref At a high level, f _div When the voltage is low level, M1, M2 and M3 are turned on, M4 is turned off, C1 is charged through M1 and M2, ramp signals are started to be generated, and voltage V at the output end is outputted _sample Starting rising from a low level;

when f _ref And f _div When the voltage is at the high level, M1 is turned on, but M2, M3 and M4 are turned off, the generation of ramp signals is stopped, and a sampling stage is entered;

when f _ref At low level, f _div At high level, M1, M2 is turned off, M3, M4 is turned on, and the output terminal voltage V _sample Pulled low.

According to the above working mechanism, the ramp wave generation process can be summarized as that when the reference signal f _ref At a high level, when the frequency divider outputs the signal f _div At low level, ramp wave starts to be generated, and after a period of time, divider clock f _div The rising edge starts to come, and then the ramp wave generation stops, and the sampling stage is further entered.

In some of these embodiments, the output terminal voltage V _sample The calculation formula is as follows:

wherein K is _slope For the slope magnitude, Δt is the time interval from generation of the ramp signal to entry into the sampling phase, i.e. the phase difference between the two, T _ref Is the reference clock period.

In some of these embodiments, the sample-and-hold filter module is clocked clk generated by the divided clock after a delay _sw The filter composed of the controlled switch and the resistor-capacitor is formed by controlling the switch to be opened to generate and filter the sampled direct-current voltage signal, and the working mode is as follows in combination with fig. 6: when f _div Clock signal clk generated after buffer1 delay _sw When the voltage is at a high level, the switch circuit is closed, the generation of ramp wave signals is stopped, the point is sampled, and the sampled voltage is filtered by the filter to output voltage V _tune 。

The sampling phase discriminator SPD according to the embodiment of the present application further controls sampling while controlling the generation of ramp wave by the frequency divider output signal, only when the frequency divider output signal f _div Low, a ramp signal is enabled.

According to the embodiment of the application, the frequency divider output clock in the phase-locked loop is used for controlling the ramp generator to generate ramp waves, so that ramp signals are generated between two phases, linearity and gain of the ramp generator can be improved, meanwhile, the frequency divider clock also generates pulse signals through different time delays to respectively control the sampling capacitors to sample, and the switch is controlled to pull down high level. The sampling capacitor is connected with the resistor capacitor to form a low-pass filter so as to filter the ripple wave of the sampled direct current level, thus improving the linearity of the SPD, obtaining high-gain and clean direct current level, generating oblique waves without using a resistor, and avoiding the defect of large change of the PVT caused by the resistance value.

The sampling phase detector provided by the embodiment of the application is different from the existing sampling phase detector SPD in that:

the output of the frequency divider is used for controlling the generation and sampling of oblique waves, so that the linearity of the SPD is improved;

the sampling capacitor is connected with the resistor capacitor to form low-pass filtering, so that signal ripple reduction is realized.

a. The traditional SPD directly generates a ramp signal by adopting a reference signal, and delay is generated by connecting a resistor and a capacitor to the output of an inverter, but the linearity of the structure is poor, and meanwhile, the gain cannot be made large. The embodiment of the application provides a mode of controlling ramp wave generation by using a frequency divider clock, and the frequency divider is used for controlling capacitor charging, so that linearity is improved.

b. The output clock of the frequency divider is controlled to be subjected to sampling and holding through a delay buffer mode, so that the sampling direct-current level is obtained, the sampling time can be better controlled, the sampling level is further controlled, the common-mode range is improved, and the linear range is improved.

c. The sampling switch takes the form of a CMOS switch, which reduces the effects of charge sharing and clock feedthrough of the switch.

d. The inverse signal of the output clock signal of the frequency divider operates in the same way as the control sampling, and the control switch ends the sampling process after a certain delay buffer, namely enters a holding stage.

e. The capacitor is connected with the resistor-capacitor filter, so that ripple waves caused by a sampling switch and other non-ideal factors can be reduced, and a cleaner direct current signal can be obtained. The sampling capacitor and the loop filter capacitor can be shared from the system architecture, so that the area can be saved.

Based on the sampling phase detector provided in the embodiments of the present application, the embodiments of the present application further provide a phase-locked loop system, which may include the sampling phase detector described in the embodiments above. It should be noted that, other portions of the pll system provided in the embodiments of the present application may refer to the structure described in fig. 1, and will not be described herein.

The embodiment of the application can realize the following technical effects:

the Sampling Phase Detector (SPD) can be applied to a sampling phase-locked loop to improve the performance of the sampling phase-locked loop. The sampling phase-locked loop is used as a novel phase-locked loop structure proposed in recent years, so that the defects of the traditional phase-locked loop can be improved to a great extent, for example, a plurality of non-idealities can be generated in the design of PFD and CP in the traditional charge pump phase-locked loop, the problems of accurate matching of pull-up and pull-down currents of the CP, charge leakage and the like are serious, the great difficulty is increased to the layout design, meanwhile, the function of the PFD is only frequency discrimination and phase discrimination, the gain of the PFD is finally related to the phase difference of two signals, and the PFD cannot provide good gain in a loop. In this regard, the sampling phase-locked loop can be superior to a charge pump phase-locked loop, and can not only provide a high-gain sampling phase detector SPD to replace a PFD, but also change a CP into a transconductance amplifier Gm, so that the design difficulty is greatly reduced, the gain of the SPD is increased, the noise performance pressure of the Gm module is also reduced, and meanwhile, one noise performance of other modules is restrained, so that the circuit structure is optimized. Compared with a sub-sampling phase-locked loop, the sampling phase-locked loop performs sampling operation after frequency division by the frequency divider, and does not directly sample the output of the VCO, so that crosstalk between the high-frequency VCO output signal and the low-frequency reference signal through a sampling switch is avoided, and the design difficulty of the sampling circuit is reduced. For the sampling phase-locked loop, if the module-level circuit is properly designed and the performance is optimized as much as possible, the performances of noise, spurious and the like of the phase-locked loop can be well improved. Therefore, the performance of the SPD becomes extremely important, the high-linearity and high-gain sampling phase discriminator is extremely important to the performances of loop locking, noise and the like, the high-gain SPD can inhibit the phase noise of modules such as Gm and the like, reduce the phase noise of a phase-locked loop, improve the locking range with high linearity, avoid loop unlocking, and increase the common mode range of VCO control voltage and the like.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the utility model. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims (3)

1. A sampling phase detector, comprising:

the input end of the first inverter P1 is a ramp wave generator for generating a clock signal f _ref The output end is electrically connected with the grid electrode of the first PMOS tube M1, the drain electrode of the first PMOS tube M1 is connected with a power supply, the source electrode of the first PMOS tube M1 is electrically connected with the drain electrode of the second PMOS tube M2, and the grid electrode of the second PMOS tube M2 is a control clock signal f _div The source of M2 is electrically connected to the drain of the first NMOS tube M3 and one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, the grid of M3 is electrically connected to the output end of the second inverter P2, and the input end of P2 is the control clock signal f _div The source electrode of M3 is electrically connected to the drain electrode of the second NMOS tube M4, the source electrode of M4 is grounded, the control clock signal f _div Through a first processThe buffer1, the second buffer2 and the third buffer3 are electrically connected to the grid electrode of the M4;

the input end of the buffer1 is the control clock signal f _div The output end of the buffer1 is respectively and electrically connected to the input end of the buffer2, the input end of the third inverter P3 and the grid electrode of the third NMOS tube M5, the drain electrode of the M5 is respectively and electrically connected to one end of the C1 and the drain electrode of the third PMOS tube M6, the grid electrode of the M6 is electrically connected to the output end of the P3, the source electrode of the M6 is respectively and electrically connected to the source electrode of the M5, one end of the second capacitor C2 and one end of the resistor R, the other end of the C2 is grounded, the other end of the R is electrically connected to one end of the third capacitor C3, the other end of the C3 is grounded, the output end of the buffer2 is electrically connected to the input end of the buffer3, and the output end of the buffer3 is electrically connected to the grid electrode of the M4.

2. The sampling phase detector of claim 1, wherein the structures of buffer1, buffer2, buffer3 are:

the input end is respectively and electrically connected to the grid electrodes of the fourth PMOS tube M7 and the fourth NMOS tube M8, the drain electrode of the M7 is connected with the power supply, the source electrode of the M7 is connected with the drain electrode of the M8, the source electrode of the M8 is grounded, the node between the source electrode of the M7 and the drain electrode of the M8 is electrically connected to the grid electrodes of the fifth PMOS tube M9 and the fifth NMOS tube M10, the drain electrode of the M9 is connected with the power supply, the source electrode of the M9 is connected with the drain electrode of the M10, the source electrode of the M10 is grounded, and the node between the source electrode of the M9 and the drain electrode of the M10 is an output end.

3. A phase locked loop system comprising the sampling phase detector of claim 1 or 2.

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