JPH0456356A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0456356A JPH0456356A JP16700290A JP16700290A JPH0456356A JP H0456356 A JPH0456356 A JP H0456356A JP 16700290 A JP16700290 A JP 16700290A JP 16700290 A JP16700290 A JP 16700290A JP H0456356 A JPH0456356 A JP H0456356A
- Authority
- JP
- Japan
- Prior art keywords
- polyimide resin
- bonding
- channel
- resin system
- bonding agent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 229920001721 polyimide Polymers 0.000 claims abstract description 20
- 239000009719 polyimide resin Substances 0.000 claims abstract description 20
- 239000000853 adhesive Substances 0.000 claims description 33
- 230000001070 adhesive effect Effects 0.000 claims description 33
- 239000012790 adhesive layer Substances 0.000 claims description 8
- 239000010409 thin film Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910021645 metal ion Inorganic materials 0.000 abstract description 8
- 239000007767 bonding agent Substances 0.000 abstract 5
- 239000003822 epoxy resin Substances 0.000 description 13
- 229920000647 polyepoxide Polymers 0.000 description 13
- 239000010410 layer Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- FKNQFGJONOIPTF-UHFFFAOYSA-N Sodium cation Chemical compound [Na+] FKNQFGJONOIPTF-UHFFFAOYSA-N 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、絶縁性の接着剤によって薄膜上の半導体素子
(以下にデバイスと記す)が基板上に張り合わされてい
る半導体集積回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor integrated circuit in which semiconductor elements (hereinafter referred to as devices) on a thin film are bonded to a substrate using an insulating adhesive. be.
(従来の技術)
基板上に絶縁層が存在しさらにその絶縁層の上に薄膜の
デバイスが存在する構造を有する半導体集積回[以下5
OI(S市con qn In5ulator)デバイ
スと称す]の製造法のひとつに、選択研磨を利用したデ
ノ(イス転写法(浜口恒夫、遠藤伸ネ臥応用物理学第5
6巻、第1.1号(1987)pp1480−1484
)が従来から知られている。デバイス転写法を用いたS
OIデバイスの製造方法の概略を第3図(a)〜(e)
に示す。まず、通常のプロセスを用いて作製されたMO
Sデバイス(第3図(a))に、薄膜化を行うための支
持基板51をエポキシ樹脂系の接着層61を介して接着
する(第3図(b))。続いて選択ポリッシング法を用
いて薄膜化を行い(第3図(C))、エポキシ樹脂系の
接着層62を介して支持基板52を接着する(第3図(
d))。最後に支持基板51および上層を接着層61を
除去する(第3図(e))。第3図(d)において支持
基板52の接着に使用される接着剤は、シリコン活性層
に直接接触し絶縁層の役割を果たしている。従来からこ
の接着剤には、取扱の簡易さなどから重合反応型である
エポキシ樹脂系接着剤を使用していた。(Prior Art) A semiconductor integrated circuit has a structure in which an insulating layer is present on a substrate and a thin film device is further present on the insulating layer [hereinafter referred to as 5
One of the manufacturing methods of the OI (S city con qn in5ulator) device is the Deno (Ice transfer method) using selective polishing (Tsuneo Hamaguchi, Nobune Endo Applied Physics No. 5).
Volume 6, No. 1.1 (1987) pp1480-1484
) has been known for a long time. S using device transfer method
The outline of the manufacturing method of the OI device is shown in Fig. 3(a) to (e).
Shown below. First, MO fabricated using a normal process
A support substrate 51 for thinning is bonded to the S device (FIG. 3(a)) via an epoxy resin adhesive layer 61 (FIG. 3(b)). Subsequently, a selective polishing method is used to reduce the film thickness (FIG. 3(C)), and the support substrate 52 is bonded via an epoxy resin adhesive layer 62 (FIG. 3(C)).
d)). Finally, the adhesive layer 61 is removed from the supporting substrate 51 and the upper layer (FIG. 3(e)). In FIG. 3(d), the adhesive used to bond the support substrate 52 is in direct contact with the silicon active layer and serves as an insulating layer. Conventionally, epoxy resin adhesives, which are polymerization reaction type, have been used for this adhesive because of their ease of handling.
(発明が解決しようとする課題)
しかしなから、このエポキシ樹脂系接着剤62には第4
図に示すようにナトリウムなどの金属イオン72が含ま
れ、正の電荷として基板電位を上げトランジスタ電気特
性に影響を及ぼす。特にNチャネルMO8FETにおい
ては、正の電荷によってpシリコン活性層21の裏面側
にチャネル71が形成される(第4図)。第5図はこの
NチャネルMO8FETのゲート電圧VGに対するドレ
イン電流IDの変化を示す図であるが、この図から明ら
かなように薄膜化する前に比べ漏れ電流が約8桁も増大
することが実験的に分かった(第5図)[高橋宗司、林
喜宏、和田重伸、國尾武光、第37回応用物理学関係連
合講演会、講演予稿集第2分冊pp、64230p−Z
C−101゜このようにシリコン活性層に直接接触する
接着層に含まれる金属イオンの存在は、デバイス転写法
を用いたSOIデバイスの特性劣化における重要な問題
となっていた。(Problem to be Solved by the Invention) However, this epoxy resin adhesive 62 has a fourth
As shown in the figure, metal ions 72 such as sodium are included, which act as positive charges to increase the substrate potential and affect the transistor electrical characteristics. Particularly in the N-channel MO8FET, a channel 71 is formed on the back side of the p-silicon active layer 21 due to positive charges (FIG. 4). Figure 5 is a diagram showing the change in drain current ID with respect to gate voltage VG of this N-channel MO8FET, and as is clear from this diagram, the leakage current increases by about 8 orders of magnitude compared to before thinning. (Figure 5) [Soji Takahashi, Yoshihiro Hayashi, Shigenobu Wada, Takemitsu Kunio, 37th Applied Physics Association Lecture, Lecture Proceedings Volume 2 pp, 64230p-Z
C-101° The presence of metal ions contained in the adhesive layer that directly contacts the silicon active layer has been an important problem in deteriorating the characteristics of SOI devices using the device transfer method.
本発明は、デバイス転写法を用いたSOIデバイスにお
いて、従来のエポキシ樹脂系接着剤がトランジスタ電気
特性に及ぼす影響を除去することを目的とする。The present invention aims to eliminate the influence of conventional epoxy resin adhesives on transistor electrical characteristics in SOI devices using a device transfer method.
(課題を解決するための手段)
本発明は、SOIデバイスのシリコン活性層が直接接触
する接着層に、金属イオンをほとんど含まなぃポリイミ
ド樹脂系接着剤を用いることによって、トランジスタ電
気特性に及ぼす影響を除去することを特徴とする。(Means for Solving the Problems) The present invention uses a polyimide resin adhesive containing almost no metal ions for the adhesive layer in direct contact with the silicon active layer of the SOI device, thereby reducing the effect on transistor electrical characteristics. It is characterized by removing.
(作用)
本発明においては、第2図(d)の支持基板2の接着に
使用される接着剤に金属イオンをほとんど含まない(l
ppm以下)ポリイミド樹脂系接着剤を用いることによ
って、基板電位を上げる要因である正電荷を減少させ、
トランジスタ電気特性に及ぼす影響を抑えている。特に
NチャネルMO8FETにおいては、正電荷の減少によ
るp型シリコンの活性層裏面側におけるチャネルの形成
が抑制され、漏れ電流はエポキシ樹脂系接着剤を用いた
時と比べ大幅に減少することが可能となる(第6図)。(Function) In the present invention, the adhesive used for adhering the support substrate 2 shown in FIG. 2(d) contains almost no metal ions (l
ppm or less) By using a polyimide resin adhesive, the positive charge, which is a factor that increases the substrate potential, is reduced,
The effect on transistor electrical characteristics is suppressed. In particular, in N-channel MO8FETs, the formation of a channel on the back side of the p-type silicon active layer due to a decrease in positive charge is suppressed, and leakage current can be significantly reduced compared to when using an epoxy resin adhesive. (Figure 6).
(実施例)
次に第1図を参照して本発明の実施例について説明する
。第1図はNチャネルMO8FETの断面図である。S
OIデバイスのシリコン活性層裏面は、金属イオンをほ
とんど含まない(lppm以下)ポリイミド樹脂系接着
剤に直接接触している。このため、基板電位を上げる要
因である正電荷は減少し、トランジスタ電気特性に及ぼ
される影響は除去される。(Example) Next, an example of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view of an N-channel MO8FET. S
The back surface of the silicon active layer of the OI device is in direct contact with a polyimide resin adhesive that contains almost no metal ions (lppm or less). Therefore, the positive charges that are a factor in increasing the substrate potential are reduced, and their influence on the transistor electrical characteristics is eliminated.
特にNチャネルMO8FETにおいては、活性層裏面に
はチャネルは形成されず、従ってチャネル性の漏れ電流
は大幅に減少する。Particularly in the N-channel MO8FET, no channel is formed on the back surface of the active layer, so channel leakage current is significantly reduced.
第2図(a)〜(e)にポリイミド樹脂系接着剤を用い
たデバイス転写法によるSOIデバイスの製造方法を示
す。この方法は、第3図において使用しているエポキシ
樹脂系接着剤をポリイミド樹脂系接着剤に置き換えるだ
けでよい。ここで、上述した構造のデバイスを得るため
には、2回目の支持基板2の接着(第2図(d))にポ
リイミド樹脂系接着剤32を使えば十分であるにもかか
わらず、敢えて1回目の支持基板1の接着(第2図(b
))にもポリイミド樹脂系接着剤31を用いていること
には注意すべきである。ポリイミド樹脂系接着剤を用い
て接着を行う際には、基板を約350°Cから400’
Cに加熱する必要がある。支持基板2の接着にポリイミ
ド樹脂系接着剤を使用するには、支持基板1の接着に使
用した接着剤の耐熱温度が約350°C以上でなければ
ならない。従来使用していたエポキシ樹脂系接着剤は耐
熱温度は高々2006C程度であるため使用することは
できないが、ポリイミド樹脂系接着剤の耐熱温度は約5
50°Cであるため、支持基板1の接着にもポリイミド
樹脂系接着剤を用いているのである。ただし、この支持
基板1の接着に使用する接着剤は耐熱温度が350°C
以上であればよいため、その条件を満たす接着剤であれ
ばポリイミド樹脂系接着剤でなくてもよい。FIGS. 2(a) to 2(e) show a method for manufacturing an SOI device by a device transfer method using a polyimide resin adhesive. In this method, it is sufficient to simply replace the epoxy resin adhesive used in FIG. 3 with a polyimide resin adhesive. Here, in order to obtain a device with the above-described structure, it is sufficient to use the polyimide resin adhesive 32 for the second bonding of the support substrate 2 (FIG. 2(d)). Adhesion of support substrate 1 for the second time (Fig. 2(b)
)) It should be noted that the polyimide resin adhesive 31 is also used. When bonding using a polyimide resin adhesive, the substrate should be heated at approximately 350°C to 400°C.
It is necessary to heat it to C. In order to use a polyimide resin adhesive to bond the support substrate 2, the adhesive used to bond the support substrate 1 must have a heat resistance temperature of approximately 350° C. or higher. Conventionally used epoxy resin adhesives have a heat resistance temperature of about 2006C at most, so they cannot be used, but polyimide resin adhesives have a heat resistance temperature of about 5C.
Since the temperature is 50° C., a polyimide resin adhesive is also used for adhering the supporting substrate 1. However, the adhesive used to bond this support substrate 1 has a heat resistance temperature of 350°C.
Since the adhesive above is sufficient, it does not need to be a polyimide resin adhesive as long as it satisfies the above conditions.
なお、本実施例ではデバイスとしてMOSFETを用い
たが、バイポーラトランジスタ等地の種類のデバイスで
もよい。In this embodiment, a MOSFET is used as a device, but other types of devices such as a bipolar transistor may also be used.
(発明の効果)
以上説明したとおり、本発明はデバイス転写法を用いた
SOIデバイスにおいて、従来のエポキシ樹脂系接着剤
がトランジスタ電気特性に及ぼす影響を除去することを
可能とする。(Effects of the Invention) As explained above, the present invention makes it possible to eliminate the influence of conventional epoxy resin adhesives on transistor electrical characteristics in an SOI device using a device transfer method.
第1図は本発明の一実施例のSOIデバイスの断面図、
第2図(a)〜(e)は第1図のSOIデバイスの製造
方法を説明するだめの図、第3図(a)〜(e)は従来
のコ、ボキシ樹脂系接着剤を用いたSOIデバイスの製
造方法を説明するための図、第4図はエポキシ樹脂系接
着剤を用いたSOIデバイスにおいての接着層中の金属
イオンによるチャネルの形成と漏れ電流の関係を説明す
るための図、第5図は薄膜化前のデバイスとエポキシ樹
脂系接着剤を用いたSOIデバイスとのNチャネルMO
8FET電気特性の比較を行った図、第6図は、エポキ
シ樹脂系接着剤を用いたSOI 7’バイスとポリイミ
ド樹脂系接着剤を用いたSOIデバイスとのNチャネル
MO8FET電気特性の比較を行った図である。
図において、11・・・ゲート、12・・・ソース、1
3・・ドレイン、21・・・シリコン活性層、31.3
2・・・ポリイミド樹脂系接着剤、41・・・LOCO
8酸化膜、51.52・・・支持基板、61.62・・
・エポキシ樹脂系接着剤1.71・・・チャネル、72
・・・ナトリウムイオン、81・・・漏れ電流。FIG. 1 is a cross-sectional view of an SOI device according to an embodiment of the present invention;
Figures 2(a) to (e) are schematic diagrams for explaining the manufacturing method of the SOI device shown in Figure 1, and Figures 3(a) to (e) are diagrams for explaining the manufacturing method of the SOI device shown in Figure 1. FIG. 4 is a diagram for explaining the method for manufacturing an SOI device; FIG. 4 is a diagram for explaining the relationship between channel formation by metal ions in the adhesive layer and leakage current in an SOI device using an epoxy resin adhesive; Figure 5 shows the N-channel MO of the device before thinning and the SOI device using epoxy resin adhesive.
Figure 6 shows a comparison of the electrical characteristics of an N-channel MO8FET between an SOI 7' vise using an epoxy resin adhesive and an SOI device using a polyimide resin adhesive. It is a diagram. In the figure, 11...gate, 12...source, 1
3...Drain, 21...Silicon active layer, 31.3
2...Polyimide resin adhesive, 41...LOCO
8 Oxide film, 51.52...Support substrate, 61.62...
・Epoxy resin adhesive 1.71...Channel, 72
...Sodium ion, 81...Leakage current.
Claims (1)
に張り合わされている半導体集積回路において、接着層
としてポリイミド樹脂系接着剤を使用していることを特
徴とする半導体集積回路A semiconductor integrated circuit in which a thin film semiconductor element is bonded to a substrate by an insulating adhesive layer, characterized in that a polyimide resin adhesive is used as the adhesive layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16700290A JPH0456356A (en) | 1990-06-26 | 1990-06-26 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16700290A JPH0456356A (en) | 1990-06-26 | 1990-06-26 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0456356A true JPH0456356A (en) | 1992-02-24 |
Family
ID=15841560
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16700290A Pending JPH0456356A (en) | 1990-06-26 | 1990-06-26 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0456356A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102425156A (en) * | 2011-09-08 | 2012-04-25 | 广东省基础工程公司 | Cross section-variable underground continuous wall and construction method thereof |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62183168A (en) * | 1986-02-06 | 1987-08-11 | Nec Corp | Manufacture of semiconductor device |
-
1990
- 1990-06-26 JP JP16700290A patent/JPH0456356A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62183168A (en) * | 1986-02-06 | 1987-08-11 | Nec Corp | Manufacture of semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102425156A (en) * | 2011-09-08 | 2012-04-25 | 广东省基础工程公司 | Cross section-variable underground continuous wall and construction method thereof |
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