JPH0456349U - - Google Patents

Info

Publication number
JPH0456349U
JPH0456349U JP1990099926U JP9992690U JPH0456349U JP H0456349 U JPH0456349 U JP H0456349U JP 1990099926 U JP1990099926 U JP 1990099926U JP 9992690 U JP9992690 U JP 9992690U JP H0456349 U JPH0456349 U JP H0456349U
Authority
JP
Japan
Prior art keywords
pellets
parts
boards
stacked
sealed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990099926U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990099926U priority Critical patent/JPH0456349U/ja
Publication of JPH0456349U publication Critical patent/JPH0456349U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structure Of Printed Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の第１の実施例を示す断面図、
第２図は同じく第２の実施例を示す断面図、第３
図は従来例を示す断面図である。 １……リードフレーム、２……マウントランド
、３……配線基板、４，４ａ〜４ｃ……ＩＣペレ
ツト、５，６……ボンデイングワイヤ、７……ト
ランスフアモールド樹脂、８……金属バンプ、９
……ポリイミドテープ、１０……銅箔、１１……
絶縁シート、１２……配線端部。 FIG. 1 is a sectional view showing a first embodiment of the present invention;
FIG. 2 is a cross-sectional view showing the second embodiment;
The figure is a sectional view showing a conventional example. 1... Lead frame, 2... Mount land, 3... Wiring board, 4, 4a to 4c... IC pellet, 5, 6... Bonding wire, 7... Transfer mold resin, 8... Metal bump, 9
... Polyimide tape, 10 ... Copper foil, 11 ...
Insulating sheet, 12...Wiring end.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] フレキシブルな有機材からなる配線基板上に、
金属バンプを介してＩＣペレツトが接続、搭載さ
れ、前記ＩＣペレツトが接続、搭載された基板が
複数個積み重ねられ、各基板間の必要な配線部分
が電気的に接続されるとともに、外部取出し電極
端子を除く全体がトランスフアモールド法で樹脂
封止されてなる構造を有することを特徴とする混
成集積回路。 On a wiring board made of flexible organic material,
IC pellets are connected and mounted via metal bumps, a plurality of boards on which the IC pellets are connected and mounted are stacked, the necessary wiring parts between each board are electrically connected, and the external lead electrode terminals are connected. 1. A hybrid integrated circuit characterized by having a structure in which the entire circuit except for the parts is sealed with a resin using a transfer molding method.
JP1990099926U 1990-09-25 1990-09-25 Pending JPH0456349U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990099926U JPH0456349U (en) 1990-09-25 1990-09-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990099926U JPH0456349U (en) 1990-09-25 1990-09-25

Publications (1)

Publication Number Publication Date
JPH0456349U true JPH0456349U (en) 1992-05-14

Family

ID=31842201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990099926U Pending JPH0456349U (en) 1990-09-25 1990-09-25

Country Status (1)

Country Link
JP (1) JPH0456349U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100342811B1 (en) * 1996-11-28 2002-11-27 앰코 테크놀로지 코리아 주식회사 Area array bumped semiconductor package with chips

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100342811B1 (en) * 1996-11-28 2002-11-27 앰코 테크놀로지 코리아 주식회사 Area array bumped semiconductor package with chips

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