JPH0263550U - - Google Patents

Info

Publication number
JPH0263550U
JPH0263550U JP14334188U JP14334188U JPH0263550U JP H0263550 U JPH0263550 U JP H0263550U JP 14334188 U JP14334188 U JP 14334188U JP 14334188 U JP14334188 U JP 14334188U JP H0263550 U JPH0263550 U JP H0263550U
Authority
JP
Japan
Prior art keywords
lead
semiconductor pellets
wires
substrate
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14334188U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14334188U priority Critical patent/JPH0263550U/ja
Publication of JPH0263550U publication Critical patent/JPH0263550U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係るハイブリツドIC用リー
ドの拡大部分上面図、第2図はその拡大部分側面
図、第3図はプレス加工前の上記ハイブリツドI
C用リードの拡大部分上面図、第4図はその拡大
部分測面図である。また、第5図は樹脂モールド
タイプの混成集積回路装置に使用されるリードフ
レームの一例を示す部分斜視図、第6図は樹脂モ
ールドタイプの混成集積回路装置の一例を示す一
部分を断面にした斜視図、第7図イは混成集積回
路装置の略示平面図、第7図ロはモノリシツクI
Cの略示平面図である。 4……リード、9……ワイヤ、6……配線基板
、8……半導体ペレツト、10……熱硬化性樹脂
材、11……外装部、12……混成集積回路装置
(ハイブリツドIC)、13……リード内端部、
14……突起。
FIG. 1 is an enlarged top view of a lead for a hybrid IC according to the present invention, FIG. 2 is an enlarged side view of the lead, and FIG. 3 is the above hybrid IC before pressing.
FIG. 4 is a top view of an enlarged portion of the C lead, and FIG. 4 is a surface view of the enlarged portion. Furthermore, FIG. 5 is a partial perspective view showing an example of a lead frame used in a resin mold type hybrid integrated circuit device, and FIG. 6 is a partially cutaway perspective view showing an example of a resin mold type hybrid integrated circuit device. 7A is a schematic plan view of a hybrid integrated circuit device, and FIG. 7B is a monolithic integrated circuit device.
It is a schematic plan view of C. 4... Lead, 9... Wire, 6... Wiring board, 8... Semiconductor pellet, 10... Thermosetting resin material, 11... Exterior part, 12... Hybrid integrated circuit device (hybrid IC), 13 ...Lead inner end,
14... Protrusion.

Claims (1)

【実用新案登録請求の範囲】 基板上に複数個の半導体ペレツトをマウントし
、基板周辺部に配置したリード端部と上記半導体
ペレツトとをワイヤにて電気的に接続し、上記半
導体ペレツトとリード端部を含む主要部分を樹脂
モールドしてなる混成集積回路装置において、 上記リードの長手方向と直交する内端部に、プ
レス加工による突起を形成したことを特徴とする
混成集積回路装置。
[Claims for Utility Model Registration] A plurality of semiconductor pellets are mounted on a substrate, and the lead ends disposed around the substrate are electrically connected to the semiconductor pellets using wires, and the semiconductor pellets and the lead ends are electrically connected to each other by wires. What is claimed is: 1. A hybrid integrated circuit device comprising a main portion including a resin molded portion, wherein a protrusion is formed by press working on an inner end portion perpendicular to the longitudinal direction of the lead.
JP14334188U 1988-10-31 1988-10-31 Pending JPH0263550U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14334188U JPH0263550U (en) 1988-10-31 1988-10-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14334188U JPH0263550U (en) 1988-10-31 1988-10-31

Publications (1)

Publication Number Publication Date
JPH0263550U true JPH0263550U (en) 1990-05-11

Family

ID=31410076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14334188U Pending JPH0263550U (en) 1988-10-31 1988-10-31

Country Status (1)

Country Link
JP (1) JPH0263550U (en)

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