JPH0452925B2 - - Google Patents
Info
- Publication number
- JPH0452925B2 JPH0452925B2 JP58182718A JP18271883A JPH0452925B2 JP H0452925 B2 JPH0452925 B2 JP H0452925B2 JP 58182718 A JP58182718 A JP 58182718A JP 18271883 A JP18271883 A JP 18271883A JP H0452925 B2 JPH0452925 B2 JP H0452925B2
- Authority
- JP
- Japan
- Prior art keywords
- lines
- drive circuit
- circuit board
- display device
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 claims description 4
- 239000010408 film Substances 0.000 description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
- G02F1/136263—Line defects
Landscapes
- Physics & Mathematics (AREA)
- Liquid Crystal (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、薄膜トランジスタ（TFT）アレイ
を用いた表示装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a display device using a thin film transistor (TFT) array.
近年、多結晶または非晶質半導体薄膜を用いた
TFTアレイを集積形成して駆動回路基板とした
結晶表示装置が注目されている。特にこの種の表
示装置は、半導体薄膜が低温で形成できることか
らガラス基板を用いることができ、従つて低コス
ト化が可能であり、また従来の露光技術、エツチ
ング技術等をそのまま適用して大面積化を図るこ
とができるといつた利点を有する。
In recent years, studies have been made using polycrystalline or amorphous semiconductor thin films.
Crystal display devices that integrate TFT arrays and use them as drive circuit boards are attracting attention. In particular, this type of display device can use glass substrates because the semiconductor thin film can be formed at low temperatures, which makes it possible to reduce costs, and it is also possible to apply conventional exposure technology, etching technology, etc. to a large area. It has the advantage that it can be used for various purposes.
第１図に従来の駆動回路基板の一画素部分の構
造を示す。ａは平面図であり、ｂはそのＡ−
A′断面図である。１はガラス基板であり、この
上にゲート電極２が形成され、この上にSiO2膜
等によるゲート絶縁膜３を介して例えば非晶質シ
リコン（ａ−Si）膜４が形成されている。ａ−Si
膜４には、ドレイン電極５、ソース電極６が形成
され、ソース電極６は透明導電膜からなる表示画
素電極７に接続されている。ゲート電極２は、マ
トリクスの行方向に配設されるアドレス線Xiと一
体形成され、これにより行方向のTFTのゲート
電極は全て共通接続される。またドレイン電極５
は、マトリクスの列方向に配設されるデータ線
Yjと一体形成され、これにより列方向のTFTの
ドレイン電極は全て共通接続される。 FIG. 1 shows the structure of one pixel portion of a conventional drive circuit board. a is a plan view, b is its A-
It is an A′ cross-sectional view. Reference numeral 1 denotes a glass substrate, on which a gate electrode 2 is formed, and on this, for example, an amorphous silicon (a-Si) film 4 is formed with a gate insulating film 3 such as a SiO 2 film interposed therebetween. a-Si
A drain electrode 5 and a source electrode 6 are formed on the film 4, and the source electrode 6 is connected to a display pixel electrode 7 made of a transparent conductive film. The gate electrode 2 is integrally formed with the address line X i arranged in the row direction of the matrix, so that all the gate electrodes of the TFTs in the row direction are commonly connected. Also, the drain electrode 5
is the data line arranged in the column direction of the matrix
It is formed integrally with Y j , so that all the drain electrodes of the TFTs in the column direction are commonly connected.
図では省略したが、実際にはこの駆動回路基板
は表示画素電極７の部分を除いてSiO2等の保護
膜でおおわれる。そしてこの駆動回路基板と、全
面に対向電極を形成した対向基板との間に液晶を
挟持してマトリクス形液晶表示装置が構成され
る。 Although not shown in the figure, this drive circuit board is actually covered with a protective film such as SiO 2 except for the display pixel electrode 7 portion. A matrix type liquid crystal display device is constructed by sandwiching liquid crystal between this drive circuit board and a counter substrate on which a counter electrode is formed on the entire surface.
ところでこの種の液晶表示装置が大面積化する
に伴つて、電極配線数や配線長が増大すると、電
極配線パターン形成時のゴミやマスク傷などによ
り短絡や断線事故が増大する。短絡の場合はスポ
ツト露光等を利用して修正することが比較的容易
であるが、断線の場合、直接的な修正はできな
い。そのため一般的には、駆動回路基板の背後に
電極補修用基板を設け、ボンデイング等を利用し
て配線の線欠陥を点欠陥に補正する手段が採られ
ている。 However, as the area of this type of liquid crystal display device becomes larger, the number of electrode wires and the length of the wires increase, and as a result, accidents such as short circuits and disconnections due to dust and mask scratches during the formation of electrode wiring patterns increase. In the case of a short circuit, it is relatively easy to correct using spot exposure or the like, but in the case of a disconnection, direct correction is not possible. Therefore, generally, a method is adopted in which an electrode repair board is provided behind the drive circuit board and a line defect in the wiring is corrected to a point defect using bonding or the like.
しかしながらこの従来法では、駆動回路基板と
は別に補修用基板を設けなければならないため、
全体として構造、製造工程ともに複雑になる。ま
た、配線の両端部付近で共に断線がある場合に
は、補修用基板では補修ができない。 However, with this conventional method, a repair board must be provided separately from the drive circuit board, so
Overall, both the structure and manufacturing process become complex. Furthermore, if there is a disconnection near both ends of the wiring, it cannot be repaired using a repair board.
本発明は上記の点に鑑み、補修用基板を用いる
ことなく、駆動回路基板の断線による表示品位の
低下を防止した表示装置を提供することを目的と
する。
In view of the above, an object of the present invention is to provide a display device that prevents deterioration in display quality due to disconnection of a drive circuit board without using a repair board.
本発明は、前述のようなTFTアレイを集積形
成してなる駆動回路基板のアドレス線、データ線
のいずれか一方を、TFTアレイの各行または各
列に２本ずつ対をなして、かつこれらの対をなす
２本がTFT部で短絡された状態として配設した
ことを特徴とする。
The present invention provides two address lines and two data lines in each row or column of the TFT array of a drive circuit board formed by integrating the TFT array as described above, and a pair of these lines. It is characterized in that the two wires forming a pair are short-circuited at the TFT section.
本発明によれば、対をなすアドレス線またはデ
ータ線の一方が断線しても他方が正常である限
り、表示欠陥とはならず、２本が同時に断線する
確率は十分小さいものとなるから、高い表示品位
が得られる。しかも駆動回路基板と別に補修用基
板を用意する従来のものに比べ、全体として構造
および製造工程は簡単であるという利点を有す
る。
According to the present invention, even if one of the address lines or data lines in a pair is disconnected, as long as the other is normal, it will not cause a display defect, and the probability that the two lines will be disconnected at the same time is sufficiently small. High display quality can be obtained. Furthermore, compared to the conventional method in which a repair board is prepared separately from the drive circuit board, the present invention has the advantage that the overall structure and manufacturing process are simpler.
また、アドレス線またはデータ線の対をなす２
本は、TFTアレイ内部の各TFT部で互いに短絡
された状態で配設され、同時に使用されるから、
アドレス線やデータ線の配線抵抗が従来に比べて
小さいものとなる。これは特に大面積表示装置を
実現する場合に大きな利点になる。 Also, 2 pairs of address lines or data lines
Books are placed in a short-circuited state in each TFT section inside the TFT array and used at the same time.
The wiring resistance of address lines and data lines is lower than that of the conventional wiring. This is a great advantage especially when realizing a large area display device.
第２図は、本発明を液晶表示装置に適用した一
実施例の駆動回路基板の一画素部分の構造を示す
ものである。ａは平面図、ｂはそのＡ−A′断面
図であり、第１図と対応する部分には第１図と同
一符号を付して詳細な説明を省く。第１図と異な
る点は、TFTのゲート電極２を行方向に共通接
続する信号線として、対をなす２本のアドレス線
Xi，Xi′を、表示画素電極７を挟むようにして配
設していることである。ゲート電極２とアドレス
線Xi，Xi′は、例えばMp膜をスパツタ法により堆
積しこれをパターニングすることにより、一体的
に形成される。すなわち対をなすアドレス線Xi，
Xi′は、ゲート電極２によつて短絡された形で配
設されて、実質１本のアドレス線として機能す
る。
FIG. 2 shows the structure of one pixel portion of a drive circuit board of an embodiment in which the present invention is applied to a liquid crystal display device. 1. A is a plan view, and b is a sectional view taken along line A-A' of FIG. The difference from Fig. 1 is that two address lines forming a pair are used as signal lines that commonly connect the gate electrodes 2 of the TFT in the row direction.
Xi and Xi' are arranged so that the display pixel electrode 7 is sandwiched therebetween. The gate electrode 2 and the address lines Xi, Xi' are integrally formed, for example, by depositing an M p film by sputtering and patterning it. That is, the paired address lines X i ,
X i ' is arranged in a short-circuited manner by the gate electrode 2, and essentially functions as one address line.
このような駆動回路基板と対向基板との間に液
晶層を挟持してマトリクス形液晶表示装置を構成
することは、従来と同様である。 The structure of a matrix type liquid crystal display device by sandwiching a liquid crystal layer between such a driving circuit board and a counter substrate is the same as in the conventional art.
この実施例によれば、対をなす２本のアドレス
線Xi，Xi′のうち一方が断線していても、他方が
導通している限り動作に支障はない。従つてゴミ
やマスク傷等の影響が少なく、高い表示品位を得
ることができる。また、補修用基板を用いる従来
例に比べて、製造工程や製造が簡単である。 According to this embodiment, even if one of the pair of address lines X i and X i ' is disconnected, there is no problem in operation as long as the other is conductive. Therefore, the influence of dust, mask scratches, etc. is small, and high display quality can be obtained. Furthermore, the manufacturing process and manufacturing are simpler than in the conventional example using a repair board.
また２本のアドレス線Xi，Xi′は、並列接続さ
れて実質１本のアドレス線として用いられるか
ら、低い配線抵抗が得られる。 Furthermore, since the two address lines X i and X i ' are connected in parallel and used as substantially one address line, low wiring resistance can be obtained.
第３図は別の実施例の駆動回路基板を示すもの
で、ａが平面図、ｂがそのＡ−A′断面図である。
第１図と対応する部分にはやはり第１図と同一符
号を付して詳細な説明は省く。この実施例では、
TFTのドレイン電極５を列方向に共通接続する
信号線として、対をなす２本のデータ線Yj，
Yj′を配設している。 FIG. 3 shows a drive circuit board of another embodiment, in which a is a plan view and b is a sectional view taken along the line A-A'.
Portions corresponding to those in FIG. 1 are given the same reference numerals as in FIG. 1, and detailed description thereof will be omitted. In this example,
A pair of two data lines Y j ,
Y j ′ is arranged.
このデータ線Yj，Yj′も、ドレイン電極５によ
り短絡された形であり、実質１本のデータ線とし
て配設されたことになる。 These data lines Y j and Y j ' are also short-circuited by the drain electrode 5, and are essentially arranged as one data line.
従つてこの実施例によつても、データ線Yj，
Yj′の一方の断線は表示動作に影響がなく、先の
実施例と同様の効果が得られる。 Therefore, also in this embodiment, the data lines Y j ,
A break in one of Y j ' does not affect the display operation, and the same effect as in the previous embodiment can be obtained.
なお実施例では、アドレス線とデータ線のうち
一方のみを、２本で対をなすようにしたが、双方
共に２本で対をなすようにしてもよい。これによ
り更に表示品位の向上が図られる。 In the embodiment, only one of the address line and the data line is made into a pair, but both may be made into a pair. This further improves display quality.
また本発明は、表示媒体として液晶の他例えば
EL層を用いた表示装置にも同様に適用すること
ができる。 Further, the present invention can be used as a display medium other than liquid crystal, for example.
It can be similarly applied to a display device using an EL layer.
第１図ａ，ｂは従来例の駆動回路基板を示す
図、第２図ａ，ｂは本発明の一実施例の駆動回路
基板を示す図、第３図ａ，ｂは他の実施例の駆動
回路基板を示す図である。
１……ガラス基板、２……ゲート電極、３……
ゲート絶縁膜、４……ａ−Si膜、５……ドレイン
電極、６……ソース電極、７……表示画素電極、
Xi，Xi′……アドレス線、Yi，Yi′……データ線。
Figures 1a and b are diagrams showing a drive circuit board of a conventional example, Figures 2a and b are diagrams showing a drive circuit board of one embodiment of the present invention, and Figures 3a and b are diagrams of another embodiment. It is a figure showing a drive circuit board. 1... Glass substrate, 2... Gate electrode, 3...
Gate insulating film, 4... a-Si film, 5... drain electrode, 6... source electrode, 7... display pixel electrode,
X i , X i ′...address lines, Y i , Y i ′...data lines.
Claims (1)
のゲートおよびドレインをそれぞれ互いに直交す
る方向に共通接続するアドレス線およびデータ線
と、各トランジスタのソースに接続される表示画
素電極とを集積形成した駆動回路基板を用いて表
示媒体を駆動する表示装置において、前記アドレ
ス線またはデータ線のうちいずれか一方が、前記
トランジスタアレイの各行または各列に２本ずつ
対をなして、かつ対をなす２本が各トランジスタ
部で短絡された状態で配設されていることを特徴
とする表示装置。1 Using a drive circuit board that integrates a thin film transistor array, address lines and data lines that commonly connect the gates and drains of each transistor in mutually orthogonal directions, and a display pixel electrode that is connected to the source of each transistor. In a display device that drives a display medium, two of the address lines or the data lines are arranged in pairs in each row or column of the transistor array, and two lines in the pair are arranged in each transistor section. A display device characterized in that it is arranged in a short-circuited state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58182718A JPS6073617A (en) | 1983-09-30 | 1983-09-30 | Display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58182718A JPS6073617A (en) | 1983-09-30 | 1983-09-30 | Display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6073617A JPS6073617A (en) | 1985-04-25 |
| JPH0452925B2 true JPH0452925B2 (en) | 1992-08-25 |
Family
ID=16123223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58182718A Granted JPS6073617A (en) | 1983-09-30 | 1983-09-30 | Display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6073617A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62245222A (en) * | 1986-04-18 | 1987-10-26 | Seiko Epson Corp | Liquid crystal display device |
| US5075674A (en) * | 1987-11-19 | 1991-12-24 | Sharp Kabushiki Kaisha | Active matrix substrate for liquid crystal display |
| NL194848C (en) * | 1992-06-01 | 2003-04-03 | Samsung Electronics Co Ltd | Liquid crystal indicator device. |
| CN106681059B (en) * | 2017-02-09 | 2019-09-24 | 厦门天马微电子有限公司 | A kind of liquid crystal display device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5677887A (en) * | 1979-11-30 | 1981-06-26 | Citizen Watch Co Ltd | Liquid crystal display unit |
-
1983
- 1983-09-30 JP JP58182718A patent/JPS6073617A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5677887A (en) * | 1979-11-30 | 1981-06-26 | Citizen Watch Co Ltd | Liquid crystal display unit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6073617A (en) | 1985-04-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |