JPH0452623B2 - - Google Patents

Info

Publication number
JPH0452623B2
JPH0452623B2 JP6459985A JP6459985A JPH0452623B2 JP H0452623 B2 JPH0452623 B2 JP H0452623B2 JP 6459985 A JP6459985 A JP 6459985A JP 6459985 A JP6459985 A JP 6459985A JP H0452623 B2 JPH0452623 B2 JP H0452623B2
Authority
JP
Japan
Prior art keywords
printed wiring
wiring board
mounting
semiconductor
sheet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6459985A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61222151A (ja
Inventor
Kenro Kimata
Katsumi Mabuchi
Hajime Yatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP6459985A priority Critical patent/JPS61222151A/ja
Publication of JPS61222151A publication Critical patent/JPS61222151A/ja
Publication of JPH0452623B2 publication Critical patent/JPH0452623B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP6459985A 1985-03-27 1985-03-27 半導体搭載用プリント配線板の製造方法 Granted JPS61222151A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6459985A JPS61222151A (ja) 1985-03-27 1985-03-27 半導体搭載用プリント配線板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6459985A JPS61222151A (ja) 1985-03-27 1985-03-27 半導体搭載用プリント配線板の製造方法

Publications (2)

Publication Number Publication Date
JPS61222151A JPS61222151A (ja) 1986-10-02
JPH0452623B2 true JPH0452623B2 (ko) 1992-08-24

Family

ID=13262876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6459985A Granted JPS61222151A (ja) 1985-03-27 1985-03-27 半導体搭載用プリント配線板の製造方法

Country Status (1)

Country Link
JP (1) JPS61222151A (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0274056A (ja) * 1988-09-09 1990-03-14 Matsushita Electric Ind Co Ltd チップキャリア及びチップキャリアアレイ
JPH0567694A (ja) * 1991-09-09 1993-03-19 Nec Corp リードレスチツプキヤリア用フレーム基板
US6686226B1 (en) 1994-02-10 2004-02-03 Hitachi, Ltd. Method of manufacturing a semiconductor device a ball grid array package structure using a supporting frame
JP3352083B2 (ja) * 1994-03-18 2002-12-03 日立化成工業株式会社 半導体パッケージ及び半導体素子搭載用基板の製造方法
JP3413191B2 (ja) * 1994-03-18 2003-06-03 日立化成工業株式会社 半導体パッケージの製造法及び半導体パッケージ
US5976912A (en) 1994-03-18 1999-11-02 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package
JP3413413B2 (ja) * 1994-03-18 2003-06-03 日立化成工業株式会社 半導体素子搭載用基板及びその製造方法
JP3352084B2 (ja) * 1994-03-18 2002-12-03 日立化成工業株式会社 半導体素子搭載用基板及び半導体パッケージ
US6465743B1 (en) 1994-12-05 2002-10-15 Motorola, Inc. Multi-strand substrate for ball-grid array assemblies and method
KR970059825A (ko) * 1997-01-25 1997-08-12 안승균 카메라용 필터를 고정하는 장치
JP4060989B2 (ja) * 1999-06-01 2008-03-12 新日本無線株式会社 リードレスチップキャリア用基板
CN106098661B (zh) * 2013-08-05 2019-01-22 日月光半导体制造股份有限公司 半导体组件及其制造方法

Also Published As

Publication number Publication date
JPS61222151A (ja) 1986-10-02

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