JPH0448751A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0448751A
JPH0448751A JP15791590A JP15791590A JPH0448751A JP H0448751 A JPH0448751 A JP H0448751A JP 15791590 A JP15791590 A JP 15791590A JP 15791590 A JP15791590 A JP 15791590A JP H0448751 A JPH0448751 A JP H0448751A
Authority
JP
Japan
Prior art keywords
opening
film
oxide film
etching
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15791590A
Other languages
Japanese (ja)
Inventor
Toshiharu Katayama
俊治 片山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15791590A priority Critical patent/JPH0448751A/en
Publication of JPH0448751A publication Critical patent/JPH0448751A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent a short-circuit of a wiring to a semiconductor substrate by burying a contact opening to the substrate formed by overetching of anisotropically etching of the opening with an insulating film when the film for forming a sidewall at the side of the opening is isotropically deposited. CONSTITUTION:A thin oxide film 2, a polysilicon layer 3, a thick oxide film 4 are formed on a silicon substrate 1, and a resist pattern 6 is formed on the film 4. Then, a contact opening 7 is formed at the thick film 4 by anisotropically etching using reactive ion etching by using the pattern 6. In this case, if an oxide 5 exists in the layer 3 directly under the opening 7, the oxide 5 is etched to form an opening 8 to the substrate 1. An oxide film 10 of the thickness of the degree of the diameter of the opening 8 is formed. A sidewall 11 of the oxide film is formed at the film 4 by etching it in thickness of the film 10 by anisotropically etching, and the opening 8 is simultaneously buried with an oxide film 12. Then, an aluminum wiring 9 is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置に関するもので、特に、コンタ
クト構造を有する半導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a contact structure.

〔従来の技術〕[Conventional technology]

第3図(a)〜(C)は従来の半導体装置の製造方法を
示す工程別断面図である。第3図において、1は単結晶
シリコン基板(以下、単にシリコノ基板という)  2
は薄い酸化膜、3はポリンリコン層、4は厚い酸化膜、
5は前記ポリシリコン層3内に存在する酸化物、6はレ
ジストをパターニングしたレジストパターン、7は前記
厚いM化膜4に形成されたコンタクト開孔部、8は前記
コンタクト開孔部7のエツチングの際に形成されてしま
った開孔部、9は金属#膜配線であるアルミ配線である
FIGS. 3A to 3C are cross-sectional views showing each step of a conventional method for manufacturing a semiconductor device. In Fig. 3, 1 is a single crystal silicon substrate (hereinafter simply referred to as silicon substrate) 2
is a thin oxide film, 3 is a polyrecon layer, 4 is a thick oxide film,
5 is an oxide present in the polysilicon layer 3; 6 is a resist pattern obtained by patterning a resist; 7 is a contact opening formed in the thick M film 4; 8 is an etching of the contact opening 7. The opening 9 formed during the step is an aluminum wiring which is a metal #film wiring.

次に、製造方法について説明する。Next, the manufacturing method will be explained.

シリコン基板1上に熱酸化法ないし化学的気相成長法(
以下、CVD法と称す)により薄い酸化膜2を形成した
後、CVD法によりポリシリコン層3.厚い酸化膜4を
形成する。この過程において、酸化雰囲気で820℃程
度の熱処理を行うと、上記ポリシリコノ層3中に酸化物
5が形成されてしまう。さらに、フォトレジスト工程を
経て、所zのomにレジストをパターニシグしてレジス
トパターン6を形成する(第3図(a)) このレジス
トパターン6を利用して、リアクティブイオンエツチン
グを用いた異方性エツチングにより厚い酸化膜4にコン
タクト開孔部7を形成する。この際、このコンタクト開
孔部7の直下のポリシリコン層3内に酸化物5が存在し
ていると、異方性エツチングのオーバエツチングにより
酸化物5がエツチングされ、シリコン基板1に至る開孔
部8が形成されてしまう。このように、コンタクト開孔
部7を形成した後、レジストパターン6を除去し、アル
ミをスパック法により形成し、アルミ配線9を形成する
(第3図(C)) 〔発明が解決しようとする課題〕 従来の半導体装置は以上のように構成されているので、
シリコン基板1上に薄い酸化膜2を介して形成されてい
るポリシリコン層3にアルミ配線9とコノタクトを形成
する際、ポリシリコン層3内に酸化物5が存在する領域
にコンタクトを形成する場合、コンタクl−開孔部7の
開孔時のオーバーエツチングによりシリコン基板1まで
コンタクトが突き抜け、アルミ配置i19とシリコン基
板1がショートするという問題点があった。
A thermal oxidation method or a chemical vapor deposition method (
After forming a thin oxide film 2 by a CVD method (hereinafter referred to as CVD method), a polysilicon layer 3 is formed by a CVD method. A thick oxide film 4 is formed. In this process, if heat treatment is performed at about 820° C. in an oxidizing atmosphere, oxide 5 will be formed in the polysilicon layer 3. Further, through a photoresist process, a resist pattern 6 is formed by patterning the resist at a location z om (FIG. 3(a)). Using this resist pattern 6, anisotropic etching using reactive ion etching is performed. A contact opening 7 is formed in the thick oxide film 4 by etching. At this time, if an oxide 5 exists in the polysilicon layer 3 directly under the contact opening 7, the oxide 5 will be etched due to overetching of the anisotropic etching, and the opening will reach the silicon substrate 1. 8 will be formed. After forming the contact hole 7 in this manner, the resist pattern 6 is removed, and aluminum is formed by the spacking method to form the aluminum wiring 9 (FIG. 3(C)). Issue] Since conventional semiconductor devices are configured as described above,
When forming a contact with an aluminum wiring 9 on a polysilicon layer 3 formed on a silicon substrate 1 via a thin oxide film 2, a contact is formed in a region where an oxide 5 exists in the polysilicon layer 3. , Contact l-Due to over-etching when opening the opening 7, the contact penetrates to the silicon substrate 1, causing a short circuit between the aluminum arrangement i19 and the silicon substrate 1.

この発明は、上記のような問題点を解消するためになさ
れたもので、半導体基板上に薄い絶縁膜を介して形成さ
れている多結晶半導体層と金属薄膜配線間のコンタクト
を形成した際に、金属f4膜配線と半導体基板がショー
トしない半導体装置を得ることを目的とする。
This invention was made to solve the above-mentioned problems, and when a contact is formed between a polycrystalline semiconductor layer formed on a semiconductor substrate via a thin insulating film and a metal thin film wiring, The object of the present invention is to obtain a semiconductor device in which the metal F4 film wiring and the semiconductor substrate do not short-circuit.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置は、コンタクト開孔部の側面
にサイドウオール形成のための絶縁膜を等方的に堆積す
る際、コンタクト開孔部の異方性工・ソチングのオーバ
エツチングで形成された半導体基板に至る開孔部を絶縁
膜で埋め込んだものである。
In the semiconductor device according to the present invention, when an insulating film for forming a sidewall is isotropically deposited on the side surface of the contact opening, the insulating film is formed by overetching the contact opening by anisotropic etching and soching. The opening leading to the semiconductor substrate is filled with an insulating film.

〔作用〕[Effect]

この発明においては、コンタクト開孔部形成のための異
方性エツチングのオーバエツチングにより形成されたコ
ンタク)・開孔部直下の半導体基板に至る開孔部は、コ
ンタク1−開孔部のサイドウオール形成の際の絶縁膜で
埋め込まれることから、金属’fiip膜配林と半導体
基板間のりEF  l・を防止する。
In this invention, the contact hole formed by over-etching of anisotropic etching for forming the contact hole is formed by contact 1 - the sidewall of the hole, and the hole leading to the semiconductor substrate directly under the hole. Since it is embedded in the insulating film during formation, it prevents the gap between the metal FIIP film and the semiconductor substrate.

〔実施例〕〔Example〕

以下、この発明の一実施例を図面について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図はこの発明の一実施例である半導体装置の断面図
である。この図で、第3図と同一符号は同じものを示し
、11は酸化膜のサイドウオールである。
FIG. 1 is a sectional view of a semiconductor device which is an embodiment of the present invention. In this figure, the same reference numerals as in FIG. 3 indicate the same parts, and 11 is an oxide film sidewall.

第2図(a)〜(e)はこの発明の半導体装置の製造方
法を示す工程別断面図である。
FIGS. 2(a) to 2(e) are cross-sectional views showing each step of the method for manufacturing a semiconductor device of the present invention.

まず、第2図(a)に示すように、第3図(a)と同様
にしてシリコン基板1上に薄い酸化膜2゜ポリシリコノ
M3.厚い酸化膜4を形成し、さらにこの厚い酸化膜4
上にしジスI・パターン6を形成する。次に、第2図(
b)に示すように、レジストパターン6を利用してリア
クティブイオンエツチングを用いた異方性エツチングに
より厚い酸化膜4にコンタクト開孔部7を形成する。こ
の際、このコンタクト開孔部7の直下のポリシリコン層
3内に酸化物5が存在していると(第2図(a))異方
性エツチングのオーバーエツチングにより上記酸化物5
がエツチングされ、シリコン基板1に至る開孔部8が形
成されろ。この状態において、引きつづき第2図(C)
に示すように、CVD法により上記開孔部8の開孔径程
度の膜厚の酸化膜10を形成する。次に、第2図(d)
に示すように、リアクティブイオンエツチングを用いた
異方性エツチングにより酸化膜10の膜厚分だけエツチ
ングすることにより、厚い酸化膜4に酸化膜のサイドウ
オール11が形成され、同時に開孔部8も酸化膜12で
埋め込まれる。次に、第2図(e)に示すように、アル
ミをスパッタ法により形成し、アノ1ミ配線9を形成す
る。
First, as shown in FIG. 2(a), a thin oxide film 2° polysilicon M3. A thick oxide film 4 is formed, and this thick oxide film 4 is further
Form a pattern 6 on top. Next, see Figure 2 (
As shown in b), contact openings 7 are formed in the thick oxide film 4 by anisotropic etching using reactive ion etching using the resist pattern 6. At this time, if an oxide 5 exists in the polysilicon layer 3 directly under the contact opening 7 (FIG. 2(a)), the oxide 5 is etched by overetching in the anisotropic etching.
is etched to form an opening 8 that reaches the silicon substrate 1. In this state, continue as shown in Figure 2 (C).
As shown in FIG. 3, an oxide film 10 having a thickness approximately equal to the diameter of the opening 8 is formed by the CVD method. Next, Figure 2(d)
As shown in FIG. 3, by etching the oxide film 10 by the thickness of the oxide film 10 by anisotropic etching using reactive ion etching, an oxide film sidewall 11 is formed on the thick oxide film 4, and at the same time, the opening 8 is etched. is also filled with an oxide film 12. Next, as shown in FIG. 2(e), aluminum is formed by sputtering to form an anodized wiring 9. Then, as shown in FIG.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明は、コンタク)−開孔部
の側面にサイドウオール形成のための絶縁膜を等方的に
堆積する際、コンタクト開孔部の異方性エツチングのオ
ーバエツチングで形成された半導体基板に至る開孔部を
絶縁膜で埋め込んだので、後工程で形成されるアルミ配
線が半導体基板とショートすることも防止でき、高品質
の半導体装置が得られる効果がある。
As explained above, the present invention is advantageous in that when an insulating film for forming a sidewall is isotropically deposited on the side surface of a contact opening, an insulating film is formed by over-etching the anisotropic etching of the contact opening. Since the opening leading to the semiconductor substrate is filled with an insulating film, it is possible to prevent the aluminum wiring formed in the subsequent process from shorting with the semiconductor substrate, resulting in a high quality semiconductor device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を示す半導体装置の断面図
、第2図はこの発明の半導体装置の製造方法を示す工程
別断面図、第3図は従来の半導体装置を示す工程別断面
図である。 図において、1は単結晶ンリコン基板、2は薄い酸化膜
、3はポリシリコン層、4は厚い酸化膜、5は酸化物、
6はレジストパターン、7はコンタクト開孔部、8は開
孔部、9はアルミ配線、10は酸化膜、11は酸化膜の
サイドウオール、12は酸化膜である。 なお、各図中の同一符号は同一または相当部分を示す。 代理人 大 岩 増 雄   (外2名)第 図 そ の の2 o12 酸化傾 第3図 平成 3年
FIG. 1 is a cross-sectional view of a semiconductor device showing an embodiment of the present invention, FIG. 2 is a cross-sectional view of each step showing a method of manufacturing the semiconductor device of this invention, and FIG. 3 is a cross-sectional view of a conventional semiconductor device showing each step. It is a diagram. In the figure, 1 is a single crystal silicon substrate, 2 is a thin oxide film, 3 is a polysilicon layer, 4 is a thick oxide film, 5 is an oxide,
6 is a resist pattern, 7 is a contact opening, 8 is an opening, 9 is an aluminum wiring, 10 is an oxide film, 11 is a sidewall of the oxide film, and 12 is an oxide film. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure No. 2 o12 Oxidation gradient Figure 3 1991

Claims (1)

【特許請求の範囲】[Claims]  半導体基板上に薄い絶縁膜を介して形成された多結晶
半導体配線と、その上に形成された厚い絶縁膜とを備え
、この厚い絶縁膜にコンタクト開孔部が形成され、この
コンタクト開孔部を介して前記多結晶半導体配線と金属
薄膜配線が電気的に接続された半導体装置において、前
記コンタクト開孔部の側面に絶縁膜を等方的に堆積し、
異方的に除去して前記コンタクト開孔部の異方性エッチ
ングのオーバエッチングで形成された前記半導体基板に
至る開孔部を前記絶縁膜で埋め込んだことを特徴とする
半導体装置。
A polycrystalline semiconductor wiring formed on a semiconductor substrate with a thin insulating film interposed therebetween and a thick insulating film formed on the polycrystalline semiconductor wiring, a contact hole formed in the thick insulating film, and a contact hole formed in the thick insulating film. In a semiconductor device in which the polycrystalline semiconductor wiring and the metal thin film wiring are electrically connected through a semiconductor device, an insulating film is isotropically deposited on a side surface of the contact opening,
A semiconductor device characterized in that an opening extending to the semiconductor substrate formed by anisotropic removal and over-etching of the anisotropic etching of the contact opening is filled with the insulating film.
JP15791590A 1990-06-14 1990-06-14 Semiconductor device Pending JPH0448751A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15791590A JPH0448751A (en) 1990-06-14 1990-06-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15791590A JPH0448751A (en) 1990-06-14 1990-06-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0448751A true JPH0448751A (en) 1992-02-18

Family

ID=15660239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15791590A Pending JPH0448751A (en) 1990-06-14 1990-06-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0448751A (en)

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