JPH0445532A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable precision processing with ease by processing a semiconductor surface layer with a solution exclusively designed to oxidize said surface layer and a solution exclusively designed to remove an oxide layer formed on the semiconductor surface layer when wet-etching the semiconductor surface layer. CONSTITUTION:A resist pattern 8 is used as a mask where recess etching is carried out partially on an nGaAs layer. This recess etching is carried out in such a manner that the resist is submerged in a solution (hydrogen peroxide: water=1:30) exclusively designed to oxide the surface of the nGaAs semiconductor for one minute and water-flow cleaned for one minute and further submerged in a solution (hydrochloric acid:water=1:10) for one minute and water flow- cleaned. After the cleaning is over, a gate electrode 9 is formed on the pattern 8 based the electron beam vapor deposition process. The depositions on the resist pattern is removed by a organic solution for the resist pattern and lift-off- processed to eliminate simultaneously. Finally, an Si-N film is covered as a surface protection film.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for manufacturing a semiconductor device in which precisely controlled wet etching is performed on the surface of a semiconductor, and is effective for manufacturing a Risenu type GaAs MESFET or HEMT. This is a great method.

<Prior Art> In recent years, in order to reduce the series resistance between the gate and source or between the gate and drain of HEMT, a thick n'' GaAs cap layer 5 (more than several hundred λ) has been used as shown in the cross-sectional view in FIG. A configuration with
-211770.

When the above cap layer 5 is formed, the HEM shown in FIG.
As shown by T, it is indispensable to make the cap layer 5 forming the tFM 9 into a concave shape or to perform etching. Therefore, recess etching is performed, which can be roughly divided into reactive ion etching (RIE).
and wet etching using a mixed solution of an acid such as hydrochloric acid, sulfuric acid, or phosphoric acid, hydrogen peroxide, and water. Note that the configuration of the HEMT in FIG.
Since the same numbers are used in the following figures, the explanation will be omitted here.

<Problems to be Solved by the Invention> When the semiconductor surface is etched using the dry etching described above, RIE is applied to the semiconductor surface where the gate electrode is to be formed.
There is a problem that crystal defects are formed due to processing. or,
Using a high melting point metal for the gate electrode formed on it,
Although processing damage caused by RIE can be recovered by heat treatment after forming the gate electrode, it has the drawback of complicating the manufacturing process.

Using another wet etching method, the conventional method shown in FIG. It is etched by progressing at the same time.

In this type of etching, if the etching rate determined by the balance between the oxidation rate of the semiconductor surface and the removal rate of the oxidized semiconductor surface layer can be changed depending on the composition of the semiconductor layer, this etching selectivity can be utilized. However, GaAs used in HEMT, A-Ga
As, InGaAs, or InA does not have wet etching that can selectively etch As, InGaAs, or InA. Therefore, the eighth
Figure K: 1 dAiG with the conventional wet etching shown.
When recess etching is performed on the gate portion of an aAs/GaAs HEMT, it is necessary to monitor the drain current in order to stop the etching when the drain current of this transistor reaches an optimum value. Moreover, as shown in Figure 4, the etchant is phosphoric acid: hydrogen peroxide: water = 8.
2) When using a 1:50 mixture, the recess etching that brings about the optimum drain current must be controlled within 2 seconds for an etching time of about 1 minute. be. Since selective etching cannot be performed in cases such as HEMT, there is a problem in that the controllability of etching is poor and, therefore, the reproducibility of the product is poor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device using wet etching, which eliminates the problems associated with conventional recess etching and allows highly accurate recess etching.

<Means for Solving the Problems> The sea urchin toenoting of a semiconductor surface according to the present invention includes a step of oxidizing the semiconductor surface and a step of removing the oxidized semiconductor surface.

At this time, recess etching is performed with high accuracy by utilizing the approximately constant thickness of the oxide layer, thereby solving the problems of conventional etching methods.

In the etching method of the present invention, the step of oxidizing the semiconductor surface with hydrogen peroxide and the step of removing the oxidized semiconductor surface layer with an acid solution are separated into separate steps. When immersed in the above-mentioned oxidizing etchant, the acid (IS- layer) on the surface of the semiconductor becomes a summing function.In other words, if the semiconductor is immersed in the oxidizing etchant for a certain period of time, the thickness of the oxidized layer will increase over time. Therefore, there is almost no change.

The oxide layer on the semiconductor surface formed in the above manner is
Although it is possible to remove the semiconductor layer by etching with hydrochloric acid, sulfuric acid, or phosphoric acid diluted to less than 30%, it is impossible to directly etch the semiconductor layer with this diluted solution. Therefore, the semiconductor surface layer is etched to a certain oxidized thickness.

Etching of the present invention is wet etching, and R
Unlike IE, there is no problem of processing damage caused by dry etching, and unlike conventional wet etching, where the etching amount is controlled only by time, the semiconductor surface is etched to a constant thickness almost regardless of time. The amount of etching can be precisely controlled by the number of times the formation of the oxide layer and the removal of the oxide layer are repeated. Therefore, it has become possible to perform wet etching such as recess etching with high precision without processing damage.

<Example> An example of the present invention will be described below with reference to the drawings. In this embodiment, a case will be described in which the etching method of the present invention is used for A) recess etching in the gate portion of a GaAs/GaAs HEMT.

First, as shown in FIG. 5, on the surface of a semi-insulating GaAs substrate 1, there are formed an undoped GaAs layer 21 with a thickness of 5000A, an undoped A-GaAs layer a1 with a thickness of 800 nm, and 40 layers with a thickness of 600 nm. nG'aAs layer 5
was continuously grown using the molecular beam epitaxy (MBE) method to form a layered structure. Next, the substrate 1 on which the laminated layers were formed by the MBE method was taken out from the MBE apparatus, and mesas were formed by ordinary wet etching to form a structure for isolation between elements. Furthermore, the source electrode 6. shown in FIG. A drain electrode 7 was formed. Further, the sixth
As shown in the figure, a resist pattern 8 for forming a GaAs electrode was prepared on the surface of the laminated growth layer, and using this resist pattern 8 as a mask, recess etching was performed on a part of the nGaAs layer. This recess etching is carried out by immersing the nGaAs semiconductor in a solution that only oxidizes the surface (hydrogen peroxide:water - 1:80) for 1 minute and washing with running water for 1 minute, as shown in Figure 1. Removal solution (hydrochloric acid: water = 1
If the process of immersing the substrate in 10) for 1 minute and then rinsing with running water for 1 minute constitutes one etching process of the present invention, this single process could reproducibly etching nGaAs by 20A.

In this example, this etching process was repeated 20 times on the nGaAs layer 5 to complete the recess etching.

Thereafter, a titanium (Ti) film with a thickness of 1000λ and a film of 800λ were deposited on top of the resist pattern 8 using an electron beam evaporation method.
A gate electrode 9 made of gold (Au) with a film thickness of 0λ was formed, and a lift-off process was performed in which the vapor deposits on the resist pattern were removed at the same time as the resist pattern was removed with an organic solvent. The gate electrode 9 formed in the above manner is shown in FIG.

Finally, a 2000A 5i-N film 10 was used as a surface protection film.
FIG. 8 shows the state in which it is coated.

In the embodiments described above, the etching of the present invention was performed using HE
Although the description has been made regarding recess etching of MT, the present invention is not limited to the embodiments, but can be applied to the after-etching of semiconductors, which requires highly accurate processing.

<Effects> By the etching method of the present invention, for example, recess-type A-Ga
When manufacturing As/GaAs HEMTs, the processing and etching can be precisely controlled even if recess etching is performed using wet etching, so there is no need to monitor the drain current during the recess etching process, making it possible to simplify the manufacturing process. Ta.

As can be seen from the above examples, the present invention makes it possible to easily perform precision machining, which was difficult in terms of machining accuracy with conventional wet etching.

[Brief explanation of the drawing]

FIG. 1 is a process flow diagram explaining the process of manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of an A-no-GaAs/GaAs HEMT with a thick GaAs cap layer, and FIG. FIG. 4 is a process flow diagram showing the entire etching process. FIG. 4 is a diagram showing the relationship between the drain current and etching time for the gate area by conventional wet etching. FIGS.
It is a sectional view showing the manufacturing process of MT. 1... Semi-insulating GaAs substrate, 2... Undoped, G
aAs layer, 8... undoped A7! GaAs layer, 4-nAJGaAs layer, 5-n GaAs layer,...source electrode, 7...drain electrode, 8...resist pattern, 9...gate electrode, 0... 5i-N film.

Claims (1)

[Claims] 1. Wet etching of the semiconductor surface layer consists of a step of treating the semiconductor surface layer with a liquid that only oxidizes the semiconductor surface layer, and a step of treating it with a liquid that only removes the oxidized layer formed on the semiconductor surface layer. A method for manufacturing a semiconductor device, characterized by: