KR20010094662A - The planarization measuring method for langasite single crystal - Google Patents

The planarization measuring method for langasite single crystal Download PDF

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KR20010094662A
KR20010094662A KR1020000017081A KR20000017081A KR20010094662A KR 20010094662 A KR20010094662 A KR 20010094662A KR 1020000017081 A KR1020000017081 A KR 1020000017081A KR 20000017081 A KR20000017081 A KR 20000017081A KR 20010094662 A KR20010094662 A KR 20010094662A
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flatness
single crystal
mrr
measuring
langasite
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KR1020000017081A
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Korean (ko)
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장민철
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오근호
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon

Abstract

PURPOSE: A method for measuring flatness of a langasite(La3Ga5SiO14) single crystal is provided to measure accurately an MRR(Material Removal Rate) of a single crystal and reduce a cost for measuring the MRR by using a simple pattern process used in a semiconductor manufacturing process. CONSTITUTION: SiO2 of thickness of 1000 angstrom is deposited as a protective layer in order to measure flatness. A photo-resist is coated on the deposited SiO2 protective layer. The photo-resist is patterned. An etching process is performed by using a mixed material of HCl: 10H2O. An MRR is obtained by dividing a removed material of a polishing process into a predetermined time. Namely, the flatness of the etched langasite single crystal is measured by performing the etching process using the mixed material of HCl: 10H2O.

Description

랑가사이트(Ｌａ3Ｇａ5ＳｉＯ14) 단결정의 평탄도 측정법{The planarization measuring method for langasite single crystal}Planarization measuring method for langasite single crystal

다층화에 따른 웨이퍼의 광역 평탄화가 부각되었고, 또한 급속한 전자 및 정보통신 기술의 발전에 따라 새로운 압전재료의 발견 필요성이 부각되었다. 이에 부응할 수 있는 새로운 단결정 소재용 압전재료인 La3Ga5SiO14는 SAW 필터나 다른 여러 가지 필터의 기판으로 쓰이기 위해서는 연마 공정의 확립이 중요하다. 그러나 La3Ga5SiO14의 경우는 신물질이기 때문에 이러한 연마공정이 확립되지 않아서, La3Ga5SiO14가 가지고 있는 우수성을 오히려 잃어버리게 된다. 이것은 표면의 상태의 문제가 주파수 특성에 상당한 나쁜 영향을 미치기 때문이다. 이에 대한 입증 자료는 Sally Laffey(IEEE International Frequency Control Symposium, 1994)의 연구결과로부터 확인할 수 있다.Wide area planarization of wafers due to multilayering has emerged, and the development of new piezoelectric materials has been highlighted with the rapid development of electronic and information communication technologies. A new piezoelectric material for single crystal material, La 3 Ga 5 SiO 14, which can be used as a substrate for SAW filters and other various filters, is important to establish a polishing process. However, since La 3 Ga 5 SiO 14 is a new material, such a polishing process is not established, and the superiority of La 3 Ga 5 SiO 14 is rather lost. This is because the problem of the state of the surface has a significant bad effect on the frequency characteristics. Evidence for this can be found in the study by Sally Laffey (IEEE International Frequency Control Symposium, 1994).

또한, 기존의 연마 속도를 구하기 위해서는 고가의 두께 측정 장비가 필요하였다. 이러한 고가의 장치를 이용함에도 불구하고 두께를 측정하였을 때 생기는 오차가 심하여 박막의 두께를 측정하는 Alpha-step같은 기계보다는 정확성이 떨어진다. 왜냐하면 이러한 고가의 두께 측정 장치는 웨이퍼의 두께를 직접적으로 측정하는 방식이 아니라 표면의 단차나 두께에 따른 유전율변화, 또는 laser를 이용하는 방법 등 측정 데이터를 전기적 신호로 환산하는 과정 때문에 이러한 오차가 생긴다. 따라서 생산 단계에 있어서 새로운 물질에 대한 연마공정 확립을 위해서는 정확하고 재현성 있는 데이터가 필요하게 된다. 특히 실험실 규모에서는 연마 공정 중에서는 이러한 고가의 장비보다는 반도체 공정에서 박막 두께를 측정하는 장비를 이용하여 보다 정확하게 측정하는 것이 더 현실적이고, 정확하고 재현성이 높은 장점이 있다. 왜냐하면 일정 시간동안 제거된 물질의 양을 일정시간당 같은 위치에서 계속적으로 측정이 가능하기 때문이다.In addition, in order to obtain a conventional polishing rate, expensive thickness measuring equipment was required. Despite the use of these expensive devices, the error in measuring the thickness is so severe that it is less accurate than a machine like Alpha-step, which measures the thickness of thin films. This expensive thickness measurement device is caused by the process of converting the measurement data into an electrical signal, such as a method of measuring the thickness of the wafer directly, not a change in the dielectric constant according to the step height or thickness of the surface, or using a laser. Therefore, accurate and reproducible data is needed to establish the polishing process for new materials in the production stage. Particularly, in the laboratory scale, it is more realistic, accurate, and reproducible to measure more accurately by using a device for measuring thin film thickness in a semiconductor process than an expensive equipment in a polishing process. This is because the amount of material removed over time can be continuously measured at the same location per time.

본 발명은 특히 두께 측정 장비의 단점으로 여겨지는 가격 문제와 정확도 문제를 반도체 공정에서 쓰이는 간단한 패턴 공정을 통하여 연마시 단결정의 정확한 MRR(Material Removal Rate)을 측정하는 것에 목적에 있다.The present invention aims to measure the exact material removal rate (MRR) of a single crystal during polishing through a simple pattern process used in a semiconductor process, in particular a price problem and an accuracy problem, which are considered disadvantages of the thickness measuring equipment.

본 발명이 이루고자 하는 기술적 과제는 langasite(La3Ga5SiO14) 연마 공정에서 중요한 요소가 되는 평탄도를 측정하는 방법에 있어서 기존의 고가 장비를 대신하여 정확하고 재현성 있는 측정 방법을 제안함으로써, 좀 더 정확한 평탄도를 측정하는데 기여하고자 한다.The technical problem of the present invention is to propose an accurate and reproducible measuring method in place of the existing expensive equipment in the method of measuring flatness, which is an important factor in langasite (La 3 Ga 5 SiO 14 ) polishing process. It is intended to contribute to measuring more accurate flatness.

도 1에서는 본 발명의 실시를 위한 공정도를 보여 주고 있고, 도 2는 이러한 실시예로 기존의 콜로이드 실리카를 이용하였을 때 langasite 단결정이 나타내는 연마속도를 보여주고 있고, 도 3은 이러한 연마 속도를 개선하기 위한 pH 조절시 나타나는 연마 속도를 보여주고 있다. 그리고, 도 4는 입자 크기에 따른 평탄도의 향상 경향을 보여 주고 있고, 도 5는 연마액 내의 입자 농도 따른 평탄도 경향 데이터를 나타내었다.Figure 1 shows a process diagram for the practice of the present invention, Figure 2 shows the polishing rate represented by the langasite single crystal when using the conventional colloidal silica in this embodiment, Figure 3 to improve this polishing rate The polishing rate is shown when the pH is adjusted. 4 shows a tendency of improving flatness according to particle size, and FIG. 5 shows flatness tendency data according to particle concentration in the polishing liquid.

본 발명의 특징, 양상 및 기존방법과 비교된 장점들은 하기의 기술 및 특정적이고 비제한적인 실시예로부터 더욱 분명히 이해될 수 있다.The features, aspects, and advantages compared to the existing methods of the present invention can be more clearly understood from the following description and specific, non-limiting examples.

[실시예] 도 1은 본 발명을 위한 간략한 공정도를 보여주고 있다. 평탄도를 측정하기 위해서 SiO2를 보호막으로 1000Å를 증착시키고, PR을 그 위에 코팅한 후 패턴을 하여 HCl: 10H2O를 이용하여 에칭을 한 후 연마 과정 중에서 물질이 제거되는 것을 일정한 시간으로 나눠 MRR(Material Removal Rarte)를 구했다.EXAMPLES Figure 1 shows a simplified process diagram for the present invention. In order to measure the flatness, 1000Å of SiO 2 was deposited as a protective film, PR was coated thereon, then patterned and etched using HCl: 10H 2 O, and then the material was removed during polishing. MRR (Material Removal Rarte) was obtained.

본 발명에서는 평탄도 측정을 위하여 정확하고 재현성 있는 평탄도 측정법을 여러 가지 방법을 통해서 본 발명의 우수성을 확인 하고자 한다. 실시예의 방법으로 연마된 La3Ga5SiO14의 연마액의 입자수에 따른 평탄도와 연마액의 입자크기에 따른 평탄도 경향을 통해 고찰하였다.In the present invention, to determine the superiority of the present invention through a variety of methods for accurate and reproducible flatness measurement method for measuring the flatness. The flatness according to the particle number of the polishing liquid of La 3 Ga 5 SiO 14 polished by the method of Example and the flatness according to the particle size of the polishing liquid were considered.

[01][01]

평탄도를 측정하기 위해서 도 1에서처럼 패턴을 하였다. 평탄도를 측정하기 위해서 SiO2를 보호막으로 1000Å를 증착시키고, PR을 그 위에 코팅한 후 패턴을 하여 HCl: 10H2O를 이용하여 에칭을 한 후 연마 과정 중에서 물질이 제거되는 것을 일정한 시간으로 나눠 구했다. MRR(Material Removal Rate)의 측정은 웨이퍼 연마 가공시 가운데 부분이 잘 연마가 되지 않아서 Bull's Eye 현상이 일어나게 되는데 이러한 미세한 두께 변화까지 정확히 측정하여 웨이퍼가 전 영역에 걸쳐 같은 속도로 연마되는 것을 조절하기 위한 수단이다. 이러한 측정을 위하여 기존의 방식은 고가의 두께 측정 장치를 이용하여 두께를 측정하였는데 측정의 재현성이 좋지 않고, 정확한 MRR을 측정할 수가 없는 단점을 가지고 있다. 그래서 도 1처럼 일정한 간격으로 같은 지점에서 계속적으로 MRR을 측정함으로써 연마시 평탄도 향상을 가져올 수 있게 된다.In order to measure the flatness, a pattern was formed as in FIG. 1. In order to measure the flatness, 1000Å of SiO 2 was deposited as a protective film, PR was coated thereon, then patterned and etched using HCl: 10H 2 O, and then the material was removed during polishing. Saved. The MRR (Material Removal Rate) is measured during the wafer polishing process so that the center of the wafer is not polished so that the Bull's Eye phenomenon occurs. Means. For this measurement, the conventional method measures the thickness by using an expensive thickness measuring device, but has a disadvantage in that the reproducibility of the measurement is not good and the accurate MRR cannot be measured. Therefore, by continuously measuring the MRR at the same point at regular intervals as shown in FIG. 1, it is possible to improve the flatness during polishing.

[비교예][Comparative Example]

[02][02]

실시 예에서 언급했던 비교를 위해서 도 2는 기존의 콜로이드 실리카를 이용하여 연마했을 때 langasite가 나타내는 연마 속도를 보여 주고 있는 그림이다. 이것은 위에서 언급한 측정법을 사용하여 측정한 데이터이다. 도 3은 연마액의 pH에 따른 연마 속도를 나타내는 그림이다. 그리고, 도 4에서는 입자크기에 따른 평탄도 효과를 보여주고 있는데 그림처럼 0.014㎛의 입자 크기가 가장 좋은 결과를 나타냈고, 또한 연마액의 가공에 있어서 가장 중요한 입자농도는 1∼2%가 가장 평탄도 향상에 기인하였다. 도 5에서 이를 증명하여 준다. 이러한 도 2, 3, 4, 5는 이러한 발명의 우수함을 증명하여 주고 있다.For comparison as mentioned in the example, FIG. 2 is a diagram showing a polishing rate indicated by langasite when polished using conventional colloidal silica. This is data measured using the above mentioned measurement method. 3 is a diagram showing the polishing rate according to the pH of the polishing liquid. In addition, Figure 4 shows the effect of the flatness according to the particle size, the particle size of 0.014㎛ showed the best results as shown in the figure, and the most important particle concentration in the processing of the polishing liquid is the most flat 1 ~ 2% This was due to the improvement. This is proved in FIG. 2, 3, 4, 5 proves the superiority of this invention.

즉, 재현성있고 정확한 평탄도 측정법이라는 것을 보여주고 있다.That is, it is a reproducible and accurate flatness measurement method.

위에서 진술한 실시 예에서 표시된 것과 같이, 본 발명에서 제시된 새로운 평탄도 측정법을 통하여 정확하고 재현성 있는 평탄도를 측정할 수 있다. 이러한 광역적인 평탄도의 중요성은 최근 반도체 산업의 주요 경향중 하나인 고집적화 때문이다. 이를 위해 단위 면적 당 많은 칩의 생산을 위한 배선의 다층화가 시도되었고, 노광 광원의 초점심도 한계로 인하여 웨이퍼의 전면에 걸친 광역평탄화가 필수적인 공정으로 인식되고 있다. 따라서 본 발명으로 인하여 La3Ga5SiO14단결정의 여러 분야의 압전 통신 소자의 기판 재료로의 응용이 가능하게 되었다. 또한 새로운 평탄도 측정법으로 인하여 광역적인 평탄도 측정이 정확하고 재현성 있게 측정할 수 있게 되어 웨이퍼 가공시 응용에 있어서 우수한 결과를 가져올 것으로 기대된다.As indicated in the above-mentioned embodiment, the new flatness measurement method presented in the present invention can measure accurate and reproducible flatness. The importance of such global flatness is due to high integration, which is one of the major trends of the semiconductor industry. To this end, multilayered wiring has been attempted for the production of a large number of chips per unit area, and it is recognized that a wide area flattening over the entire surface of the wafer is essential due to the limited depth of focus of the exposure light source. Therefore, the present invention enables the application of La 3 Ga 5 SiO 14 single crystal to the substrate material of piezoelectric communication devices in various fields. In addition, the new flatness measurement method is expected to enable accurate and reproducible measurement of global flatness measurement, which is expected to produce excellent results in wafer processing applications.

Claims (3)

패턴 공정에서, HCl과 H2O 혼산을 이용한 에칭 공정.Etching process using HCl and H 2 O mixed acid in the pattern process. 제 1항에 있어서, 상기 혼산이 HCl : H2O의 비가 1:10이 되도록 이루어진 것을 특징으로 하는 La3Ga5SiO14계열의 압전 세라믹 단결정 에칭 공정.The method of claim 1, wherein the horn acid HCl: a single crystal piezoelectric ceramic etching process of La 3 Ga 5 SiO 14 series, characterized in that made such that the ratio of H 2 O 1:10. 제 2항에 있어서, 상기 혼산을 이용하여 에칭된 langasite 단결정의 평탄도 측정법.The method of claim 2, wherein the flatness of the langasite single crystal etched using the mixed acid.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0380543A (en) * 1989-08-24 1991-04-05 Fujitsu Ltd Semiconductor device
JPH0445532A (en) * 1990-06-13 1992-02-14 Sharp Corp Manufacture of semiconductor device
JPH08130204A (en) * 1994-10-31 1996-05-21 Oki Electric Ind Co Ltd Surface treatment method of ingap and manufacture of semiconductor laser
US5605490A (en) * 1994-09-26 1997-02-25 The United States Of America As Represented By The Secretary Of The Army Method of polishing langasite

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0380543A (en) * 1989-08-24 1991-04-05 Fujitsu Ltd Semiconductor device
JPH0445532A (en) * 1990-06-13 1992-02-14 Sharp Corp Manufacture of semiconductor device
US5605490A (en) * 1994-09-26 1997-02-25 The United States Of America As Represented By The Secretary Of The Army Method of polishing langasite
JPH08130204A (en) * 1994-10-31 1996-05-21 Oki Electric Ind Co Ltd Surface treatment method of ingap and manufacture of semiconductor laser

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