JPH11258266A - Method for making appropriate etching depth by anisotropic etching in production process of semiconductor device and semiconductor device manufactured by applying the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently measure the accuracy of an etching depth in a noncontact manner by a method wherein a pattern which contains a test pattern is formed on a protective film on the face of a wafer, the pattern is changed into a pattern which can observe a change in proportion to the etching depth in the vertical direction and the remaining etching time required for setting a depth to a prescribed value in an inspection is computed. SOLUTION: The 100 plane crystal is used as a surface, and a test pattern 5 is formed in such a way that its L-shaped side 5a becomes a 111 orientation. In this state, an anisotropic etching operation is performed, and the exposed surface of a silicon chip is etched in a direction perpendicular to the surface of a wafer. The image of the test pattern 5 on the surface of the wafer is inspected under a microscope, and a change which is proportional to an etching depth in the vertical direction can be observed as a length A. Then, in the halfway part of an anisotropic etching process, the image of the test pattern 5 is inspected. On the basis of information on its inspection, the remaining etching time required for setting the etching depth to a prescribed value is computed. When the image on the surface of the wafer is observed in this manner, the accuracy of the etching depth can be inspected in a noncontact manner, and the measurement of the etching depth can be made efficient.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for optimizing an etching depth by anisotropic etching in a semiconductor device manufacturing process, and a semiconductor device manufactured by applying the method. The present invention relates to a device such as a semiconductor pressure sensor for processing a micro-mechanical diaphragm or the like by etching.

[0002]

2. Description of the Related Art Semiconductor integrated circuit manufacturing technology has been applied to the manufacture of ultra-small mechanical devices, and has been developed as a micromachine technology for manufacturing various forms of three-dimensional structures on silicon chips for various uses. Ultra-small devices that integrate circuit devices and mechanical devices on a silicon chip have also been developed. A typical one is a semiconductor pressure sensor. A silicon chip is subjected to a deep anisotropic etching process to form a very thin diaphragm, and a sensor circuit for electrically detecting mechanical displacement and deformation of the diaphragm is integrally formed.

In the manufacturing process of this type of semiconductor device, it is extremely important to optimize the etching depth by anisotropic etching (work according to design values) in order to realize a device with high accuracy and high performance. That is what. Thus, in the process of anisotropically etching a silicon wafer, sampling inspection is performed in the middle to measure the etching depth. Then, calculate the remaining etching time required to make the etching depth a specified value,
The remaining etching process is performed.

[0004]

The above-described inspection of the etching depth has been conventionally performed by a stylus inspection. The stylus inspection is a method of measuring the dimension of a step by applying a probe of a precision position measuring device to a step formed by etching the silicon surface. This method has a problem in that it takes a long time for inspection, is inefficient, and is not suitable for mass production lines. Further, since the probe is brought into contact with the wafer to be inspected, the wafer may be damaged or foreign matter may be attached. Therefore, the sample to be inspected cannot be returned to the production line and is discarded. Therefore, the mass production efficiency is reduced.

Further, the above-mentioned stylus inspection is performed on a wafer sampled during the etching process. However, it is extremely difficult to perform this stylus inspection as a final inspection for each chip (device) after dicing. Therefore, the inspection of the etching accuracy of each chip is not performed, and the fact is that at the stage when the device is incorporated into the final product, it is determined that the chip is defective by some kind of inspection. This is another major factor that impairs productivity.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to enable non-contact and efficient measurement of etching depth accuracy by anisotropic etching.

[0007]

In order to achieve the above-mentioned object, a method according to the present invention is characterized by having the following requirements (1) to (4). (1) Anisotropic etching is performed by patterning a protective film on the surface of a semiconductor wafer. (2) A test pattern is formed on a part of the protective film pattern. (3) When the semiconductor wafer is etched in a direction perpendicular to the surface by the anisotropic etching, the image of the test pattern on the surface of the semiconductor wafer is inspected with a microscope or the like, so that the test pattern is vertically oriented. Is formed in a pattern in which a change proportional to the etching depth can be observed. (4) An image of the test pattern is inspected during the anisotropic etching process, and a remaining etching time required for setting the etching depth to a specified value is calculated based on the inspection information.

In this manner, the etching depth can be easily confirmed from the change in the planar shape. Therefore, there is no need to use a stylus, the process is simple and the inspection can be performed quickly, and the device is not damaged, thereby improving the yield.

As specific means for realizing the requirement (3), as shown in FIGS. 2 to 6, a part (reference numeral 7) protruding inward is provided in a part of the pattern, As shown in FIG. 7, a method using the (111) plane can be employed.

In the method satisfying the above requirements, in some cases, it is desirable to form a plurality of types of the test patterns in a large number of device forming areas on the semiconductor wafer. Further, traces of the test pattern remain in the semiconductor device to which the present invention is applied.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a plan configuration of a pressure sensor manufactured by applying the method of the present invention. This is one device that is manufactured simultaneously on a single crystal silicon wafer and divided by dicing. A circular diaphragm 2 is formed at the center of the silicon chip 1 (the periphery is a space by etching), and an electrode film 3 formed on the diaphragm 2 and a substrate surface facing the lower surface side of the diaphragm 2 (see FIG. The capacitance with the electrode film formed on the terminals 4a and 4
b. A test pattern 5 according to the present invention is formed at a position where one corner of the silicon chip 1 does not interfere.

FIG. 2 shows four specific examples of the test pattern 5.
This is shown in FIGS. In anisotropically etching the surface of the silicon chip 1 with KOH or TMAH, first, a silicon oxide film 6 is patterned on the silicon surface as an etching protection film. The test pattern 5 is formed as a part of the pattern of the protective film.

The test pattern 5 in the embodiment of FIG.
It is shaped like a letter. Here, as shown in FIG. 3A, the test pattern 5 is formed such that one side 5a of the L-shape is oriented in the <111> direction with the (100) plane of the silicon single crystal as the surface. Then, as shown in FIG. 3A and FIG. 3A, which is a cross-sectional view taken along the line III-III, the silicon oxide film 6
(10) of the silicon chip 1 (wafer)
0) The surface is exposed.

In this state, when anisotropic etching is performed using an etchant such as TMAH, the exposed surface of the silicon chip 1 is etched in the <100> direction (perpendicular to the wafer surface) of the silicon crystal plane. Go. It is an object of the present invention to finish the vertical etching depth as designed.

At this time, the etching rate in the <100> direction is the fastest, and the etching rate in the <111> direction is the slowest. The etching rate in the <110> direction is faster than the etching rate in the <111> direction. Therefore, the (111) plane including the opened edge portion of the silicon oxide film 6 is exposed (see FIG. 3B). Also, unlike the other vertices, the ridge line of the inside bent portion 7 of the L-shape has a mountain shape (the other portion has a valley shape), and thus is eroded outward (etching proceeds). . As a result, as shown in FIG. 2B, the side 5a of the L-shaped side of the test pattern 5 becomes oblique, and the (110) plane is exposed.

Then, as the etching proceeds, <100>
Digging deep in the direction (perpendicular to the wafer surface), and in the horizontal direction, the etching rate in the <110> direction is faster than the etching rate in the <111> direction.
Etching proceeds in the 10> direction. Thereby, one side 5a
, The remaining length A of the (111) plane gradually decreases. That is, since the remaining length A is proportional to and corresponds to the vertical erosion depth, by measuring the state of the test pattern 5 and the remaining distance A, it is possible to know the depth remaining distance and the like. it can.

Therefore, by inspecting the image of the test pattern on the wafer surface with a microscope or the like, a change proportional to the etching depth in the vertical direction can be observed as the length A.
Therefore, during the anisotropic etching process, the image of the test pattern is inspected, and the remaining etching time required for setting the etching depth to a specified value is calculated based on the inspection information.

The test pattern 5 of the embodiment shown in FIG.
It is formed in a T shape. The two sides 5b and 5c of the T-shaped test pattern 5 used for inspection are different in length. The directions of the sides 5b and 5c are defined as <111>
Direction. As a result, the remaining portions ((110)) from the tips of both sides 5b and 5c when etching is performed for the same time.
Length B, where the (111) plane is exposed without becoming a plane)
C is different. Therefore, when the single crystal silicon wafer is etched in a direction perpendicular to the surface ((100) direction) by anisotropic etching using TMAH or the like, an image of the test pattern 5 on the wafer surface is inspected by a microscope or the like. Thus, a change proportional to the vertical etching depth can be observed as the length B or C. That is, the length of the remaining distance B on the long side 5b side is equal to or less than the upper limit in the allowable range, and the length of the remaining distance C on the short side 5c side is equal to or more than the lower limit in the allowable range. When it fits, it will be a good product.

Therefore, the image of the test pattern is inspected during the anisotropic etching process, and the remaining etching time required for setting the etching depth to a specified value is calculated based on the inspection information. Also, it can be easily confirmed that the range is within a non-defective product.

The test pattern 5 of the embodiment shown in FIG.
It is formed in an H shape. Also in this case, the direction of the two upper and lower parallel sides 5d and 5e at the center is made to coincide with the <111> direction, and the side 5d is shorter. Therefore, T
When a single crystal silicon wafer is etched in a direction perpendicular to the surface by anisotropic etching using MAH,
By inspecting the image of the test pattern 5 on the wafer surface with a microscope or the like, a change proportional to the etching depth in the vertical direction can be observed as the length D or E. That is, the length of the remaining distance E on the long side 5e side is equal to or less than the upper limit of the allowable range, and the length of the remaining distance D on the short side 5d side is equal to or more than the lower limit of the allowable range. When it fits, it will be a good product. Therefore, during the anisotropic etching process, inspect the image of the test pattern,
Based on the inspection information, a remaining etching time required for setting the etching depth to a specified value is calculated. When the (110) plane is formed from both sides in this way, the determination can be performed with higher accuracy.

The test pattern 5 in the embodiment of FIG. 6 is L-shaped as in FIG. 2, but for convenience in measuring the length A with a microscope or the like, a scale 51 along the test pattern 5 is provided. Is formed. As a result, the quality can be easily determined.

FIG. 7 shows another example of the test pattern 5. This corresponds to a case where a single crystal silicon wafer is anisotropically etched with KOH. The test pattern 5 of this embodiment is a square. When a single crystal silicon wafer is anisotropically etched with KOH, the (100) plane of the silicon crystal plane is etched in a direction perpendicular to the wafer surface. It is an object of the present invention to finish the vertical etching depth as designed.

That is, in the case of the square test pattern 5 shown in FIG. 7A, as the etching progresses, as shown in FIG. 7B and FIG. The square of the face becomes smaller and (11
1) The surface increases. And finally, FIG.
(C), the (100) plane disappears as shown in FIG. 8 (B).

Therefore, by inspecting the wafer surface image with a microscope or the like, a change proportional to the etching depth in the vertical direction can be observed as the size of the (100) plane. Therefore, during the anisotropic etching process, the image of the test pattern is inspected, and the remaining etching time required for setting the etching depth to a specified value is calculated based on the inspection information. In addition, by preparing a plurality of square test patterns having different sizes, it is possible to easily know the etching depth by checking to which pattern the (100) plane has disappeared.

The description so far has been about the anisotropic wafer etching process. Through many processes including this process, a target semiconductor device is built on a wafer, and when a wafer processing step is completed, the wafer is cut into individual devices by a dicing process. Then, as an inspection process of the separated individual devices, a step of observing the test pattern 5 on each chip surface with a microscope or the like is set, and an inspection of the etching accuracy of each individual device can be performed.

[0026]

According to the present invention, the etching accuracy can be inspected in a non-contact manner by observing the image of the wafer (or chip) surface with a microscope or the like, so that the inspection can be performed efficiently in a short time and the wafer to be inspected may be damaged. There is no attachment of foreign matter, and therefore, the wafer to be inspected can be returned to the production line for commercialization, and the mass production efficiency is improved. In addition, since the etching accuracy test can be performed on each device after dicing, there is also an effect that a defective product of the etching accuracy can be removed before the mounting process.

[Brief description of the drawings]

FIG. 1 is a plan view of a pressure sensor as an example of a semiconductor device to which the present invention is applied.

FIG. 2 is a diagram showing a form of a test pattern according to a first embodiment of the present invention and changes thereof.

FIG. 3A is a cross-sectional view taken along line III-III in FIG. 2A. (B) is III-III in FIG.
FIG.

FIG. 4 is a diagram showing a form of a test pattern according to a second embodiment of the present invention and changes thereof.

FIG. 5 is a diagram showing a form of a test pattern according to a third embodiment of the present invention and changes thereof.

FIG. 6 is a diagram showing a form of a test pattern according to a fourth embodiment of the present invention and changes thereof.

FIG. 7 is a diagram showing a test pattern according to a fifth embodiment of the present invention and a change thereof.

FIG. 8A is a longitudinal sectional view of FIG. 7B.
(B) is a longitudinal sectional view in FIG. 7 (C).

[Explanation of symbols]

 Reference Signs List 1 silicon chip 2 diaphragm 3 electrode film 4a, 4b terminal 5 test pattern 6 silicon oxide film (protective film) 51 scale

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/84 H01L 21/306 BU

Claims (3)

[Claims] 1. A method for optimizing an etching depth by anisotropic etching in a semiconductor device manufacturing process, which satisfies the following requirements (1) to (4). (1) Anisotropic etching is performed by patterning a protective film on the surface of a semiconductor wafer. (2) A test pattern is formed on a part of the protective film pattern. (3) When the semiconductor wafer is etched in a direction perpendicular to the surface by the anisotropic etching, the image of the test pattern on the surface of the semiconductor wafer is inspected with a microscope or the like, so that the test pattern is vertically oriented. Is formed in a pattern in which a change proportional to the etching depth can be observed. (4) An image of the test pattern is inspected during the anisotropic etching process, and a remaining etching time required for setting the etching depth to a specified value is calculated based on the inspection information. 2. The method according to claim 1, wherein a plurality of types of the test patterns are formed in a large number of device formation areas on the semiconductor wafer. 3. The semiconductor device according to claim 1, wherein a trace of the test pattern remains in the method according to claim 1 or 2.