CN115588604A - Semiconductor material with good heat resistance for electronic communication industry and preparation method thereof - Google Patents

Semiconductor material with good heat resistance for electronic communication industry and preparation method thereof Download PDF

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Publication number
CN115588604A
CN115588604A CN202210953550.XA CN202210953550A CN115588604A CN 115588604 A CN115588604 A CN 115588604A CN 202210953550 A CN202210953550 A CN 202210953550A CN 115588604 A CN115588604 A CN 115588604A
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wafer
etching
heat resistance
good heat
electronic communication
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林佳琪
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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Abstract

The invention discloses a semiconductor material with good heat resistance for the electronic communication industry and a preparation method thereof, relating to the technical field of electronic communication and comprising the following raw materials: 8-10 parts of cadmium sulfide, 35-40 parts of silicon carbide, 25-30 parts of indium phosphide, 10-12.5 parts of polyacrylonitrile and 18-20 parts of gallium arsenide. The semiconductor material with good heat resistance for the electronic communication industry has good heat resistance, ensures the stability of a crystal in the actual electrifying use process, uses pure oxygen to generate a silicon dioxide layer through dry oxidation, ensures that an oxide layer on the surface of a wafer is thin and compact, improves the precision of the semiconductor material, effectively removes photoresist in an uncovered area of a pattern through spraying a developer on the wafer after photoetching is completed, and enables a printed circuit pattern to be displayed. After the development is finished, the circuit diagram drawing quality is ensured by checking through various measuring equipment and an optical microscope, etching is carried out through reactive ion etching, and the ion anisotropy characteristic can be utilized by RIE.

Description

Semiconductor material with good heat resistance for electronic communication industry and preparation method thereof
Technical Field
The invention relates to the technical field of electronic communication, in particular to a semiconductor material with good heat resistance for the electronic communication industry and a preparation method thereof.
Background
Electronic and communication, which is the combination of electronic science, technology and information technology, constructs the engineering field of modern information society, utilizes the basic theory of electronic science, technology and information technology to solve the technical problems of electronic components, integrated circuits, electronic control, instruments and meters, computer design and manufacture and the related fields of electronic and communication engineering, researches the theory and technology of detection, transmission, exchange, processing and display of electronic information, uses semiconductor materials mostly in the electronic and communication industries, the semiconductor materials can be classified according to chemical compositions, and then separately lists amorphous state and liquid semiconductor with special structure and performance as a class. Semiconductor materials can be classified into elemental semiconductors, inorganic compound semiconductors, organic compound semiconductors, and amorphous and liquid semiconductors according to such classification methods.
The existing semiconductor material used in the electronic and communication industries generally has insufficient heat resistance, and is influenced by temperature in the actual use process, so that the conditions of abnormal work and communication failure of electronic communication equipment are caused.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a semiconductor material with good heat resistance for the electronic communication industry and a preparation method thereof, and solves the problems in the background technology.
In order to achieve the purpose, the invention is realized by the following technical scheme, and the semiconductor material with good heat resistance for the electronic communication industry comprises the following raw materials: 8-10 parts of cadmium sulfide, 35-40 parts of silicon carbide, 25-30 parts of indium phosphide, 10-12.5 parts of polyacrylonitrile and 18-20 parts of gallium arsenide.
Optionally, the preparation method of the semiconductor material with good heat resistance for the electronic communication industry comprises the following steps:
s1, preparing a wafer
Firstly, sequentially putting cadmium sulfide, silicon carbide, phosphorus and polyacrylonitrile with a specified proportion content into a heating tank for heating, enabling the cadmium sulfide, the silicon carbide, the phosphorus and the polyacrylonitrile to be mutually fused, adding gallium arsenide after the fusion is completed, fusing again, cooling the fused silicon to obtain a silicon column after the fusion is completed, cutting off two ends of the silicon column by using a diamond saw, cutting the silicon column into slices with the same thickness, wherein the diameter of each slice determines the size of a wafer, adding a 'flat zone' or a 'dent' mark on each slice after the silicon column is cut, conveniently setting a processing direction according to the mark standard in the subsequent steps, grinding the slices to remove surface flaws, then polishing to form a smooth surface, and removing residual pollutants by cleaning to obtain a finished product wafer with a clean surface;
s2, oxidizing photoetching
Carrying out oxidation treatment on the finished product wafer prepared in the step S1, firstly removing organic matters and metal impurities in the wafer and evaporating residual moisture, then placing the wafer in a high-temperature environment, forming silicon dioxide by flowing oxygen on the surface of the wafer, coating photoresist on the silicon dioxide after oxidation, enabling the wafer to become 'photographic paper' by changing chemical properties through the photoresist, covering the wafer with a photoresist film, completing circuit printing by controlling light irradiation through photoetching, printing a circuit on the wafer with the photoresist film coated below when light passes through a mask containing a circuit pattern, spraying a developer on the wafer after photoetching, effectively removing the photoresist in an area uncovered by the pattern by spraying the developer on the wafer after photoetching, and displaying the printed circuit pattern, wherein the wafer needs to be inspected through various measuring equipment and an optical microscope after development is completed, so that the drawing quality of the circuit pattern is ensured;
s3, etching and depositing
After the wafer is subjected to photoetching in S2, removing any redundant oxide film through etching, only leaving a semiconductor circuit diagram, etching the wafer, and etching through reactive ion etching, wherein RIE (reactive ion etching) can utilize the characteristic of ion anisotropy to realize the etching of high-fineness patterns, then depositing the etched wafer, and the precursor gas can perform chemical reaction in the reaction cavity and generate a film attached to the surface of the wafer;
s4, wafer interconnection
S3, after the etching and deposition of the wafer are completed, copper interconnection is carried out on the wafer, copper filling is carried out on a channel and a via hole etched on the surface of the wafer, a metal circuit pattern is formed on the surface of the wafer, redundant copper after filling is removed by a metal Chemical Mechanical Polishing (CMP) method, an oxide film can be deposited after the completion, the redundant film is removed by photoetching and etching processes, and the whole copper interconnection process needs to be repeated continuously until the copper interconnection is completed;
s5, electrifying test
Testing the wafers after the wafers are interconnected, applying temperature and AC/DC voltage to the wafers to perform aging test of the wafers, performing temperature, speed and motion test on the wafers through the probe card, automatically sorting the wafers which fail to pass the electrical test according to test data values by a system, repairing the sorted wafers, and finally testing the repaired wafers again until the test is qualified;
s6, packaging and warehousing
Through the process treatment of S1-S5, single chips with the same size can be formed on the wafer, the semiconductor chips are cut along the scribing lines on the wafer until the semiconductor chips are separated, the chips are attached to the lead frame after being separated from the wafer, the semiconductor chips are protected through the lead frame and can be subjected to electric signal exchange with an external circuit, liquid adhesive can be used when the chips are attached, then the chips are connected, the chips are packaged after the connection is completed, the semiconductor integrated circuit is protected from the influence of temperature, humidity and external conditions, the semiconductor integrated circuit is subjected to final defect test such as test equipment after the packaging is completed, and the semiconductor integrated circuit is stored in a warehouse after the test.
Optionally, the temperature of the wafer surface oxidation in the step S2 oxidation photolithography process is 1100 ℃.
Optionally, in the step S2, an oxidation manner in the oxidation lithography process is specifically dry oxidation, and a lithography manner is specifically EUV ultraviolet lithography.
Optionally, in the etching deposition process in step S3, the etching mode is specifically reactive ion etching, and the deposition mode is specifically chemical vapor deposition.
Optionally, the cutting mode in the packaging and warehousing process in the step S6 is specifically laser cutting.
The invention provides a semiconductor material with good heat resistance for the electronic communication industry, which has the following beneficial effects: the semiconductor material with good heat resistance for the electronic communication industry has good heat resistance, ensures the stability of crystals in the actual electrifying use process, generates a silicon dioxide layer by using dry oxidation, ensures that the oxide layer on the surface of a wafer is thin and compact, improves the precision of the semiconductor material, effectively removes photoresist in the area where the pattern is not covered by the pattern by spraying developer on the wafer after photoetching is completed, thereby showing the printed circuit pattern, needs to be checked by various measuring equipment and an optical microscope after the development is completed, ensures the drawing quality of the circuit diagram, etches by reactive ion etching, RIE can utilize the characteristic of ion anisotropy, realizes the etching of the pattern with high fineness, reduces the reaction temperature by a chemical vapor deposition mode, reduces the deposition times, brings higher-quality films, interconnects the wafers by copper, has higher device connection speed, has higher reliability, and better resists electromigration.
Detailed description of the invention
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to specific embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
A semiconductor material with good heat resistance for the electronic communication industry comprises the following raw materials: 8 parts of cadmium sulfide, 35 parts of silicon carbide, 25 parts of indium phosphide, 10 parts of polyacrylonitrile and 18 parts of gallium arsenide.
Detailed description of the invention
A semiconductor material with good heat resistance for the electronic communication industry comprises the following raw materials: 9 parts of cadmium sulfide, 38 parts of silicon carbide, 28 parts of indium phosphide, 11.5 parts of polyacrylonitrile and 19 parts of gallium arsenide.
Detailed description of the invention
A semiconductor material with good heat resistance for the electronic communication industry comprises the following raw materials: 10 parts of cadmium sulfide, 40 parts of silicon carbide, 30 parts of indium phosphide, 12.5 parts of polyacrylonitrile and 20 parts of gallium arsenide.
The preparation method of the semiconductor material with good heat resistance for the electronic communication industry comprises the following specific steps:
s1, preparing a wafer
Firstly, sequentially putting cadmium sulfide, silicon carbide, phosphorus and polyacrylonitrile with a specified proportion content into a heating tank for heating, enabling the cadmium sulfide, the silicon carbide, the phosphorus and the polyacrylonitrile to be mutually fused, adding gallium arsenide after the fusion is completed, fusing again, cooling the fused silicon to obtain a silicon column after the fusion is completed, cutting off two ends of the silicon column by using a diamond saw, cutting the silicon column into slices with the same thickness, wherein the diameter of each slice determines the size of a wafer, adding a 'flat zone' or a 'dent' mark on each slice after the silicon column is cut, conveniently setting a processing direction according to the mark standard in the subsequent steps, grinding the slices to remove surface flaws, then polishing to form a smooth surface, and removing residual pollutants by cleaning to obtain a finished product wafer with a clean surface;
s2, oxidizing photoetching
Carrying out oxidation treatment on the finished product wafer prepared in the step S1, firstly removing organic matters and metal impurities in the wafer and evaporating residual moisture, then placing the wafer in a high-temperature environment, forming silicon dioxide by flowing oxygen on the surface of the wafer, coating photoresist on the silicon dioxide after oxidation, enabling the wafer to be 'photographic paper' by changing chemical properties of the photoresist, covering a photoresist film on the wafer, controlling light irradiation through photoetching to complete circuit printing, printing a circuit on the wafer with the photoresist film coated thereunder when light passes through a mask containing a circuit pattern, spraying a developer on the wafer after photoetching, effectively removing the photoresist in an area uncovered by the pattern by spraying the developer on the wafer after photoetching is completed, displaying the printed circuit pattern, and inspecting the circuit pattern by various measuring equipment and an optical microscope after the development is completed to ensure the drawing quality of the circuit pattern;
the temperature of wafer surface oxidation in the oxidation photoetching process is 1100 ℃;
in the oxidation photoetching process, the oxidation mode is dry oxidation, and the photoetching mode is EUV ultraviolet photoetching;
s3, etching and depositing
After the wafer is subjected to photoetching in S2, removing any redundant oxide film through etching, only leaving a semiconductor circuit diagram, etching the wafer, and etching through reactive ion etching, wherein RIE (reactive ion etching) can utilize the characteristic of ion anisotropy to realize the etching of high-fineness patterns, then depositing the etched wafer, and the precursor gas can perform chemical reaction in the reaction cavity and generate a thin film attached to the surface of the wafer;
the etching mode in the etching deposition process is specifically reactive ion etching, and the deposition mode is specifically chemical vapor deposition;
s4, wafer interconnection
S3, after the etching and deposition of the wafer are completed, copper interconnection is carried out on the wafer, copper filling is carried out on etched channels and via holes on the surface of the wafer, so that metal circuit patterns are formed on the surface of the wafer, redundant copper after filling is removed by a metal Chemical Mechanical Polishing (CMP) method, an oxide film can be deposited after the completion, redundant films can be removed by photoetching and etching processes, and the whole copper interconnection process needs to be repeated continuously until the copper interconnection is completed;
s5, electrifying test
Testing the wafers after the wafers are interconnected, applying temperature and AC/DC voltage to the wafers to perform aging test of the wafers, performing temperature, speed and motion test on the wafers through the probe card, automatically sorting the wafers which fail to pass the electrical test according to test data values by a system, repairing the sorted wafers, and finally testing the repaired wafers again until the test is qualified;
s6, packaging and warehousing
Through the process treatment of S1-S5, single chips with the same size can be formed on the wafer, the semiconductor chips are cut along scribing lines on the wafer until the semiconductor chips are separated, the chips are attached to the lead frame after being separated from the wafer, the semiconductor chips are protected through the lead frame and can perform electric signal exchange with an external circuit, liquid adhesive can be used when the chips are attached, then the chips are connected, the chips are packaged after the connection is completed, the semiconductor integrated circuit is protected from the influence of temperature, humidity and external conditions, the chips are subjected to final defect testing such as testing equipment after the packaging, and the chips are stored in a warehouse after the testing;
the cutting mode in the packaging and warehousing process is specifically laser cutting.
In summary, the preparation method of the semiconductor material with good heat resistance for the electronic communication industry comprises the following specific steps:
s1, preparing a wafer
Firstly, sequentially putting cadmium sulfide, silicon carbide, phosphorus and polyacrylonitrile with a specified proportion content into a heating tank for heating, enabling the cadmium sulfide, the silicon carbide, the phosphorus and the polyacrylonitrile to be mutually fused, adding gallium arsenide after the fusion is completed, fusing again, cooling the fused silicon to obtain a silicon column after the fusion is completed, cutting off two ends of the silicon column by using a diamond saw, cutting the silicon column into slices with the same thickness, wherein the diameter of each slice determines the size of a wafer, adding a 'flat zone' or a 'dent' mark on each slice after the silicon column is cut, conveniently setting a processing direction according to the mark standard in the subsequent steps, grinding the slices to remove surface flaws, then polishing to form a smooth surface, and removing residual pollutants by cleaning to obtain a finished product wafer with a clean surface;
carrying out oxidation treatment on the finished product wafer prepared in the step S1, firstly removing organic matters and metal impurities in the wafer and evaporating residual moisture, then placing the wafer in a high-temperature environment, forming silicon dioxide by flowing oxygen on the surface of the wafer, coating photoresist on the silicon dioxide after oxidation, enabling the wafer to be 'photographic paper' by changing chemical properties of the photoresist, covering a photoresist film on the wafer, controlling light irradiation through photoetching to complete circuit printing, printing a circuit on the wafer with the photoresist film coated thereunder when light passes through a mask containing a circuit pattern, spraying a developer on the wafer after photoetching, effectively removing the photoresist in an area uncovered by the pattern by spraying the developer on the wafer after photoetching is completed, displaying the printed circuit pattern, and inspecting the circuit pattern by various measuring equipment and an optical microscope after the development is completed to ensure the drawing quality of the circuit pattern;
after the photoetching of the wafer is completed in the S2, removing any redundant oxide film through etching, only leaving a semiconductor circuit diagram, etching the wafer, etching through reactive ion etching, and RIE (reactive ion etching) can utilize the characteristic of ion anisotropy to realize the etching of high-fineness patterns, then depositing the etched wafer, wherein precursor gas can generate chemical reaction in a reaction cavity and generate a film attached to the surface of the wafer, and through a chemical vapor deposition mode, the reaction temperature is reduced, the deposition times are reduced, and a high-quality film is brought to enable the surface of the wafer to be alternately stacked with a plurality of thin metal films;
s3, after the etching and deposition of the wafer are completed, copper interconnection is carried out on the wafer, copper filling is carried out on etched channels and via holes on the surface of the wafer, so that metal circuit patterns are formed on the surface of the wafer, redundant copper after filling is removed by a metal Chemical Mechanical Polishing (CMP) method, an oxide film can be deposited after the completion, redundant films can be removed by photoetching and etching processes, and the whole copper interconnection process needs to be repeated continuously until the copper interconnection is completed;
testing the wafers after the wafers are interconnected, applying temperature and AC/DC voltage to the wafers to perform aging test of the wafers, performing temperature, speed and motion test on the wafers through the probe card, automatically sorting the wafers which fail to pass the electrical test according to test data values by a system, repairing the sorted wafers, and finally testing the repaired wafers again until the test is qualified;
through the process treatment of S1-S5, single chips with the same size can be formed on the wafer, the semiconductor chips are cut along the scribing lines on the wafer until the semiconductor chips are separated, the chips are attached to the lead frame after being separated from the wafer, the semiconductor chips are protected through the lead frame and can be subjected to electric signal exchange with an external circuit, liquid adhesive can be used when the chips are attached, then the chips are connected, the chips are packaged after the connection is completed, the semiconductor integrated circuit is protected from the influence of temperature, humidity and external conditions, the semiconductor integrated circuit is subjected to final defect test such as test equipment after the packaging is completed, and the semiconductor integrated circuit is stored in a warehouse after the test.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered as the technical solutions and the inventive concepts of the present invention within the technical scope of the present invention.

Claims (6)

1. A semiconductor material with good heat resistance for the electronic communication industry is characterized by comprising the following raw materials: 8-10 parts of cadmium sulfide, 35-40 parts of silicon carbide, 25-30 parts of indium phosphide, 10-12.5 parts of polyacrylonitrile and 18-20 parts of gallium arsenide.
2. The method for preparing the semiconductor material with good heat resistance for the electronic communication industry according to claim 1, characterized by comprising the following specific steps:
s1, preparing a wafer
Firstly, sequentially putting cadmium sulfide, silicon carbide, phosphorus and polyacrylonitrile with a specified proportion content into a heating tank for heating, enabling the cadmium sulfide, the silicon carbide, the phosphorus and the polyacrylonitrile to be mutually fused, adding gallium arsenide after the fusion is completed, fusing again, cooling the fused silicon to obtain a silicon column after the fusion is completed, cutting off two ends of the silicon column by using a diamond saw, cutting the silicon column into slices with the same thickness, wherein the diameter of each slice determines the size of a wafer, adding a 'flat zone' or a 'dent' mark on each slice after the silicon column is cut, conveniently setting a processing direction according to the mark standard in the subsequent steps, grinding the slices to remove surface flaws, then polishing to form a smooth surface, and removing residual pollutants by cleaning to obtain a finished product wafer with a clean surface;
s2, oxidizing photoetching
Carrying out oxidation treatment on the finished product wafer prepared in the step S1, firstly removing organic matters and metal impurities in the wafer and evaporating residual moisture, then placing the wafer in a high-temperature environment, forming silicon dioxide by flowing oxygen on the surface of the wafer, coating photoresist on the silicon dioxide after oxidation, enabling the wafer to be 'photographic paper' by changing chemical properties of the photoresist, covering a photoresist film on the wafer, controlling light irradiation through photoetching to complete circuit printing, printing a circuit on the wafer with the photoresist film coated thereunder when light passes through a mask containing a circuit pattern, spraying a developer on the wafer after photoetching, effectively removing the photoresist in an area uncovered by the pattern by spraying the developer on the wafer after photoetching is completed, displaying the printed circuit pattern, and inspecting the circuit pattern by various measuring equipment and an optical microscope after the development is completed to ensure the drawing quality of the circuit pattern;
s3, etching and depositing
After the wafer is subjected to photoetching in S2, removing any redundant oxide film through etching, only leaving a semiconductor circuit diagram, etching the wafer, and etching through reactive ion etching, wherein RIE (reactive ion etching) can utilize the characteristic of ion anisotropy to realize the etching of high-fineness patterns, then depositing the etched wafer, and the precursor gas can perform chemical reaction in the reaction cavity and generate a film attached to the surface of the wafer;
s4, wafer interconnection
S3, after the etching and deposition of the wafer are completed, copper interconnection is carried out on the wafer, copper filling is carried out on a channel and a via hole etched on the surface of the wafer, a metal circuit pattern is formed on the surface of the wafer, redundant copper after filling is removed by a metal Chemical Mechanical Polishing (CMP) method, an oxide film can be deposited after the completion, the redundant film is removed by photoetching and etching processes, and the whole copper interconnection process needs to be repeated continuously until the copper interconnection is completed;
s5, electrifying test
Testing the wafers after the wafers are interconnected, applying temperature and AC/DC voltage to the wafers to perform aging test of the wafers, performing temperature, speed and motion test on the wafers through the probe card, automatically sorting the wafers which fail to pass the electrical test according to test data values by a system, repairing the sorted wafers, and finally testing the repaired wafers again until the test is qualified;
s6, packaging and warehousing
Through the process treatment of S1-S5, single chips with the same size can be formed on the wafer, the semiconductor chips are cut along the scribing lines on the wafer until the semiconductor chips are separated, the chips are attached to the lead frame after being separated from the wafer, the semiconductor chips are protected through the lead frame and can be subjected to electric signal exchange with an external circuit, liquid adhesive can be used when the chips are attached, then the chips are connected, the chips are packaged after the connection is completed, the semiconductor integrated circuit is protected from the influence of temperature, humidity and external conditions, the semiconductor integrated circuit is subjected to final defect test such as test equipment after the packaging is completed, and the semiconductor integrated circuit is stored in a warehouse after the test.
3. The method for preparing the semiconductor material with good heat resistance for the electronic communication industry according to claim 2, wherein the method comprises the following steps: the temperature of wafer surface oxidation in the step S2 oxidation photoetching process is 1100 ℃.
4. The method for preparing the semiconductor material with good heat resistance for the electronic communication industry according to claim 2, wherein the method comprises the following steps: in the step S2, the oxidation mode in the oxidation lithography process is specifically dry oxidation, and the lithography mode is specifically EUV ultraviolet lithography.
5. The method for preparing the semiconductor material with good heat resistance for the electronic communication industry according to claim 2, wherein the method comprises the following steps: in the etching and deposition process of the step S3, the etching mode is specifically reactive ion etching, and the deposition mode is specifically chemical vapor deposition.
6. The method for preparing the semiconductor material with good heat resistance for the electronic communication industry according to claim 2, wherein the method comprises the following steps: and S6, the cutting mode in the packaging and warehousing process is specifically laser cutting.
CN202210953550.XA 2022-08-10 2022-08-10 Semiconductor material with good heat resistance for electronic communication industry and preparation method thereof Pending CN115588604A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116207078A (en) * 2023-04-28 2023-06-02 智科博芯(北京)科技有限公司 Chip structure and manufacturing and testing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116207078A (en) * 2023-04-28 2023-06-02 智科博芯(北京)科技有限公司 Chip structure and manufacturing and testing method thereof

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