JPH0443309B2 - - Google Patents

Info

Publication number
JPH0443309B2
JPH0443309B2 JP58002044A JP204483A JPH0443309B2 JP H0443309 B2 JPH0443309 B2 JP H0443309B2 JP 58002044 A JP58002044 A JP 58002044A JP 204483 A JP204483 A JP 204483A JP H0443309 B2 JPH0443309 B2 JP H0443309B2
Authority
JP
Japan
Prior art keywords
signal
bit
delay
bits
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58002044A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59127171A (ja
Inventor
Seiichiro Iwase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP58002044A priority Critical patent/JPS59127171A/ja
Publication of JPS59127171A publication Critical patent/JPS59127171A/ja
Publication of JPH0443309B2 publication Critical patent/JPH0443309B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Processing Of Color Television Signals (AREA)
JP58002044A 1983-01-10 1983-01-10 ディジタル信号処理回路 Granted JPS59127171A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58002044A JPS59127171A (ja) 1983-01-10 1983-01-10 ディジタル信号処理回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58002044A JPS59127171A (ja) 1983-01-10 1983-01-10 ディジタル信号処理回路

Publications (2)

Publication Number Publication Date
JPS59127171A JPS59127171A (ja) 1984-07-21
JPH0443309B2 true JPH0443309B2 (enrdf_load_stackoverflow) 1992-07-16

Family

ID=11518322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58002044A Granted JPS59127171A (ja) 1983-01-10 1983-01-10 ディジタル信号処理回路

Country Status (1)

Country Link
JP (1) JPS59127171A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0239704A (ja) * 1988-07-29 1990-02-08 Tech Res & Dev Inst Of Japan Def Agency アダプティブアンテナ装置

Also Published As

Publication number Publication date
JPS59127171A (ja) 1984-07-21

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