JPH0442597A - Manufacture of ceramic multilayered wiring board - Google Patents
Manufacture of ceramic multilayered wiring boardInfo
- Publication number
- JPH0442597A JPH0442597A JP15125990A JP15125990A JPH0442597A JP H0442597 A JPH0442597 A JP H0442597A JP 15125990 A JP15125990 A JP 15125990A JP 15125990 A JP15125990 A JP 15125990A JP H0442597 A JPH0442597 A JP H0442597A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic
- board
- conductive
- wiring board
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000463 material Substances 0.000 claims abstract description 36
- 229910000679 solder Inorganic materials 0.000 claims abstract description 35
- 239000011230 binding agent Substances 0.000 claims abstract description 7
- 239000011342 resin composition Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 25
- 238000010438 heat treatment Methods 0.000 abstract description 14
- 230000008018 melting Effects 0.000 abstract description 9
- 238000002844 melting Methods 0.000 abstract description 9
- 230000035939 shock Effects 0.000 abstract description 7
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 5
- 238000005476 soldering Methods 0.000 abstract description 5
- 239000003795 chemical substances by application Substances 0.000 abstract description 2
- 239000007767 bonding agent Substances 0.000 abstract 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 239000000853 adhesive Substances 0.000 description 11
- 230000001070 adhesive effect Effects 0.000 description 11
- 229910052802 copper Inorganic materials 0.000 description 10
- 239000010949 copper Substances 0.000 description 10
- 239000011521 glass Substances 0.000 description 8
- 239000000203 mixture Substances 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000010304 firing Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、セラミック基板複数枚が積層接着されてな
るセラミック多層配線板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a ceramic multilayer wiring board in which a plurality of ceramic substrates are laminated and bonded.
近年、電子機器の小型化・軽量化に伴い、電子回路の実
現のために使われている配線板に高密度化が強く要請さ
れている。セラミック配線板においても例外ではなく、
高密度化のために、多層化が検討・提案されている。In recent years, as electronic devices have become smaller and lighter, there has been a strong demand for higher density wiring boards used to implement electronic circuits. Ceramic wiring boards are no exception.
Multi-layering is being considered and proposed for higher density.
例えば、導体ペーストを回路パターンで印刷したセラミ
ック基板前段階のセラミックグリーンシートを積み重ね
て焼成するという方法があるが、焼成の際にワレ易いと
か、反り易いとかという問題がある。For example, there is a method of stacking and firing ceramic green sheets that are printed with conductor paste in a circuit pattern before a ceramic substrate, but this method has problems such as being prone to cracking or warping during firing.
そこで、上記ワレや反りの問題を解消するため、グリー
ンシートではない基板化・回路化処理をしたセラミック
基板複数を得ておいて、これらを、回路における基板間
導通用部分が高温(800℃程度)処理型導電性接合材
を介して対面するとともに他の部分がガラス組成物の絶
縁性接着剤を介するようにして重ね合わせておいて、加
圧加熱する方法がある(尾野他;電子材料 1988年
5月P、64〜68頁)。しかしながら、この方法でも
、反りの問題が十分に改善されたとは言い難(、また、
セラミック基板間接着部分の耐熱衝撃性が十分でないと
いう問題がある。Therefore, in order to solve the problem of cracking and warping mentioned above, we obtained a plurality of ceramic substrates that were processed into substrates and circuits instead of using green sheets, and used them to heat the conductive parts between the substrates in the circuit at a high temperature (approximately 800 degrees Celsius). ) There is a method in which the two parts are placed facing each other through a treated conductive bonding material and the other parts are overlapped through an insulating adhesive made of a glass composition, and then heated under pressure (Ono et al.; Electronic Materials 1988). May P, pp. 64-68). However, even with this method, it cannot be said that the problem of warping has been sufficiently improved (,
There is a problem that the thermal shock resistance of the bonded portion between the ceramic substrates is insufficient.
この発明は、上記事情に鑑み、反りが生じ難く、セラミ
ック基板間接着部分の耐熱衝撃性が優れたセラミック多
層配線板を得ることのできる方法を提供することを課題
とする。In view of the above circumstances, it is an object of the present invention to provide a method for obtaining a ceramic multilayer wiring board that is less likely to warp and has excellent thermal shock resistance at bonded portions between ceramic substrates.
前記課題を解決するため、この発明にかかるセラミック
多層配線板の製造方法では、回路が形成された複数のセ
ラミック基板を、回路における基板間導通用部分が導電
性接合材を介して対面するようにして重ね合わせておい
て、加熱処理するにあたり、前記導電性接合材を、樹脂
組成物をバインダーとする導電ペーストおよび/または
半田材とするようにしている。In order to solve the above problem, in the method for manufacturing a ceramic multilayer wiring board according to the present invention, a plurality of ceramic substrates on which circuits are formed are arranged so that the parts for conduction between the boards in the circuits face each other via a conductive bonding material. The electrically conductive bonding material is a electrically conductive paste and/or a solder material using a resin composition as a binder when the electrically conductive bonding material is stacked on top of each other and subjected to heat treatment.
この発明で使う回路形成済のセラミック基板としては、
セラミック基板に無電解メツキ等のメツキ法、あるいは
、スパッタリング等の蒸着法により金属層(例えば、銅
層)を形成しフォトリソグラフィ技術を利用してパター
ン化して回路を設けたものが挙げられる。この他、導電
ペーストを所定パターンで印刷し焼成したものも挙げら
れるが、前者の金属層形成・パターン化の方が微細な回
路形成が可能であり、回路自体の電気抵抗が低いという
利点もある。セラミック基板は、さらに、抵抗素子や半
導体素子も搭載され)(IC(ハイブリッドIC)化さ
れたものであってもよい。また、セラミック基板の厚み
は、通常、0.3〜1n程度である。The circuit-formed ceramic substrate used in this invention is as follows:
Examples include those in which a metal layer (for example, a copper layer) is formed on a ceramic substrate by a plating method such as electroless plating or a vapor deposition method such as sputtering, and then patterned using photolithography technology to provide a circuit. Another option is to print a conductive paste in a predetermined pattern and fire it, but the former method of forming a metal layer and patterning allows for the formation of finer circuits, and has the advantage that the electrical resistance of the circuit itself is lower. . The ceramic substrate may further include a resistive element and a semiconductor element (IC (hybrid IC)).The thickness of the ceramic substrate is usually about 0.3 to 1 nm.
この発明では導電性接合材として、樹脂組成物(例えば
、エポキシ樹脂組成物の如き熱硬化性樹脂組成物)をバ
インダーとする導電ペースト、半田材が単独または併用
される。導電ペーストの場合、スクリーン印刷法等でセ
ラミック基板表面の所定位置に塗布するようにする。半
田材の場合、半田ペースト(半田粉末とビビクルを混練
したクリーム状物)を用いてスクリーン印刷法等でセラ
ミック基板表面の所定位置に塗布するか、半田浴への浸
漬によりセラミック基板表面の所定位置に付着させる等
の方法がある。In the present invention, as the conductive bonding material, a conductive paste having a resin composition (for example, a thermosetting resin composition such as an epoxy resin composition) as a binder and a solder material are used alone or in combination. In the case of a conductive paste, it is applied to a predetermined position on the surface of the ceramic substrate using a screen printing method or the like. In the case of solder material, solder paste (a creamy mixture of solder powder and vehicle) is applied to a predetermined position on the surface of a ceramic substrate using a screen printing method, or it is applied to a predetermined position on the surface of a ceramic substrate by dipping it in a solder bath. There are methods such as attaching it to
熱処理は、通常、導電ペーストの場合は200℃以下の
温度、半田材の場合は250℃以下の温度の条件で行い
、0.1〜1 kg/cIa程度の圧力をかけるように
することが好ましい。Heat treatment is usually performed at a temperature of 200°C or lower for conductive pastes and 250°C or lower for solder materials, and preferably at a pressure of about 0.1 to 1 kg/cIa. .
続いて、図面を参照しながら、製造の一例の流れを説明
する。Next, an example of the flow of manufacturing will be described with reference to the drawings.
まず、第1図(a)にみるように、スルーホール用孔2
.2付のセラミック基板(厚み0.5鶴、縦10at、
横10am)1.1′を準備し、これを、270〜33
0℃程度の85%リン酸浴中に3〜10分間浸漬し表面
を粗化処理する。つぎに、通常の厚付は無電解銅メツキ
法により、基板表面を厚み10nの銅層で覆い、第1図
中)にみるように、通常のフォトリソグラフィ技術を利
用して銅層をパターン化しスルーホールを含む回路3・
・・を形成する。この場合、回路での最小線幅、最小線
間距離を50n程度とすることが十分に可能である。First, as shown in Fig. 1(a), the through-hole hole 2
.. Ceramic board with 2 (thickness 0.5, length 10at,
Prepare 1.1' (width 10am) and connect it to 270~33
The surface is roughened by immersing it in an 85% phosphoric acid bath at about 0° C. for 3 to 10 minutes. Next, the surface of the substrate is covered with a 10 nm thick copper layer using an electroless copper plating method, and the copper layer is patterned using normal photolithography technology, as shown in Figure 1). Circuit 3 including through holes
... to form. In this case, it is fully possible to set the minimum line width and minimum line distance in the circuit to about 50n.
続いて、第1図(C)にみるように、半導体素子5、抵
抗素子6および絶縁層7を設ける。セラミック基板1の
場合、市販の半田レジストを、回路3における基板間導
通用部分(導通用電極)3aおよび半導体素子5実装部
分を除いて塗布し硬化して絶縁層7を形成した後、半導
体素子5をハンダ付けする。勿論、半導体素子は、直接
基板上に接合されていてもよい。セラミック基板1′の
場合、抵抗素子6を形成した後、市販の半田レジストを
、回路3の基板間導通用部分(導通用電極)3aを除い
て塗布し硬化して絶縁層7を形成する。抵抗素子6の形
成には、通常のN2焼成型抵抗体ペースト、あるいは、
有機系抵抗体ペーストが使われる。なお、絶縁層はガラ
ス組成物を用いて形成してもよい。Subsequently, as shown in FIG. 1(C), a semiconductor element 5, a resistance element 6, and an insulating layer 7 are provided. In the case of the ceramic substrate 1, a commercially available solder resist is applied to the circuit 3 except for the inter-board conduction part (conduction electrode) 3a and the part where the semiconductor element 5 is mounted and cured to form the insulating layer 7. Solder 5. Of course, the semiconductor element may be directly bonded onto the substrate. In the case of the ceramic substrate 1', after the resistance element 6 is formed, a commercially available solder resist is applied to the circuit 3 except for the inter-substrate conduction portion (conduction electrode) 3a and hardened to form the insulating layer 7. To form the resistor element 6, a normal N2 fired resistor paste or
Organic resistor paste is used. Note that the insulating layer may be formed using a glass composition.
素子等の搭載後、第1図(dlにみるように、セラミッ
ク基板1′の基板間導通用部分3’aに導電性接合材と
して、樹脂組成物をバインダーとする導電ペースト8を
デイスペンサーにより塗布する。そして、セラミック基
板1.1′を基板間導通用部分3a、3′aが導電性接
合材を介して対面するようにして重ね合わせておいて、
例えば、N黛雰囲気下、150℃の条件で加圧加熱する
と、導電ペーストが硬化して基板間導通用部分3a、3
′aが結合し、第1図(e)にみるように、セラミック
多層配線板が完成する。After mounting the elements, etc., as shown in FIG. Then, stack the ceramic substrates 1.1' so that the inter-substrate conductive parts 3a and 3'a face each other with the conductive bonding material in between,
For example, if the conductive paste is heated under pressure at 150° C. in a nitrogen atmosphere, the conductive paste will harden and the conductive parts 3a and 3 will be hardened.
'a are combined, and a ceramic multilayer wiring board is completed as shown in FIG. 1(e).
第1図(e)に示すセラミック多層配線板は、導電ペー
ストのみで基板間を接着させるようにしたが、絶縁層7
表面の少なくとも一部に有機系接着剤(例えば、半田レ
ジスト)を塗布し前記加圧加熱を行うようにしてもよい
。半田材と有機系接着剤を併用する場合、最初、加圧加
熱し接着剤を硬化させ、ついで、半田溶融温度以上の温
度で(無圧でもよい)熱処理する。接着剤の分だけ、基
板間の接着力が高くなる。In the ceramic multilayer wiring board shown in FIG. 1(e), the boards were bonded together using only a conductive paste, but
An organic adhesive (for example, solder resist) may be applied to at least a portion of the surface, and the pressure and heating may be performed. When a solder material and an organic adhesive are used together, the adhesive is first cured by pressure heating, and then heat-treated at a temperature equal to or higher than the solder melting temperature (no pressure may be used). The adhesive force between the substrates increases by the amount of adhesive.
なお、導電性接合材として、半田材を用いる場合には、
加熱温度は半田溶融温度以上とする。In addition, when using solder material as the conductive bonding material,
The heating temperature shall be higher than the solder melting temperature.
もちろん、この発明は、上記−例に限らない。Of course, the invention is not limited to the above example.
例えば、基板表面の粗化処理は省略してもよい。For example, the roughening treatment on the substrate surface may be omitted.
重ね合わせたセラミック基板枚数は2枚であったが、重
ね合せる基板枚数に制限はなく、3枚、4枚・・・と多
数枚であってもよいことは言うまでもない。さらに、導
電性接合材を、もう一方のセラミック基板1にも設ける
ようにしてもよい。Although the number of stacked ceramic substrates was two, there is no limit to the number of stacked ceramic substrates, and it goes without saying that it may be as many as three, four, and so on. Furthermore, the conductive bonding material may also be provided on the other ceramic substrate 1.
この発明にかかるセラミック多層配線板の製造方法では
、導電性接合材として、熱処理温度の低くて済む樹脂組
成物をバインダーとする導電ペーストおよび/または半
田材からなるものを用い、従来よりも低い温度の熱処理
でセラミック基板を積層接着させるため、反りが生じ難
い。また、処理温度が低いので、接着剤を併用し接着力
を高める場合にも有機系接着剤で事足り、ガラス組成物
で基板間を直に結合することはしないので、基板間接着
部分の耐熱衝撃性が良くなる。ガラス組成物による直結
合は、それ以降の加工工程で加わる熱衝撃でガラス部分
に割れが入り易くて弱いのである。In the method for manufacturing a ceramic multilayer wiring board according to the present invention, a conductive paste and/or a solder material whose binder is a resin composition that requires a low heat treatment temperature is used as the conductive bonding material, and the temperature is lower than that of the conventional method. Because the ceramic substrates are laminated and bonded through heat treatment, warping is less likely to occur. In addition, since the processing temperature is low, even if an adhesive is used in combination to increase the adhesive strength, an organic adhesive is sufficient, and the glass composition does not directly bond the substrates, so the thermal shock resistance of the bonded part between the substrates is reduced. Sexuality improves. Direct bonding using a glass composition is weak, as the glass portion is prone to cracking due to thermal shock applied during subsequent processing steps.
以下、この発明の詳細な説明する。この発明は下記の実
施例に限らない。The present invention will be explained in detail below. This invention is not limited to the following embodiments.
一実施例1−
まず、スルーホール用孔付の96%アルミナ基板(厚み
0.5 m 、縦10CI11、横10cm)3枚それ
ぞれの表面を、高速スパッタリング法により、基板表面
を厚み10μの銅層で覆い、通常のフォトリソグラフィ
技術を利用してパターン化しスルーホールを含む回路・
・・を形成した。回路での最小線幅、最小線間距離は5
0Ir@である。Example 1 - First, the surface of each of three 96% alumina substrates (thickness 0.5 m, length 10 CI 11, width 10 cm) with holes for through holes was coated with a 10 μ thick copper layer by high-speed sputtering. The circuits and through-holes are then patterned using conventional photolithography techniques.
... was formed. The minimum line width and minimum line distance in the circuit is 5
0Ir@.
ついで、N、焼成型抵抗体ペーストを用い、抵抗素子を
形成した後、セラミック基板の回路における基板間導通
用部分以外の部分を半田レジストで覆い、熱処理し絶縁
層を形成した。Next, a resistive element was formed using N, fired type resistor paste, and then a portion of the circuit of the ceramic substrate other than the inter-board conduction portion was covered with a solder resist and heat treated to form an insulating layer.
つぎに、セラミック基板の基板間導通用部分に導電性接
合材としてエポキシ系樹脂組成物をバインダーとする銅
(導電)ペーストをデイスペンサーにより塗布し、3枚
のセラミック基板を基板間導通用部分が導電ペーストを
介して対面するようにして重ね合わせておいて、N2雰
囲気下、150℃の条件で加圧加熱すると、導電ペース
トが硬化し基板間導通用部分が結合して、セラミック多
層配線板が完成した。得られたセラミック多層配線板で
は、電気的導通、基板間密着力がいずれも十分な状態で
あった。Next, a copper (conductive) paste with an epoxy resin composition as a binder is applied as a conductive bonding material to the part for inter-board conduction of the ceramic substrates using a dispenser, and the three ceramic boards are connected to the part for inter-board conduction. They are stacked facing each other with conductive paste interposed between them, and when heated under pressure at 150°C in an N2 atmosphere, the conductive paste hardens and the conductive parts between the boards are bonded, forming a ceramic multilayer wiring board. completed. The obtained ceramic multilayer wiring board had sufficient electrical continuity and adhesion between the substrates.
実施例2−
導電性接合材として、市゛販の半田ペーストを用い、N
、雰囲気下、半田溶融温度を越す230℃の条件で加圧
加熱した後、放冷することで半田を固化させるようにし
た他は、実施例1と同様にしてセラミック多層配線板を
得たが、電気的導通、基板間密着力はいずれも十分であ
った。Example 2 - Commercially available solder paste was used as the conductive bonding material, and N
A ceramic multilayer wiring board was obtained in the same manner as in Example 1, except that the solder was heated under pressure in an atmosphere at 230° C., which exceeds the solder melting temperature, and then allowed to cool to solidify the solder. , electrical conductivity, and adhesion between the substrates were all sufficient.
一実施例3−
まず、96%アルミナ基板(厚み0.5 wa 、縦1
0口、横10cm)2枚それぞれの表面に、スクリーン
法により高温処理型の銅ペーストを、所定パターンで印
刷した。印刷パターンでの最小線幅、最小線間距離は1
50μである。Example 3 - First, a 96% alumina substrate (thickness 0.5 wa, length 1
A high-temperature-treated copper paste was printed in a predetermined pattern on the surface of each of the two sheets (width 10 cm) using a screen method. The minimum line width and minimum distance between lines in the printing pattern is 1
It is 50μ.
ついで、N2焼成型抵抗体ペーストを所定位置に印刷す
るとともに、セラミック基板の回路における基板間導通
用部分以外の部分をガラスペーストで覆い、Nオ雰囲気
下、950℃の温度で焼成し、回路、抵抗素子および絶
縁層を同時に形成した。Next, N2 firing type resistor paste was printed in a predetermined position, and the parts of the circuit on the ceramic board other than the part for inter-board conduction were covered with glass paste, and fired at a temperature of 950°C in an N2 atmosphere to complete the circuit. A resistive element and an insulating layer were formed at the same time.
以後、実施例1と同様にしてセラミック多層配線板を得
た。完成したセラミック多層配線板では、電気的導通、
基板間密着力がいずれも十分な状態であった。Thereafter, a ceramic multilayer wiring board was obtained in the same manner as in Example 1. The completed ceramic multilayer wiring board has electrical continuity,
Adhesion between the substrates was in a sufficient state in all cases.
一実施例4−
スルーホール用孔付の96%アルミナ基板(厚み0.5
鶴、縦10QII、横10co+)2枚を準備し、これ
を、300℃程度の85%リン酸浴中に5分間浸漬し表
面を粗化処理した。つぎに、通常の厚付は無電解銅メツ
キ法により、基板表面を厚み10μの銅層で覆い、通常
のフォトリソグラフィ技術を利用して銅層を選択的にエ
ツチング処理してパターン化しスルーホールを含む回路
を形成した。回路での最小線幅、最小線間距離は50μ
程度である。Example 4 - 96% alumina substrate (thickness 0.5
Two pieces of paper crane (10QII length, 10CO+ width) were prepared and immersed in an 85% phosphoric acid bath at about 300° C. for 5 minutes to roughen the surface. Next, the surface of the board is covered with a copper layer with a thickness of 10 μm using an electroless copper plating method, and the copper layer is selectively etched and patterned using normal photolithography technology to form through holes. A circuit containing the following was formed. The minimum line width and minimum line distance in the circuit is 50μ
That's about it.
続いて、1枚のセラミック基板に関し、有機系抵抗体ペ
ーストを所定の位置に塗布し硬化させ抵抗素子を形成し
た後、基板間導通用部分以外の部分に市販の半田レジス
トを塗布して熱処理し絶縁層を形成した。Next, an organic resistor paste is applied to a predetermined position on one ceramic substrate and cured to form a resistance element, and then a commercially available solder resist is applied to the parts other than the parts for inter-board conduction and heat-treated. An insulating layer was formed.
また、もう1枚のセラミック基板に関しては、基板間導
通用部分以外の部分に市販の半田レジストを塗布して熱
処理し絶縁層を形成した後、半導体素子をハンダ付けし
た。Regarding the other ceramic substrate, a commercially available solder resist was applied to the parts other than the parts for inter-board conduction, and after heat treatment was performed to form an insulating layer, a semiconductor element was soldered.
その後、実施例1と同様にして、セラミック多層配線板
を得た。Thereafter, in the same manner as in Example 1, a ceramic multilayer wiring board was obtained.
実施例5−
導電性接合材用の導体ペーストの塗布の後、絶縁層表面
の数個所に有機系接着剤である半田レジストをデイスペ
ンサーで塗布した後、加圧加熱するようにした他は、実
施例4と同様にしてセラミック多層配線板を得た。Example 5 - After applying the conductive paste for the conductive bonding material, a solder resist, which is an organic adhesive, was applied to several places on the surface of the insulating layer using a dispenser, and then pressure and heating were performed. A ceramic multilayer wiring board was obtained in the same manner as in Example 4.
実施例4のセラミック多層配線板に比べ、実施例5のセ
ラミック多層配線板は、接着剤を併用したので、基板間
の接着力がより十分なものとなっていた。Compared to the ceramic multilayer wiring board of Example 4, the ceramic multilayer wiring board of Example 5 had more sufficient adhesion between the boards because an adhesive was used in combination.
一比較例1一
実施例3において、基板間導通用部分に銅粉末、ガラス
粉末およびビヒクルからなる高温焼成型の導電性接合材
を塗布しておいて、N8中、900℃の温度で加圧加熱
し基板間をガラス組成物たる絶縁層で直に結合させるよ
うにした他は、同様にしてセラミック多層配線板を得た
。Comparative Example 1 In Example 3, a high-temperature firing type conductive bonding material made of copper powder, glass powder, and vehicle is applied to the conductive part between the boards, and then pressure is applied at a temperature of 900°C in N8. A ceramic multilayer wiring board was obtained in the same manner except that the substrates were heated and directly bonded to each other through an insulating layer made of a glass composition.
比較例1のセラミック多層配線板は、実施例3のものに
比べ、反りが大きく、基板間接着部分の耐熱衝撃性が低
かった。The ceramic multilayer wiring board of Comparative Example 1 had greater warpage than that of Example 3, and the thermal shock resistance of the bonded portion between the boards was low.
以上に述べたように、この発明にかかるセラミック多層
配線板の製造方法では、セラミック基板の積層接着の際
の熱処理温度が従来よりも低いために反り難く、しかも
、セラミック基板をガラス組成物で直に接合せずに済む
ため、基板間接着部分の熱衝撃特性を向上させることが
できる。As described above, in the method for manufacturing a ceramic multilayer wiring board according to the present invention, the heat treatment temperature during lamination bonding of ceramic substrates is lower than that in the past, so warping is less likely to occur. Since there is no need to bond the substrates to each other, it is possible to improve the thermal shock characteristics of the bonded portion between the substrates.
第1図は、この発明のセラミック多層配線板の製造方法
の一例を実施するときの工程を説明するための模式的断
面図である。
1.1′・・・回路が形成されたセラミック基板3・・
・回路 3a、3 / a・・・基板間導通用部分8
・・・導電ペースト
手続補正書(帥
第1図
(d)
1.1略牛のJしR
特願平2−151259号
2、発明の名称
セラミック多層配線板の製造方法
3、補正をする者
事件との関係 特許出願人
住 所 大阪府門真市大字門真1048番地
名 称(583)松下電工株式会社
代表者 (懐価役三好俊夫
4、代理人
6、補正の対象
明細書
7、補正の内容
■ 明細書第4頁第6〜8行に「また、セラミック基板
の・・・程度である。」とあるを、「勿論、半導体素子
等が半田により実装されている場合には、その半田が溶
けない温度で多層化がなされる。また、セラミック基板
の厚みは、通常、0.1〜1■程度である。」と訂正す
る。
■ 明細書第5頁第1〜3行に「半田材の場合は・・・
好ましい。」とあるを、「半田材の場合は400℃以下
の温度の条件で行い、0.1〜1 kg/ant程度の
圧力をかけるようにすることが好ましい。
なお、多層板とした後、半導体素子等の部品を実装する
ために行われるハンダリフロー工程で基板間の半田が溶
けて基板がずれないように、ハンダリフロー温度以上の
融点(液相温度)を有する高温半田材を用いるのが好ま
しい。」と訂正する。
■ 明細書第6頁第15行に「デイスペンサー」とある
を、「デイスペンサーあるいは周知のスクリーン印刷」
と訂正する。
■ 明細書第7頁第2行と第3行の間に「ここでは、半
導体素子等の部品が実装された基板を多層化する方法に
ついて説明したが、勿論、半導体素子等の部品は多層化
した後で実装するようにしてもよいことは言うまでもな
い。」を挿入する。
■ 明細書第9頁第12〜13行に「デイスペンサー」
とあるを、「スクリーン印刷」と訂正する。
■ 明細書第12頁第3行に「ハンダ付けした。」とあ
るを、「融点183℃の半田材を用いハンダ付した。」
と訂正する。
■ 明細書第12頁第15行と第16行の間に下記の文
言を挿入する。
[一実施例6
導電性接合材として、市販の液相温度240℃を有する
高温半田ペーストを用い、N2雰囲気下、半田溶融温度
を越す280℃で加熱加圧した後、放冷することで半田
を固化させるようにした他は、実施例1と同様にしてセ
ラミック多層配線板を得たが、
電気的導通、
基板間密着力はいずれも
十分であった。
」FIG. 1 is a schematic cross-sectional view for explaining steps in carrying out an example of the method for manufacturing a ceramic multilayer wiring board of the present invention. 1.1'... Ceramic substrate 3 on which a circuit is formed...
・Circuit 3a, 3/a...Inter-board conduction part 8
... Conductive Paste Procedure Amendment (Fig. 1(d) 1.1 Abbreviation of JushiR Patent Application No. 151259/1999 2, Name of Invention Method for Manufacturing Ceramic Multilayer Wiring Board 3, Person Making Amendment) Relationship to the case Patent applicant address 1048 Oaza Kadoma, Kadoma City, Osaka Name (583) Representative of Matsushita Electric Works Co., Ltd. (Kaikaishi Toshio Miyoshi 4, Agent 6, Specification subject to amendment 7, Contents of amendment ■ On page 4, lines 6 to 8 of the specification, it says, "Also, the same level as for ceramic substrates." Multi-layering is done at a temperature that does not melt.Also, the thickness of the ceramic substrate is usually about 0.1 to 1 inch.''.■ It is corrected to read ``Solder material'' on page 5, lines 1 to 3 of the specification. In the case of···
preferable. "In the case of soldering materials, it is preferable to conduct the soldering at a temperature of 400°C or less and apply a pressure of about 0.1 to 1 kg/ant. Furthermore, after forming a multilayer board, it is preferable to conduct In order to prevent the solder between the boards from melting and shifting during the solder reflow process used to mount components such as elements, it is preferable to use a high-temperature solder material that has a melting point (liquidus temperature) higher than the solder reflow temperature. ”, he corrected. ■ On page 6, line 15 of the specification, the word "dispenser" has been replaced with "dispenser or well-known screen printing."
I am corrected. ■ On page 7 of the specification, between the second and third lines, it says, ``Here, we have explained a method for multilayering a board on which components such as semiconductor elements are mounted. It goes without saying that you can implement it later." ■ “Dispenser” on page 9, lines 12-13 of the specification
Correct the statement to "screen printing." ■ On page 12, line 3 of the specification, the phrase "soldered" was replaced with "soldered using a solder material with a melting point of 183°C."
I am corrected. ■ Insert the following text between lines 15 and 16 on page 12 of the specification. [Example 6] A commercially available high-temperature solder paste with a liquidus temperature of 240°C was used as the conductive bonding material, and after heating and pressurizing it at 280°C, which exceeds the solder melting temperature, in an N2 atmosphere, the solder was soldered by allowing it to cool. A ceramic multilayer wiring board was obtained in the same manner as in Example 1, except that the ceramic multilayer wiring board was solidified, and the electrical conductivity and adhesion between the boards were both sufficient. ”
Claims (1)
おける基板間導通用部分が導電性接合材を介して対面す
るようにして重ね合わせておいて、加熱処理するように
するセラミック多層配線板の製造方法において、前記導
電性接合材が、樹脂組成物をバインダーとする導電ペー
ストおよび/または半田材からなることを特徴とするセ
ラミック多層配線板の製造方法。1. Manufacturing a ceramic multilayer wiring board in which a plurality of ceramic substrates on which circuits are formed are stacked so that the conductive parts between the circuits face each other via a conductive bonding material, and then heat treated. A method for manufacturing a ceramic multilayer wiring board, characterized in that the conductive bonding material comprises a conductive paste and/or a solder material using a resin composition as a binder.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15125990A JPH0442597A (en) | 1990-06-08 | 1990-06-08 | Manufacture of ceramic multilayered wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15125990A JPH0442597A (en) | 1990-06-08 | 1990-06-08 | Manufacture of ceramic multilayered wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0442597A true JPH0442597A (en) | 1992-02-13 |
Family
ID=15514756
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15125990A Pending JPH0442597A (en) | 1990-06-08 | 1990-06-08 | Manufacture of ceramic multilayered wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0442597A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017060256A (en) * | 2015-09-15 | 2017-03-23 | 株式会社オートネットワーク技術研究所 | Circuit structure and electric connection box |
-
1990
- 1990-06-08 JP JP15125990A patent/JPH0442597A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017060256A (en) * | 2015-09-15 | 2017-03-23 | 株式会社オートネットワーク技術研究所 | Circuit structure and electric connection box |
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