JPH0440733B2 - - Google Patents
Info
- Publication number
- JPH0440733B2 JPH0440733B2 JP57172104A JP17210482A JPH0440733B2 JP H0440733 B2 JPH0440733 B2 JP H0440733B2 JP 57172104 A JP57172104 A JP 57172104A JP 17210482 A JP17210482 A JP 17210482A JP H0440733 B2 JPH0440733 B2 JP H0440733B2
- Authority
- JP
- Japan
- Prior art keywords
- phase
- microinstruction
- register
- control memory
- microinstructions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57172104A JPS5971549A (ja) | 1982-09-30 | 1982-09-30 | マイクロプログラムによる仮処置方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57172104A JPS5971549A (ja) | 1982-09-30 | 1982-09-30 | マイクロプログラムによる仮処置方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5971549A JPS5971549A (ja) | 1984-04-23 |
| JPH0440733B2 true JPH0440733B2 (cs) | 1992-07-06 |
Family
ID=15935616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57172104A Granted JPS5971549A (ja) | 1982-09-30 | 1982-09-30 | マイクロプログラムによる仮処置方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5971549A (cs) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5029731B2 (ja) | 2010-07-08 | 2012-09-19 | 富士電機機器制御株式会社 | 電磁接触器 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5736347A (en) * | 1980-08-13 | 1982-02-27 | Nec Corp | Data processing equipment |
-
1982
- 1982-09-30 JP JP57172104A patent/JPS5971549A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5971549A (ja) | 1984-04-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5594741A (en) | Method for control of random test vector generation | |
| GB1274830A (en) | Data processing system | |
| JPS62249226A (ja) | プログラム可能論理装置およびその方法 | |
| JPS6231439B2 (cs) | ||
| JPH0769791B2 (ja) | マイクロプロセッサ | |
| JPH0440733B2 (cs) | ||
| JPS59211146A (ja) | スキヤンイン方法 | |
| JP3771393B2 (ja) | 半導体記憶装置、この半導体記憶装置を搭載した回路基板、および、この半導体記憶装置の接続試験方法 | |
| JP2924968B2 (ja) | 時間双方向シミュレーション装置 | |
| RU2034329C1 (ru) | Устройство управления | |
| JP2581214B2 (ja) | 論理シミュレータ | |
| JPS5814265A (ja) | ワンチツプマイクロコンピユ−タ | |
| JPH02110792A (ja) | マイクロコンピュータ | |
| JPS62186338A (ja) | シミユレ−シヨンシステム | |
| JPS6367212B2 (cs) | ||
| JPS61161509A (ja) | 高速シ−ケンス演算方式及びその装置 | |
| JPH01142848A (ja) | アドレストラップ回路 | |
| D'Antonoli | Design, Manufacture and Testing of a 4-Bit Microprocessor | |
| JPS6045827B2 (ja) | 試験パタ−ン発生器 | |
| JPS61288243A (ja) | コンペアアンドスワツプ命令処理方式 | |
| JPS59170937A (ja) | 論理演算回路 | |
| JPS63172349A (ja) | Mos大規模集積回路 | |
| Johnson et al. | Abc's Of Processor Design: Introductory Computer Architecture Using The Lis 4 | |
| JPS63129430A (ja) | マイクロプログラム制御装置 | |
| JPS6237745A (ja) | 統合マイクロプログラム制御方式 |