JPS5736347A - Data processing equipment - Google Patents

Data processing equipment

Info

Publication number
JPS5736347A
JPS5736347A JP11124880A JP11124880A JPS5736347A JP S5736347 A JPS5736347 A JP S5736347A JP 11124880 A JP11124880 A JP 11124880A JP 11124880 A JP11124880 A JP 11124880A JP S5736347 A JPS5736347 A JP S5736347A
Authority
JP
Japan
Prior art keywords
instruction
instructions
input
edb
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11124880A
Other languages
Japanese (ja)
Other versions
JPS6150336B2 (en
Inventor
Minoru Matsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11124880A priority Critical patent/JPS5736347A/en
Publication of JPS5736347A publication Critical patent/JPS5736347A/en
Publication of JPS6150336B2 publication Critical patent/JPS6150336B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30178—Runtime instruction translation, e.g. macros of compressed or encrypted instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To enlarge general usage of data processings and to respond instructions having different word lengths which give enlargement of instruction word length, by combining prescribed bits from signal lines and bits from signal lines for expanding instructions, when data are input into instruction controlling equipment. CONSTITUTION:Data of 8 bits which form 1 instruction code are directly input into instruction controlling equipment 1 from signal lines DB0-DB7 of an instruction line 4, and 1 bit from a signal line EDB4' for expanding instruction is input into the equipment 1 through an AND gate 5. Moreover, negative and positive EDB signals are added to an external terminal 6, and, only when the EDB signal is positive, the expansion instruction from the signal line EDB is input into an expansion instruction register 1'. Also, the positive logic of the EDB signal from the terminal 6 is input into the CPU3 as an expansion instruction, and instructions containing expansion instructions are set to registers 1 and 1'. Then, each instruction is decoded by an instruction decoding equipment 2 and an expansions instruction decoding equipment 2', and the decoded instructions are sent to the CPU3, and thus general usage of data processing is expanded.
JP11124880A 1980-08-13 1980-08-13 Data processing equipment Granted JPS5736347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11124880A JPS5736347A (en) 1980-08-13 1980-08-13 Data processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11124880A JPS5736347A (en) 1980-08-13 1980-08-13 Data processing equipment

Publications (2)

Publication Number Publication Date
JPS5736347A true JPS5736347A (en) 1982-02-27
JPS6150336B2 JPS6150336B2 (en) 1986-11-04

Family

ID=14556346

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11124880A Granted JPS5736347A (en) 1980-08-13 1980-08-13 Data processing equipment

Country Status (1)

Country Link
JP (1) JPS5736347A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5971549A (en) * 1982-09-30 1984-04-23 Fujitsu Ltd Tentative processing system by microprogram
EP0924602A2 (en) * 1997-12-17 1999-06-23 Hewlett-Packard Company Instruction masking in providing instruction steams to a processor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5177151A (en) * 1974-12-27 1976-07-03 Nippon Electric Co MAIKUROMEIREIKAKUCHOSOCHI
JPS5397349A (en) * 1977-02-05 1978-08-25 Fujitsu Ltd Order decording system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5177151A (en) * 1974-12-27 1976-07-03 Nippon Electric Co MAIKUROMEIREIKAKUCHOSOCHI
JPS5397349A (en) * 1977-02-05 1978-08-25 Fujitsu Ltd Order decording system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5971549A (en) * 1982-09-30 1984-04-23 Fujitsu Ltd Tentative processing system by microprogram
JPH0440733B2 (en) * 1982-09-30 1992-07-06 Fujitsu Ltd
EP0924602A2 (en) * 1997-12-17 1999-06-23 Hewlett-Packard Company Instruction masking in providing instruction steams to a processor
EP0924602A3 (en) * 1997-12-17 2002-08-14 Elixent Limited Instruction masking in providing instruction steams to a processor

Also Published As

Publication number Publication date
JPS6150336B2 (en) 1986-11-04

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