JPH04370889A - Extension circuit for output port - Google Patents

Abstract

PURPOSE:To obtain an extension circuit for an output port which can convert the serial data signals into more parallel data signals. CONSTITUTION:An output circuit 11 outputs signal data signal Pa, a shift clock signal Pb, and a load clock signal Pc. A data converter 12 is provided with a data input terminal D, a shift clock input terminal SC, a load clock input terminal LC and an output terminal O. Then the circuit 12 reads the signal Pa inputted to the terminal D synchronously with the shift clock signal SC inputted to the terminal SC and in accordance with the logical state of the load signal LC inputted to the terminal LC. Thus the circuit 12 decides the output level of the terminal O and outputs the parallel signals O through plural terminals).

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an expansion circuit for an output port of a computer.

0002

2. Description of the Related Art When a computer controls a certain control object, for example, an engine control computer (ECU) controls an engine, as the control becomes more complex and sophisticated, the number of control objects increases, and the output circuit of the ECU increases. The number of ports is becoming insufficient. In particular, when using a one-chip microcontroller, the computer's internal circuitry cannot be changed, so external circuitry must be used to cope with the lack of ports.

[0003] Therefore, the following method has been considered to expand the output port. FIG. 3 shows an output circuit of a conventional ECU, and in the figure, 21 is an output IC. Here, the output IC 21 is, for example, an output IC of a one-chip microcomputer,
It has three circuits: output ports Pa, Pb, and Pc. If this continues, only three sets of control objects can be controlled at the same time. Therefore, connect the conversion IC22 to the output IC21,
An output port expansion circuit is proposed in which the output IC 21 is configured to output a serial data signal, a shift clock signal, and a load clock signal from output ports Pa, Pb, and Pc.

The conversion IC 22 has three input ports D (D
ata), SC (Shift Clock), LC (L
oadClock) and multiple (
It has 8) output ports O0 to O7 (hereinafter referred to as symbols without subscripts as necessary), and the input ports are connected to the output IC.
and each output port is connected to a controlled device (not shown). As shown in FIG. 4, this conversion IC is
A serial data signal input to input port D is read in synchronization with a shift clock signal input to input port SC, distributed in correspondence to output port O, and converted into a parallel data signal. When the load clock signal input to the input port LC rises, these parallel data signals are output as parallel data signals from the corresponding output ports O.

[0005]

However, the above-described output port expansion circuit has a problem in that the number of control target devices that can be obtained is limited by the number of output ports of the conversion IC. This invention was made in view of the above problems, and provides an output port expansion circuit that converts serial data signals into more parallel data signals and allows more control objects to be controlled at the same time. The purpose is to

[0006]

In order to achieve the above object, an output port expansion circuit of the present invention includes an output circuit that outputs a serial data signal, a shift clock signal, and at least one load clock signal, and a data input circuit. A plurality of data conversion circuits provided with a terminal, a shift clock input terminal, a load clock input terminal, and a plurality of output terminals, and the logic state of the load clock signal output from this output circuit, or the combination of the logic states of the load clock signal. The data conversion circuit has an inverter circuit that outputs a load signal with a different logic state to each data conversion circuit, and the data conversion circuit synchronizes the serial data signal input to the data input terminal with the shift clock signal input to the shift clock terminal. Read and determine the output level of each output terminal,
Parallel signals are output from a plurality of output terminals depending on the logic state of the load signal input to the load clock terminal.

[0007]

[Operation] In the output port expansion circuit of the present invention, a load signal having a different logic state and phase is input from the inverter circuit to each data conversion circuit according to the logic state of the load clock signal output from the output circuit, and these data The conversion circuit reads the serial data signal in synchronization with the shift clock signal according to the logic state of the load signal, determines the output level of each output terminal, and outputs it as a parallel data signal from each output terminal according to the logic state of the load signal. do. Therefore, by increasing the number of data conversion circuits, many parallel data signals can be obtained.

[0008]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 and 2 show an output port expansion circuit according to an embodiment of the present invention, with FIG. 1 being a block diagram and FIG.
is a timing chart for explaining the effect.

FIG. 1 shows an output port expansion device applied to a control device such as an engine, in which 11 is an output IC (output circuit), 12a is a first data conversion IC (data conversion circuit), and 12b is a first data conversion circuit. 2 data conversion IC (data conversion circuit). The output IC 11 has three output ports Pa, P
b, Pc, and outputs a serial data signal from output port Pa, a shift clock signal from output port Pb, and a load signal from output port Pc.

As shown in FIG. 2, which will be described later, the serial data signal (designated Pa for convenience) consists of a 16-bit digital signal divided into 8 bits each, and the shift clock signal (designated Pb for convenience) consists of a 16-bit digital signal divided into 8 bits each. is a digital signal having the same period as the serial data signal, and the load signal (designated by Pc for convenience) is a logic signal having approximately the same period as the serial data signal.

[0011] First and second data conversion circuits 12a,
12b (Hereinafter, numbers without subscripts will be used as needed)
are data input port D (Data) and shift clock input port SC (Shift Clock), respectively.
and load input port LC (Load Clock)
It also has eight output ports O0 to O7 (represented by numbers without subscripts as necessary). These data conversion circuits 12 have a data input port D connected to an output port Pa of the output IC 11, and a shift clock input port S.
C is connected in parallel to the output port Pb, the first data conversion circuit 12a has the load input port LC directly connected to the output port Pc of the output circuit 11, and the second data conversion circuit 12b has the load input port Pc connected directly to the output port Pc of the output circuit 11. It is connected to the output port Pc via the inverter circuit 13. The inverter circuit 13 inverts the load signal Pc output from the output port Pc and outputs it to the load input port LC of the second data conversion circuit 12b.

In the output port expansion circuit of this embodiment, the output IC 11 receives the serial data signal from the port Pa, the shift clock signal from the port Pb, and the output IC 11 from the port Pb.
A load signal is output from c. The serial data signal Pa is input to the port D of each conversion IC 12, the shift clock signal Pb is input to the port SC of each conversion IC 12, and the load signal Pc is input to the port SC of each conversion IC 12a.
The signal is input to the port LC of the conversion IC 12b, and is inverted and input to the port LC of the conversion IC 12b via the inverter circuit 13.

Here, as shown in FIG. 2, the load signal P
If c is L level, the first conversion IC 12a reads the serial data signal Pa in synchronization with the shift clock signal Pb and determines the level of the output ports O0 to O7, and the second conversion IC 12b reads the serial data signal Pa in synchronization with the shift clock signal Pb, and the second conversion IC 12b determines the level of the output ports O0 to O7. An H-level signal inverted by the inverter circuit 13 is input to the inverter circuit 13, and reading of the data signal is prohibited. And load signal Pc
When Pc rises, the first conversion IC 12a outputs parallel data signals O0 to O7 from each output port O0 to O7, and holds the signals until the next rise of load signal Pc. Note that in FIG. 2, the output port and the signal output from the output port are represented by the same reference numerals.

Next, when the load signal Pc is inverted to H level, the first conversion IC 12a is prohibited from reading the serial data signal Pa because the port LC becomes H level, contrary to the above case. 2 conversion IC 12b converts the serial data signal Pa because the port LC changes to L level.
is read in synchronization with shift clock signal Pb. Then, the second conversion IC 12b outputs the parallel data signals O8 to O15 from the output ports O0 to O7 at the falling edge of the load signal Pc, that is, at the rising edge of the inverted signal input to the port LC, and outputs the parallel data signals O8 to O15 to the next port LC. Holds the input signal until it rises.

Thereafter, as the level of the load signal changes, the first conversion IC 12a and the second conversion IC 12b alternately output parallel data signals as described above, and the serial data output from the output IC 11. Signal Pa is converted into 16 parallel data signals O0 to O15.

[0016] In the above embodiment, two conversion ICs are used.
12 is shown as an example, but it is also possible to provide more conversion ICs to convert serial data signals into more parallel data signals. However, in such a configuration, the output IC 11 must be configured to output a plurality of load signals, and these load signals must be converted by an inverter circuit. For example, the four transformations I
If C is provided, output I outputs two types of load signals.
The inverter circuit generates four types of load signals from these two types of load signals and outputs them to each conversion IC.
input to the port.

Furthermore, this output port expansion circuit is unsuitable for control objects that require a fast response speed, such as ignition timing control and fuel injection control, but is not suitable for warning lamps that do not require a fast response speed. It is suitable for use in turning on/off relays of air conditioners and other relays, controlling fuel pumps, etc., and the method of the present invention is preferable for integrating the control of such auxiliary devices into one ECU.

[0018]

As explained above, according to the output port expansion circuit according to the present invention, the load signal is inverted by the inverter circuit, and the load signals having different phases are inputted to the plurality of data conversion circuits. Since the data conversion circuits read serial data signals at different times so that each data conversion circuit converts them into parallel data signals, many parallel data signals can be obtained from one serial data signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an output port expansion circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the output port expansion circuit according to an embodiment of the present invention.

[Figure 3
]Block diagram of conventional output port expansion circuit

[Figure 4] Timing chart for explaining the operation of a conventional output port expansion circuit

[Explanation of symbols]

11... Output IC (output circuit), 12, 12a,
12b... Conversion IC (conversion circuit), 13... Inverter circuit.

Claims (1)

[Claims] 1. A plurality of output circuits that output a serial data signal, a shift clock signal, and at least one type of load clock signal, and a plurality of output terminals provided with a data input terminal, a shift clock input terminal, a load clock input terminal, and a plurality of output terminals. and an inverter circuit that outputs a load signal with a different phase to each data conversion circuit according to the logic state of the load clock signal output by the output circuit or a combination of the logic states of the load clock signal. The conversion circuit determines the output level of each output terminal by reading the serial data signal input to the data input terminal in synchronization with the shift clock signal input to the shift clock terminal according to the logic state of the load signal input to the load clock terminal. An output port expansion circuit characterized in that parallel signals are output from each of the plurality of output terminals.