JPH04369038A - Instruction prefetching device - Google Patents

Abstract

PURPOSE:To improve through-put by compacting the size of a circuit while allowing the circuit to correspond to various instruction word lengths and minimizing a queue state to an instruction execution request. CONSTITUTION:A queue memory 2 forming a series of instruction data storing area of kXn byte length by connecting k n-byte length instruction data temperarily storing registers 2a to a ROM 1 for storing microcomputer program of n-byte reference instruction word length is included in this instruction prefetch device. The device is also provided with a queue management part 5 for controlling the prefetching of each n bytes out of the instruction data of j-byte optional word length from the ROM 1 to the queue memory 2 while always grasping the leading address of instruction data to be read out next from the queue memory 2, the total number of bytes of effective instruction data stored in the memory 2, the batch reading of j-byte length instruction data from the memory 2 by a selector 3 and the transfer of the instruction data to an instruction decoding part 4.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention sequentially prefetches instruction data of a microcomputer stored in a program memory such as a ROM, in order to fetch instructions and execute current processing in parallel. The present invention relates to an instruction prefetch device for sequentially decoding instruction data in an instruction decoding section prior to execution.

0002

2. Description of the Related Art First, a conventional instruction prefetch device will be explained. FIG. 6 is a block diagram showing the configuration of a conventional instruction prefetch device, and FIG. 7 is a conceptual diagram showing the detailed configuration of the queue 22 in FIG. 6 and the flow of instruction data through the queue.

[0003] Microcomputer instructions generally consist of an operation code section that determines the type of instruction and its operation, and an operand section that modifies the operation of the instruction. Figure 6
The conventional instruction prefetch device shown in FIG. The instruction data is sequentially prefetched from the ROM 21 in units of m bytes, and the prefetched instruction data is also transferred in units of m bytes to the instruction decoder 23, where the instruction decoder 23 sequentially decodes them. For this purpose, the present instruction prefetch device includes a queue 22 and a sequence control section 24.

[0004] The queue 22 is a ROM, as shown in FIG.
21 and has an i-stage m-byte long instruction data temporary storage register 22a that sequentially shifts instruction data between them, and the instruction data is read and written in FIFO (first-in first-out) format. It is something that will be done. However, the instruction data read from the queue 22 and transferred to the instruction decoder 23 will be particularly referred to as queue data hereinafter.

[0005] The sequence control unit 24 is provided with free space information of the queue 22, which is updated every time the prefetching of instruction data to the queue 22 is completed, and every time the instruction decoding unit 23 finishes decoding the instruction data. The instruction decoded byte number information, that is, the information regarding the number of bytes of the decoded instruction data is given to the instruction decoded byte number information. The sequence control unit 24 receives this information and outputs a shift clock signal for controlling the FIFO operation of the queue 22, and
It has an address pointer for holding the start address of the next instruction data to be prefetched from the ROM 21, and outputs the contents of the address pointer as a ROM address.

The operation of the conventional instruction prefetch device described above will now be described. In the initial state in which all instruction data temporary storage registers 22a of the queue 22 are empty, the sequence control unit 24 first uses empty cycles to read data from the ROM 21 to the queue 2 until the queue 22 is full.
2, the instruction data is sequentially prefetched in units of m bytes according to the address pointer. At this time, the previously prefetched instruction data advances between the respective instruction data temporary storage registers 22a by a shift clock signal given from the sequence control section 24.

On the other hand, the instruction data prefetched into the queue 22 is sequentially transferred to the instruction decoding section 23 as queue data in units of m bytes by a shift clock signal also applied from the sequence control section 24. The instruction decoding unit 23 executes the instruction decoding after acquiring the opcode part and operand part necessary for the instruction decoding. When the decoding of one instruction is completed, the instruction decoding section 23 sends instruction decoding byte number information to the sequence control section 24 to prompt prefetching of the next instruction data.

[0008] After predicting whether the branch condition in the conditional branch instruction is satisfied or not, the queue 2 is
In some cases, a branch prediction method was adopted in which instruction data was prefetched to the second branch. However, if, for example, the branch condition is predicted to not hold and the prefetch is proceeding, but the branch condition actually holds, then all of the instruction data that has already been prefetched in the queue 22 becomes invalid. If the branch prediction is incorrect in this way, the prefetch must be performed until the queue 22 is filled with instruction data, as in the case of the above initial state where all instruction data temporary storage registers 22a of the queue 22 are empty. Cue data cannot be given to the instruction decoder 23.

[0009]

As mentioned above, in the conventional instruction prefetch device, the queue 22 uses a data shift method in which the instruction data itself is shifted between a plurality of instruction data temporary storage registers 22a. If the branch prediction is incorrect, the instruction decoder 2 must perform prefetching until the queue 22 is filled with instruction data.
Unable to give cue data to 3. Therefore, a waiting state corresponding to the shift time corresponding to the number of stages of the instruction data temporary storage register 22a occurs in response to an instruction execution request, resulting in a decrease in system throughput. Also,
In order to configure the queue 22 using a data shift method, it is necessary to use a master-slave type flip-flop, which poses a problem of increasing the scale of the circuit.

Furthermore, a plurality of instruction data temporary storage registers 22a each having a length of m bytes whose basic size is the instruction operation code width of a microcomputer are arranged in series, and instruction data is stored between the instruction data temporary storage registers 22a.
Since the configuration of the queue 22 is such that the queue is sequentially shifted in units of bytes, there is a problem in that the units of writing and reading from the queue 22 are both limited to units of m bytes. In other words, the instruction word length is a multiple of m bytes (2 m bytes, 3
For instructions with a different number of bytes than m bytes,...),
A part of the instruction data temporary storage register 22a is wasted. In recent years, microcomputers have become more sophisticated and complex, and their instruction word lengths have become more diverse.As mentioned above, the queue 22 in which both the writing unit and the reading unit are fixed to m bytes, This will significantly reduce throughput.

An object of the present invention is to reduce the circuit scale while making it possible to deal with various instruction word lengths, and to improve throughput by minimizing the waiting state for instruction execution requests.

0012

[Means for Solving the Problems] In order to solve the above problems, the present invention forms a series of long instruction data storage areas by arranging a plurality of instruction data temporary storage registers in parallel with a program memory. Adopts a queue memory that makes it possible to write and read instruction data of arbitrary word length j bytes to and from the instruction data storage area, and simultaneously realizes writing and reading of the instruction data to and from any address. This is what I did.

[0013] To explain concretely, the invention of claim 1:
Sequentially prefetching instruction data of an arbitrary word length j bytes from a program memory storing a plurality of instruction data constituting a microcomputer program having a standard instruction word length n bytes in units of n bytes that match the standard instruction word length, and This is an instruction prefetching device for sequentially decoding the prefetched instruction data of arbitrary word length j bytes in an instruction decoding section, which adopts the following configuration including a queue memory, a selector, and a queue management section. be.

That is, the queue memory includes a plurality of instruction data temporary storage registers each having a length of n bytes, which is the same as the standard instruction word length, and the plurality of instruction data temporary storage registers are connected to each other and stored in the program memory. Valid and undeciphered instruction data is stored in the instruction data storage area that is arranged in parallel to the instruction data storage area and can be written to and read from any address, which is configured by the plurality of instruction data temporary storage registers. Instruction data of arbitrary word length j bytes is sequentially prefetched from the program memory into an unstored free area in units of n bytes that match the standard instruction word length, and multiple instruction data of arbitrary word length j bytes are packed into each other without gaps. It is something that can be done.

[0015] The selector also reads out the instruction data of arbitrary word length j bytes prefetched into the queue memory from the specified address of the queue memory, and sends the read instruction data of arbitrary word length j bytes to the instruction decoding section. The information is transferred sequentially.

Further, the queue management section executes prefetching of instruction data from the program memory to the queue memory when at least an n-byte length area corresponding to a prefetch unit of instruction data is secured as a free area in the queue memory; And in parallel with the prefetch, the selector reads the instruction data from the queue memory and transfers the instruction data by giving the queue memory the start address of valid and undeciphered instruction data to be read next from the queue memory. This is what makes it possible to carry out the following.

According to the second aspect of the invention, the instruction data in the queue memory is read to an arbitrary address while always keeping track of the start address of the instruction data to be read next from the queue memory and the total number of bytes of the instruction data in the queue memory. To control writing and reading from arbitrary addresses,
This configuration employs a queue management section that includes the following queue memory pointer, effective byte number register, update means during prefetch, update means during instruction decoding, and prefetch control section.

That is, the queue memory pointer always holds the first address of valid and undeciphered instruction data to be read next from the queue memory as the queue memory read address, and by giving the queue memory read address to the queue memory. This allows the selector to read instruction data from the queue memory and transfer the instruction data.

The effective byte number register always holds the total number of valid and undeciphered instruction data bytes in the queue memory as the effective byte number.

Furthermore, the prefetch update means updates the number of effective bytes by the number n of bytes of the prefetched instruction data every time a prefetch of n byte units matching the standard instruction word length of the instruction data to the queue memory is completed. This updates the effective byte count register to increase the number of bytes.

Furthermore, the instruction decoding update means receives the number j of bytes of the decoded instruction data from the instruction decoder every time the instruction decoder finishes decoding the instruction data of arbitrary word length j bytes, and Every time the number j of bytes of decoded instruction data is given, the number j of bytes of the decoded instruction data
The queue memory pointer is updated to advance the queue memory read address by J, and the effective byte number register is updated to reduce the effective byte number by the number j of bytes of the decoded instruction data.

Finally, the prefetch control unit calculates the start address of the free area in the queue memory and the number of bytes of the free area from the queue memory read address and the number of effective bytes, and uses at least the prefetch unit of instruction data as the free area. When an area with a length of n bytes corresponding to By specifying the start address of a free area in the memory, prefetching of instruction data from the program memory to the queue memory is executed.

[0023]

According to the invention of claim 1, a plurality of instruction data temporary storage registers each having a length of n bytes (constant), which is the same as the standard instruction word length, are connected in parallel to the program memory. A series of instruction data storage areas each having a byte length are formed in the queue memory. The instruction data storage area can be written to and read from any address, and when an area of at least n bytes long is secured as an empty area at any position, the program memory is transferred to the empty area. Instruction data of an arbitrary word length of j bytes is sequentially prefetched in units of n bytes. At this time, a plurality of instruction data having an arbitrary word length of j bytes are packed into the instruction data storage area without any gaps between them.

On the other hand, the queue management section always manages the start address of valid and undeciphered instruction data to be read next from the queue memory, and in parallel with the prefetching of instruction data from the program memory to the queue memory. , the selector reads out instruction data of arbitrary word length j bytes in the queue memory from an address specified by the queue management section, for example, all at once, and sequentially transfers the instruction data to the instruction decoding section. In other words, when the n-byte free space required for prefetching is secured in the queue memory,
Prefetching of instruction data from the program memory to the queue memory is immediately executed, and the prefetched instruction data is immediately read by the selector and transferred to the instruction decoding section without waiting for the queue memory to be filled with instruction data. It is.

According to the second aspect of the invention, the start address of valid and undeciphered instruction data to be read next from the queue memory is always held in the queue memory pointer as the queue memory read address, and The total number of valid and undeciphered instruction data bytes is always held in the valid byte count register as the valid byte count. The contents of the queue memory pointer are advanced by j bytes by the instruction decoding update means each time the selector completes the transfer of instruction data of arbitrary word length j bytes from the queue memory to the instruction decoding section and the decoding of the instruction data. So,
Its validity is always ensured. In addition, the contents of the effective byte count register are incremented by n bytes by the prefetch update means every time the prefetch of instruction data from the program memory to the queue memory in units of n bytes is completed. Each time the transfer of instruction data of an arbitrary word length of j bytes to the instruction data and the decoding of the instruction data are completed, the instruction decoding update means decreases the number by j bytes, so that its validity is also always ensured.

[0026] The prefetch control unit determines the start address of the free area in the queue memory and the start address of the free area based on the contents of the queue memory pointer and the effective byte number register, that is, the accurate queue memory read address and the effective number of bytes. Calculate the number of bytes. Then, the number of bytes of the free area is checked, and when an area with a length of n bytes that matches at least the prefetch unit of instruction data is secured as the free area, the next instruction data to be prefetched from the program memory is In addition to specifying the start address, the start address of the free area calculated for the queue memory is specified as the queue memory write address for the next instruction data to be prefetched. Thereby, prefetching of instruction data from the program memory to the free area of the queue memory is accurately executed. On the other hand, the queue memory pointer allows the selector to accurately read instruction data from the queue memory by providing a queue memory read address to the queue memory.

[0027]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an instruction prefetch device in an embodiment of the present invention.

The instruction prefetch device shown in the figure sequentially prefetches instruction data of an arbitrary word length of j bytes in units of n bytes from the ROM 1 in which a plurality of instruction data of a microcomputer with a standard instruction word length of n bytes is stored. The prefetched instruction data of arbitrary word length j bytes is sequentially decoded by an instruction decoding section 4, and includes a queue memory 2, a selector 3, and a queue management section 5.

The queue memory 2 has k (k is an integer of 2 or more) instruction data temporary storage registers 2a arranged in parallel with the ROM 1. Each instruction data temporary storage register 2a has a length of n bytes, and is connected to each other to form a series of instruction data storage areas having a total length of k×n bytes. The instruction data storage area of the queue memory 2 temporarily stores instruction data of an arbitrary word length j bytes prefetched from the ROM 1 in units of n bytes, and can be written to and read from any address. It is.

The selector 3 reads the prefetched instruction data of arbitrary word length j bytes into the queue memory 2 from the specified address of the queue memory 2, and transfers the read instruction data of arbitrary word length j bytes to the queue memory. The data is sequentially transferred to the instruction decoder 4 as data.

The queue management unit 5 transfers n bytes from the ROM 1 to the queue memory 2 while always keeping track of the start address of the next instruction data to be read from the queue memory 2 and the total number of bytes of instruction data in the queue memory 2. It controls the prefetching of unit instruction data, and also controls the batch reading of j-byte length instruction data from the queue memory 2 by the selector 3 and the transfer of the instruction data to the instruction decoding section 4. For this purpose, the queue management section 5 receives a prefetch end signal from the queue memory 2, receives the instruction decoding end signal and instruction decoding byte number information from the instruction decoding section 4, and sends the command to the ROM 1 for prefetching instruction data. A ROM address is given to the queue memory 2, a queue memory write address is given to the queue memory 2, and a queue memory read address is given to the queue memory 2 for reading instruction data from the queue memory 2.

FIG. 2 is a block diagram showing the detailed configuration of the queue management section 5. As shown in FIG. As shown in the figure, the queue management section 5
is effective byte number register 11, adder 12, subtracter 1
3. A queue memory pointer 14 and a prefetch control unit 15 are provided.

The effective byte count register 11 always holds the total number of bytes of valid and undeciphered instruction data in the queue memory 2 as the effective byte count, and the queue memory pointer 14 indicates the number of bytes to be read next from the queue memory 2. The head address of valid and undeciphered instruction data is always held as a queue memory read address, and the queue memory read address is outputted to the queue memory 2.

The adder 12 is valid for the number n (fixed value) of bytes of the prefetched instruction data each time the prefetch end signal is given at the end of prefetching the instruction data in units of n bytes to the queue memory 2. The effective byte number register 11 is updated to increase the number of bytes. The subtracter 13 extracts information about the number j (variable value) of the decoded instruction data each time the instruction decoder 4 finishes decoding the instruction data of arbitrary word length j bytes, that is, the instruction decoding byte number information. It is given from the instruction decoding unit 4 along with the instruction decoding end signal, and each time it updates the queue memory pointer 14 so as to advance the queue memory read address by the number j of bytes of the decoded instruction data, and by the same number j of bytes. The effective byte number register 11 is updated to reduce the number of effective bytes.

The prefetch control unit 15 uses the number of effective bytes held by the effective byte number register 11 and the queue memory read address held by the queue memory pointer 14 in order to prefetch instruction data from the ROM 1 to the queue memory 2. The start address of the free area in the queue memory 2 and the number of bytes of the free area are calculated based on Specify the start address of the instruction data to be prefetched next as the ROM address, and specify the start address of the free area for queue memory 2 as the queue memory write address for the instruction data to be prefetched next. It is something.

Next, the operation of the instruction prefetch device according to the present embodiment explained above is as follows: (a) When the instruction data is n bytes (b) When the instruction data is smaller than n bytes (c) When the instruction data is The explanation will be given with reference to FIGS. 3 to 5, which show changes in the prefetch position of instruction data in the queue memory 2 and updates to the queue memory pointer 14 in three cases where the size is larger than n bytes. . However, the unhatched blank areas in FIGS. 3 to 5 indicate empty areas of the queue memory 2, and the hatched areas indicate the queue memory 2 in which valid and undeciphered instruction data is stored.
The effective area of each is shown.

(a) When instruction data is n bytes (a1) to (a5) in FIG. 3 are cases where the word length j (bytes) of the instruction data to be prefetched matches the standard instruction word length n (bytes). This is a diagram. First, as shown in (a1), in the initial state, all registers for temporarily storing instruction data in the queue memory 2 are empty areas, and the contents of the effective byte number register 11 are cleared to 0. In this way, when an area of n bytes or more is secured as a free space in the queue memory 2, prefetching from the ROM 1 to the queue memory 2 is performed using the free cycle. However, in the initial state, as shown in (a1), the leftmost instruction data temporary storage register becomes the first prefetch position.

When n-byte instruction data is actually prefetched to this prefetch position as shown in (a2), the contents of the queue memory pointer 14 are determined so as to specify the start address of the prefetched instruction data. At the same time, the adder 12 increments the contents of the effective byte number register 11 by n. As a result, the prefetch position is updated as shown in (a2),
The next prefetched n-byte instruction data is packed into the previously prefetched n-byte instruction data without any gaps. In parallel with the above prefetching of instruction data into the free area, the instruction data in the queue memory 2 is read for decoding, but if there are many free cycles, the number of prefetches exceeds the number of reads. The queue memory 2 is filled with command data.

The instruction data prefetched into the queue memory 2 is read by the selector 3 from the queue memory read address specified by the queue memory pointer 14 and transferred to the instruction decoder 4 in parallel with the prefetch as described above. be done. As shown in (a3), in a state where all instruction data temporary storage registers of the queue memory 2 are filled with instruction data, for example, the instruction data stored in the leftmost instruction data temporary storage register is read out. When the decoding of the instruction data is completed, the queue management section 5 receives the instruction decoding byte number information (n bytes in this case) from the instruction decoding section 4 and advances the queue memory pointer 14 by n bytes using the subtractor 13. At the same time, the contents of the effective byte number register 11 are decreased by n. As a result, an area with a length of n bytes corresponding to the prefetch unit of instruction data is secured as a free area in the queue memory 2, and the next prefetch becomes possible.

By the way, when the contents of the queue memory pointer 14 advance to the start address of the rightmost instruction data temporary storage register as shown in (a4), the queue memory pointer 14 is set in a ring shape when the next instruction is decoded. Update to. In other words, as shown in (a5), when the rightmost instruction data temporary storage register becomes the next prefetch position at the end of instruction decoding, the queue memory pointer 14 is at the beginning of the leftmost instruction data temporary storage register. Updated to specify the address.

(b) When the instruction data is smaller than n bytes In (b1) to (b5) of FIG. 4, the word length j (bytes) of the instruction data to be prefetched is the standard instruction word length n (bytes).
It is a figure when it is smaller than. As in the case of Figure 3, RO
In parallel with the prefetching of instruction data from M1 to queue memory 2 in units of n bytes, the reading of instruction data from queue memory 2 proceeds, but if there are many empty cycles, the number of prefetching exceeds the number of reading. Therefore, the queue memory 2 is filled with command data. However, the j (<n) byte length instruction data that is prefetched later is packed into the j (<n) byte length instruction data that is prefetched first without any gaps. As a result, as shown in (b1), all instruction data temporary storage registers in the queue memory 2 are filled with instruction data, and the queue memory pointer 14 specifies the start address of the leftmost instruction data temporary storage register. shall have proceeded to.

At this point, as shown in (b2), j(<
n) When byte-length instruction data is extracted by the selector 3 and the decoding of the instruction data is completed, the queue management section 5 receives instruction decoding byte number information from the instruction decoding section 4 (in this case, j bytes, j< n), the subtracter 13 advances the queue memory pointer 14 by j bytes and decrements the contents of the valid byte number register 11 by j in the same manner as described above. However, unlike in case (a) above, the number j of bytes of the decoded instruction data is smaller than n, so if only one instruction data is decoded, the free space in the queue memory 2 will be filled with instruction data. An area of n-byte length, which is a prefetch unit, is not secured, and the next prefetch is not executed immediately. As shown in (b3), the next n-byte unit prefetch becomes possible only when the decoding of the next instruction data is completed.

Note that when the contents of the queue memory pointer 14 advance to the rightmost instruction data temporary storage register as shown in (b4), the queue memory pointer 14 is updated in a ring shape when the next instruction is finished decoding. . In other words,
As shown in (b5), when the rightmost instruction data temporary storage register becomes the next prefetch position at the end of instruction decoding, the queue memory pointer 14 points to the address in the leftmost instruction data temporary storage register. j bytes are updated as instructed.

(c) When the instruction data is larger than n bytes In (c1) to (c4) of FIG. 5, the word length j (bytes) of the instruction data to be prefetched is the standard instruction word length n (bytes).
It is a figure when it is larger than. As in the case of (b), since there are many empty cycles, all of the instruction data temporary storage registers in the queue memory 2 are filled with instruction data as shown in (c1), and the queue memory pointer 14 is set to the leftmost instruction data. Assume that the process proceeds to specify the start address of the temporary storage register. However, in this case as well, the ROM
Prefetching of instruction data from 1 to queue memory 2 is performed in units of n bytes, and the prefetching data is j(
>n) byte length instruction data is packed into the previously prefetched j(>n) byte length instruction data without any gaps.

At this point, as shown in (c2), the j (>n) byte length instruction is stored across the leftmost instruction data temporary storage register and the adjacent instruction data temporary storage register. When the data is extracted by the selector 3 and the decoding of the instruction data is completed, the queue management section 5 receives the instruction decoding byte number information (in this case, j bytes, j>n) from the instruction decoding section 4 and subtracts it. Similarly to the above, the queue memory pointer 14 is advanced by j bytes, and the contents of the valid byte number register 11 are decreased by j. In this case, since the number j of bytes of decoded instruction data is larger than n, the decoding of one instruction data is completed, and an n-byte length area, which is the prefetch unit of instruction data, is used as a free space in the queue memory 2. is secured and the next prefetch can be executed immediately.

Note that when the contents of the queue memory pointer 14 advance to the middle of the rightmost instruction data temporary storage register as shown in (c3), the queue memory pointer 14 is ringed when the next instruction is decoded. Update as follows. At this time, as shown in (c4), the specified address of the queue memory pointer 14 jumps over the leftmost instruction data temporary storage register and reaches the instruction data temporary storage register adjacent to the leftmost instruction data temporary storage register. If the data is advanced, a free area of 2×n bytes can be secured at a time, so prefetching is performed twice in n-byte units successively using the free cycle.

As described above, according to this embodiment, unlike the conventional data shift method, it is possible to write to and read from arbitrary addresses as the queue memory 2 using a plurality of instruction data temporary storage registers 2a. Since a series of instruction data storage areas are formed, the instruction data prefetched into the queue memory 2 is immediately read out by the selector 3 and sent to the instruction decoder 4 without waiting for the queue memory 2 to be filled with instruction data. be transferred. Therefore, even if the initial state or branch prediction is wrong, the waiting state for instruction execution requests is minimized, and throughput is improved. Further, a simple data latch circuit can be used in the configuration of the queue memory 2, and the circuit scale can be reduced.

Furthermore, by concatenating a plurality of instruction data temporary storage registers 2a to form a queue memory 2, a series of instruction data storage areas in which instruction data of arbitrary word length j bytes can be written and read is formed. At the same time, multiple instruction data of arbitrary word length j bytes are packed into the series of instruction data storage areas without gaps between each other, so the queue memory can be used without wastage, and it can flexibly handle various instruction word lengths. It is possible. Moreover, since the size of each of the instruction data temporary storage registers 2a and the prefetch unit of instruction data are made to match the standard instruction word length of a microcomputer, n bytes, the configuration of the interface circuit between the ROM 1 and the queue memory 2 is made It is easy to do this, and the circuit scale can be reduced in this respect as well. Also,
This is convenient for handling a large number of standard instruction data with a standard instruction word length of n bytes, and the highest throughput can be achieved for instruction data with this word length.

Furthermore, it is provided with an effective byte number register 11 and a queue memory pointer 14, which are updated accurately at the time of prefetching and instruction decoding, and based on the effective number of bytes of the queue memory 2 managed by both and the read address. Since the prefetching of instruction data to the queue memory 2 and the reading of instruction data from the queue memory 2 are controlled, the word length of the instruction data is the standard instruction word length n.
Even if the instruction data is different from the byte, the instruction data can be correctly prefetched and the prefetched instruction data can be accurately transferred to the instruction decoder 4.

[0050]

As described above, according to the invention of claim 1, unlike the conventional data shift method, by connecting a plurality of registers for temporarily storing instruction data, writing to an arbitrary address and writing to an arbitrary address can be performed. Since we have adopted a queue memory configuration that forms a series of instruction data storage areas that can be read from, it is possible to specify addresses from any location in the queue memory in parallel with prefetching instruction data into the empty area of the queue memory. The instruction data can be read by In other words, when a free space of the byte length required for prefetching is secured in the queue memory, prefetching of instruction data to the queue memory is immediately executed, and the prefetched instruction data fills the queue memory with instruction data. It is read out immediately and transferred to the instruction decoding section without waiting for the instruction decoder. Therefore, even if the initial state or branch prediction is wrong, the waiting state for instruction execution requests is minimized, and throughput is improved. Further, since the queue memory can be constructed using a simple data latch circuit instead of the master-slave type flip-flop used in the conventional data shift method, the circuit scale can be reduced.

Furthermore, a configuration is adopted that includes a queue memory that forms a series of instruction data storage areas in which instruction data of arbitrary word length j bytes can be written and read by a plurality of mutually connected instruction data temporary storage registers. Moreover, since a plurality of instruction data of arbitrary word length j bytes are packed into the series of instruction data storage area without gaps between each other, the queue memory can be used without waste, and it is possible to flexibly handle various instruction word lengths. I can handle it.

Moreover, since the size of each of the plurality of instruction data temporary storage registers constituting the queue memory and the instruction data prefetch unit are made to match the standard instruction word length of a microcomputer, n bytes, the program memory and the queue are The structure of the interface circuit with the memory is easy, and the circuit scale can also be reduced in this respect. In addition, it is convenient for handling instruction data with a standard instruction word length of n bytes, which is generally large in number, and the highest throughput can be achieved for instruction data of this word length.

Further, according to the invention of claim 2, a queue memory pointer and an effective byte number register are provided which are updated accurately at the time of prefetching and instruction decoding, and the read address and effective byte number register regarding the queue memory managed by both are provided. Since we have adopted a configuration in which prefetching of instruction data into a free area of the queue memory and reading of instruction data from the queue memory are executed based on the number,
Even if the word length of the instruction data is different from the standard instruction word length n bytes, the instruction data can be correctly prefetched and the prefetched instruction data can be accurately transferred to the instruction decoder.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an instruction prefetch device in an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a queue management section in FIG. 1;

FIG. 3 shows the change in the prefetch position of instruction data in the queue memory in FIG. 1 and the update of the queue memory pointer when the word length of the instruction data to be prefetched matches the standard instruction word length n (bytes). FIG.

FIG. 4 is a diagram similar to FIG. 3 in a case where the word length of instruction data to be prefetched is smaller than the standard instruction word length n (bytes).

FIG. 5 is a diagram similar to FIG. 3 in a case where the word length of instruction data to be prefetched is larger than the standard instruction word length n (bytes).

FIG. 6 is a block diagram showing the configuration of a conventional instruction prefetch device.

7 is a conceptual diagram showing the detailed configuration of the queue in FIG. 6 and the flow of command data through the queue; FIG.

[Explanation of symbols]

1...ROM (program memory) 2...Queue memory 2a...Register for temporarily storing instruction data 3...Selector 4...Instruction decoding section 5...Queue management section 11...Valid byte number register 12...Adder (updating means at prefetch) 13... Subtractor (updating means when decoding an instruction) 14...Queue memory pointer 15...Prefetch control unit

Claims (2)

[Claims] Claim 1: Instruction data of an arbitrary word length of j bytes is extracted from a program memory storing a plurality of instruction data constituting a microcomputer program with a standard instruction word length of n bytes in units of n bytes that match the standard instruction word length. An instruction prefetch device for sequentially prefetching and causing an instruction decoding unit to sequentially decode the prefetched instruction data of arbitrary word length j bytes, the instruction prefetching device including a plurality of instructions each having a length of n bytes, which is the same as a standard instruction word length. an arbitrary address configured by the plurality of instruction data temporary storage registers, the plurality of instruction data temporary storage registers being connected to each other and arranged in parallel with the program memory; Out of the instruction data storage area that can be written to and read from any address, instruction data of an arbitrary word length j bytes is transferred from the program memory to an empty area in which valid and undeciphered instruction data is not stored. A queue memory in which a plurality of instruction data of an arbitrary word length j bytes are packed into each other without gaps by sequential prefetching in units of n bytes that match, and an arbitrary word length j prefetched into the queue memory.
a selector for reading byte of instruction data from a specified address of the queue memory and sequentially transferring the read instruction data of arbitrary word length j bytes to the instruction decoder; When an n-byte length area corresponding to a data prefetch unit is secured, prefetching of instruction data from the program memory to the queue memory is executed, and the next data to be read from the queue memory in parallel with the prefetch. and a queue management unit for causing the selector to read instruction data from the queue memory and transfer the instruction data by giving a start address of valid and undeciphered instruction data to the queue memory. Features an instruction prefetch device. 2. The instruction prefetch device according to claim 1, wherein the queue management section always holds a start address of valid and undeciphered instruction data to be read next from the queue memory as a queue memory read address; a queue memory pointer for causing the selector to read instruction data from the queue memory and transfer the instruction data by giving the queue memory read address to the queue memory; and a valid and undeciphered pointer in the queue memory. an effective byte count register for always holding the total number of bytes of instruction data as the effective byte count; the prefetch time updating means for updating the effective byte number register so as to increase the number of effective bytes by the number n of bytes of the instruction data that has been read, and the instruction decoding unit completing the decoding of the instruction data of arbitrary word length j bytes. The number of bytes of instruction data decoded for each j
is given from the instruction decoder, and each time the number j of bytes of the decoded instruction data is given, the queue memory pointer is updated so that the queue memory read address is advanced by the number j of bytes of the decoded instruction data. and updating means for updating the effective byte number register so as to reduce the effective byte number by the number j of bytes of the decoded instruction data; The start address of the free area in the queue memory and the number of bytes of the free area are calculated, and when an area with a length of n bytes that matches at least the prefetch unit of instruction data is secured as the free area, the program by specifying the start address of the instruction data to be prefetched next and specifying the start address of the free area for the queue memory as the queue memory write address for the instruction data to be prefetched next. An instruction prefetch device comprising: a prefetch control unit for prefetching instruction data from a memory to a queue memory.