JPS5627455A - Instruction prefetch system using buffer register with byte aligner - Google Patents

Instruction prefetch system using buffer register with byte aligner

Info

Publication number
JPS5627455A
JPS5627455A JP10239279A JP10239279A JPS5627455A JP S5627455 A JPS5627455 A JP S5627455A JP 10239279 A JP10239279 A JP 10239279A JP 10239279 A JP10239279 A JP 10239279A JP S5627455 A JPS5627455 A JP S5627455A
Authority
JP
Japan
Prior art keywords
instruction
brs
buffer register
empty
byte aligner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10239279A
Other languages
Japanese (ja)
Other versions
JPS612216B2 (en
Inventor
Takeshi Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10239279A priority Critical patent/JPS5627455A/en
Publication of JPS5627455A publication Critical patent/JPS5627455A/en
Publication of JPS612216B2 publication Critical patent/JPS612216B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To make it possible to fetch continuous data without reference to the boundary of words by transferring data to the 1st and 2nd instruction buffer register BRs under the condition of fixed states of BRs by providing a byte aligner circuit at the output side of BRs.
CONSTITUTION: Instructions read out of memory unit 9 are stored in instruction buffer register BRs 12-0 and 12-1 and to the output side of BRs, byte aligner circuit 13 is connected. Instructions are indefinite in length and range from one to eight bytes. Instruction prefetching incrementer 3 sets the contents of instruction address register 1 to +0, +4 or +8 in accordance with states where BR12-0, 12-1 are both empty, where either one is empty or where neither one is empty. Instruction prefetch control part 8, when BR12-0 or 12-1 is emptied, transfers data from an area, assigned by memory address register 7, to the BR. When the fetch of an instruction is commanded, continuous data can be fetched in the order of FIF0 by way of circuit 13 without reference to the boundary of words.
COPYRIGHT: (C)1981,JPO&Japio
JP10239279A 1979-08-10 1979-08-10 Instruction prefetch system using buffer register with byte aligner Granted JPS5627455A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10239279A JPS5627455A (en) 1979-08-10 1979-08-10 Instruction prefetch system using buffer register with byte aligner

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10239279A JPS5627455A (en) 1979-08-10 1979-08-10 Instruction prefetch system using buffer register with byte aligner

Publications (2)

Publication Number Publication Date
JPS5627455A true JPS5627455A (en) 1981-03-17
JPS612216B2 JPS612216B2 (en) 1986-01-23

Family

ID=14326166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10239279A Granted JPS5627455A (en) 1979-08-10 1979-08-10 Instruction prefetch system using buffer register with byte aligner

Country Status (1)

Country Link
JP (1) JPS5627455A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59154546A (en) * 1983-02-24 1984-09-03 Toshiba Corp Information processor
JPS6041137A (en) * 1984-07-11 1985-03-04 Hitachi Ltd Operand reader
JPH04125745A (en) * 1990-09-18 1992-04-27 Fujitsu Ltd Method and device for data write control
JPH04369038A (en) * 1991-06-18 1992-12-21 Matsushita Electric Ind Co Ltd Instruction prefetching device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59154546A (en) * 1983-02-24 1984-09-03 Toshiba Corp Information processor
JPS6041137A (en) * 1984-07-11 1985-03-04 Hitachi Ltd Operand reader
JPH04125745A (en) * 1990-09-18 1992-04-27 Fujitsu Ltd Method and device for data write control
JPH04369038A (en) * 1991-06-18 1992-12-21 Matsushita Electric Ind Co Ltd Instruction prefetching device

Also Published As

Publication number Publication date
JPS612216B2 (en) 1986-01-23

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