JP2682761B2 - Instruction prefetch device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention sequentially prefetches instruction data of a microcomputer stored in a program memory such as a ROM and the like in order to fetch an instruction and execute a current process in parallel. The present invention relates to an instruction prefetch device for sequentially decoding the instruction data by an instruction decoding unit before execution.

[0002]

2. Description of the Related Art First, a conventional instruction prefetch device will be described. FIG. 6 is a block diagram showing the configuration of a conventional instruction prefetch device, and FIG. 7 is a conceptual diagram showing the detailed configuration of the queue 22 in FIG. 6 and the flow of instruction data through the queue.

An instruction of a microcomputer is generally composed of an operation code section which determines the type of the instruction and its operation and an operand section which modifies the operation of the instruction. FIG.
Also, the conventional instruction prefetch device shown in FIG. 7 is configured by using the word length (instruction opcode width) m bytes of the operation code part as a basic size, and stores a plurality of instruction data which constitutes a program. The instruction data is sequentially prefetched (prefetched) from the ROM 21 in units of m bytes, and the prefetched instruction data is also transferred to the instruction decoding unit 23 in units of m bytes and sequentially decoded by the instruction decoding unit. For this purpose, the present instruction prefetch device has a queue 22 and a sequence controller 24.

The queue 22 is a ROM as shown in FIG.
21 has an i-stage m-byte-length instruction data temporary storage register 22a arranged in series with respect to 21 and sequentially shifting instruction data between them, and the instruction data is read / written in a FIFO (first-in / first-out) format. It is what is done. However, the instruction data read from the queue 22 and transferred to the instruction decoding unit 23 will be particularly referred to as queue data hereinafter.

The sequence control section 24 is provided with empty area information of the queue 22 which is updated each time the prefetch of the instruction data to the queue 22 is completed, and every time the instruction decoding section 23 completes the decoding of the instruction data. The instruction decoding byte number information, that is, the information regarding the byte number of the decoded instruction data is given. The sequence control unit 24
Receives the information and outputs a shift clock signal for controlling the FIFO operation of the queue 22, and has an address pointer for holding the start address of the instruction data to be prefetched next from the ROM 21. The contents of the address pointer are output as a ROM address.

The operation of the conventional instruction prefetch device described above will be described. In the initial state in which all the instruction data temporary storage registers 22a of the queue 22 are empty, the sequence controller 24 first uses the empty cycle from the ROM 21 to the queue 2 until the queue 22 becomes full.
2. Instruction data is sequentially prefetched in units of m bytes according to the address pointer. At this time, the prefetched instruction data advances between the instruction data temporary storage registers 22a by the shift clock signal given from the sequence control unit 24.

On the other hand, the instruction data prefetched into the queue 22 is sequentially transferred to the instruction decoding unit 23 as m-byte unit queue data by the shift clock signal similarly supplied from the sequence control unit 24. The instruction decoding unit 23 acquires an operation code portion and an operand portion necessary for instruction decoding and then executes instruction decoding. When the decoding of one instruction is completed, the instruction decoding unit 23 sends the instruction decoding byte number information to the sequence control unit 24 to prompt the prefetch of the next instruction data.

It should be noted that, after predicting whether or not the branch condition in the conditional branch instruction is satisfied, the queue 2 is determined based on the prediction.
In some cases, a branch prediction method for advancing the prefetch of the instruction data to 2 is adopted. However, for example, if the branch condition is actually met even though the branch condition is predicted not to be met and the prefetch is proceeded, all the instruction data already prefetched in the queue 22 becomes invalid. When the branch prediction is deviated in this way, prefetching must be performed until the queue 22 is filled with instruction data, as in the case of the above initial state in which all the instruction data temporary storage registers 22a of the queue 22 are empty. The queue data cannot be given to the instruction decoding unit 23.

[0009]

As described above, in the conventional instruction prefetch device, since the queue 22 is a data shift system in which the instruction data itself is shifted among a plurality of instruction data temporary storage registers 22a, the initial state and If the branch prediction is incorrect, the instruction decoding unit 2 must perform prefetching until the queue 22 is filled with instruction data.
3 cannot be given cue data. Therefore, a wait state corresponding to the shift time corresponding to the number of stages of the instruction data temporary storage register 22a occurs with respect to the instruction execution request, and the throughput of the system is lowered. Further, in order to configure the queue 22 by the data shift method, it is necessary to use a master-slave type flip-flop, which causes a problem that the circuit becomes large in scale.

Furthermore, a plurality of m-byte length instruction data temporary storage registers 22a having a basic instruction opcode width of the microcomputer are arranged in series, and the instruction data is stored between the instruction data temporary storage registers 22a by m.
Since the structure of the queue 22 that sequentially shifts in units of bytes is adopted, there is a problem that the writing and reading units of the queue 22 are limited to units of m bytes.
That is, the instruction word length is a multiple of m bytes (2 m bytes, 3
For an instruction with a number of bytes different from m bytes, ...)
A part of the instruction data temporary storage register 22a is wasted. In recent years, microcomputers, which have been highly functionalized and complicated, have diversified instruction word lengths. As described above, in the queue 22 in which the writing unit and the reading unit are both fixed to m bytes. It significantly reduces the throughput.

It is an object of the present invention to reduce the circuit scale while making it possible to cope with various instruction word lengths, and to improve the throughput by minimizing the waiting state for an instruction execution request.

[0012]

In order to solve the above-mentioned problems, the present invention, for a microcomputer having a standard instruction word length of n bytes, temporarily stores three or more instruction data each having an n-byte length. A queue memory in which a series of instruction data storage areas having a byte length three times or more of n bytes is formed by arranging registers in parallel with the program memory is used, and the instruction data storage areas are used. The writing of n bytes to the instruction data storage area and the cutting out of instruction data having an arbitrary word length of j bytes from an arbitrary address of the instruction data storage area are realized at the same time. Where j =
Any of n, j> n and j <n is allowed.

More specifically, according to the present invention , a standard instruction word having an instruction word length of n bytes is converted into a standard instruction word from a program memory storing a plurality of instruction data constituting a microcomputer program. An instruction prefetch device for sequentially prefetching in units of n bytes matching the length, and causing the instruction decoding unit to sequentially decode the prefetched arbitrary word length j bytes of instruction data. And a configuration including a queue management unit.

That is, the queue memory includes three or more instruction data temporary storage registers each having the same n-byte length as the standard instruction word length, and the three or more instruction data temporary storage registers are connected to each other. In addition, a series of instruction data storage areas having a byte length three times or more of n bytes capable of writing to and reading from an arbitrary address are formed in parallel with the program memory, and the instruction is stored. Arbitrary arbitrary j-byte instruction data is sequentially prefetched from the program memory in units of n bytes, which matches the standard instruction word length, into an empty area in the data storage area where valid and undecoded instruction data is not stored. A plurality of instruction data having a word length of j bytes are packed without a gap.

The selector cuts out the instruction data of arbitrary byte length j bytes prefetched into the queue memory from the specified address of the queue memory and reads it.
The read instruction data having an arbitrary word length of j bytes is sequentially transferred to the instruction decoding unit.

Further, the queue management unit executes prefetching of instruction data from the program memory to the queue memory when at least an n-byte length area corresponding to a prefetch unit of instruction data is secured as an empty area in the queue memory, Further, the selector reads the instruction data from the queue memory and transfers the instruction data by giving the starting address of valid and undecoded instruction data to be read next from the queue memory in parallel with the prefetch. And to execute.

Moreover, the present invention always writes the instruction data of the queue memory to an arbitrary address while always grasping the start address of the instruction data to be read next from the queue memory and the total number of bytes of the instruction data in the queue memory. In order to control reading from an arbitrary address, the structure of the queue management unit including the following queue memory pointer, effective byte number register, prefetch updating unit, instruction decoding updating unit, and prefetch control unit is adopted. is there.

That is, the queue memory pointer holds the start address of valid and undecoded instruction data to be read next from the queue memory as a queue memory read address, and gives the queue memory read address to the queue memory to select the selector. To read the instruction data from the queue memory and transfer the instruction data.

The valid byte number register holds the total number of valid and undecoded instruction data bytes in the queue memory as the valid byte number.

Furthermore, the prefetch-time updating means sets the number of valid bytes by the number of bytes n of the prefetched instruction data every time the prefetching in units of n bytes matching the standard instruction word length of the instruction data to the queue memory is completed. The number of valid bytes register is updated so as to increase.

Further, the instruction decoding time updating means is provided with the byte number j of the decoded instruction data from the instruction decoding section each time the instruction decoding section completes decoding of the instruction data of arbitrary word length j bytes, and the decoding is performed. Each time the number of bytes j of the command data that has been decoded is given, the number of bytes j of the decoded command data
The queue memory pointer is updated so as to advance the read address of the queue memory, and the valid byte number register is updated so as to reduce the valid byte number by the byte number j of the decoded instruction data.

Finally, the prefetch control unit calculates the start address of the free area in the queue memory and the number of bytes of the free area from the queue memory read address and the number of effective bytes, and at least the prefetch unit of the instruction data as the free area. When an area of n-byte length corresponding to is secured, the start address of the instruction data to be prefetched next to the program memory is specified and a queue memory write address for the instruction data to be prefetched next is queued. By designating the start address of the free area for the memory, prefetch of instruction data from the program memory to the queue memory is executed.

[0023]

According to the present invention , a plurality of n-byte (constant) instruction data temporary storage registers having the same length as the standard instruction word length are connected in parallel to the program memory to form n-byte 3 bytes.
A series of instruction data storage areas having a length more than twice the byte length are formed in the queue memory. The command data storage area is
When writing to an arbitrary address and reading from an arbitrary address is possible, and when an empty area of at least n bytes is secured in any position, an arbitrary word length of j bytes is written from the program memory to the empty area. Instruction data is sequentially prefetched in units of n bytes. At this time, a plurality of instruction data having an arbitrary word length of j bytes are packed into the instruction data storage area without a gap.

On the other hand, the queue management unit always manages the start address of the valid and undecoded instruction data to be read next from the queue memory, and in parallel with the prefetch of the instruction data from the program memory to the queue memory. The selector cuts out the instruction data of arbitrary word length j bytes in the queue memory from the address designated by the queue management unit and reads it, and sequentially transfers the instruction data to the instruction decoding unit. That is, when an empty area of n bytes required for prefetch can be secured in the queue memory, the prefetch of instruction data from the program memory to the queue memory is immediately executed, and the prefetched instruction data is stored in the queue memory. That is, it is immediately read by the selector and transferred to the instruction decoding unit without waiting to be satisfied.

Further, according to the present invention , the start address of the valid and undecoded instruction data to be read next from the queue memory is held in the queue memory pointer as the queue memory read address, and the valid and undecoded data in the queue memory is stored. The total number of bytes of the instruction data for decoding is held in the valid byte number register as the valid byte number. The content of the queue memory pointer is advanced by j bytes by the instruction decoding update means each time transfer of instruction data of arbitrary word length j bytes from the queue memory to the instruction decoding unit by the selector and decoding of the instruction data are completed. So its validity is always ensured. Further, the content of the valid byte number register is incremented by n bytes by the prefetch updating means each time the n-byte unit prefetch of the instruction data from the program memory to the queue memory is completed. Every time the transfer of the instruction data having an arbitrary word length of j bytes to and the decoding of the instruction data are completed, the updating means at the time of decoding the instruction decrements it by j bytes, so that its validity is always secured.

The prefetch control unit, based on the contents of the queue memory pointer and the effective byte number register, that is, the correct queue memory read address and the effective byte number, starts the free space start address in the queue memory and the free space. Calculate the number of bytes and. Then, the number of bytes of the empty area is checked, and when an area of at least n bytes that matches the prefetch unit of the instruction data is secured as the empty area, the instruction data to be prefetched next to the program memory The start address is specified, and the start address of the empty area calculated for the queue memory is specified as the queue memory write address for the instruction data to be prefetched next. As a result, prefetching of instruction data from the program memory to the empty area of the queue memory is accurately executed. On the other hand, the queue memory pointer gives a queue memory read address to the queue memory so that the selector can accurately read the instruction data from the queue memory.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an instruction prefetch device according to an embodiment of the present invention.

The instruction prefetch device shown in the figure sequentially prefetches instruction data of arbitrary word length j bytes from the ROM 1 in which a plurality of instruction data of a microcomputer having a standard instruction word length n bytes is stored in units of n bytes, In addition, the prefetched instruction data of arbitrary word length j bytes is sequentially decoded by the instruction decoding unit 4, and includes a queue memory 2, a selector 3 and a queue management unit 5. Here, the byte length j of the instruction data is arbitrary and variable,
Any of j = n, j> n, and j <n is allowed.

The queue memory 2 has k (k is an integer of 3 or more ) instruction data temporary storage registers 2 a arranged in parallel with the ROM 1. Each instruction data temporary storage register 2a has a length of n bytes, and is connected to each other to form a series of instruction data storage areas having a length of k × n bytes. The instruction data storage area of the queue memory 2 temporarily stores instruction data of an arbitrary word length j bytes prefetched from the ROM 1 in units of n bytes, and can be written to and read from an arbitrary address. Is.

The selector 3 reads the instruction data of arbitrary word length j bytes prefetched in the queue memory 2 from the specified address of the queue memory 2, and the read instruction data of arbitrary word length j bytes is stored in the queue memory 2. The data is sequentially transferred to the instruction decoding unit 4.

The queue management unit 5 keeps track of the start address of the instruction data to be read next from the queue memory 2 and the total number of bytes of the instruction data in the queue memory 2, and n bytes from the ROM 1 to the queue memory 2 In addition to controlling the prefetch of the unit instruction data, the selector 3 controls the batch reading of the instruction data of the j-byte length from the queue memory 2 and the transfer of the instruction data to the instruction decoding unit 4. For this purpose, the queue management unit 5 receives the prefetch end signal from the queue memory 2, receives the instruction decode byte number information together with the instruction decode end signal from the instruction decode unit 4, and sends it to the ROM 1 for prefetching the instruction data. And a queue memory write address to the queue memory 2, and a queue memory read address to the queue memory 2 for reading instruction data from the queue memory 2.

FIG. 2 is a block diagram showing a detailed configuration of the queue management unit 5. As shown in the figure, the queue management unit 5
Is a valid byte number register 11, an adder 12, and a subtractor 1
3, a queue memory pointer 14 and a prefetch control unit 15.

The valid byte number register 11 always holds the total number of valid and undecoded instruction data in the queue memory 2 as the valid byte number, and the queue memory pointer 14 should be read next from the queue memory 2. The head address of valid and undecoded instruction data is always held as a queue memory read address and the queue memory read address is output to the queue memory 2.

The adder 12 is effective for the number of bytes n (constant value) of the prefetched instruction data every time the prefetch end signal is given at the end of the prefetch of the instruction data to the queue memory 2 in units of n bytes. The effective byte number register 11 is updated so as to increase the number of bytes. Each time the instruction decoding unit 4 finishes decoding the instruction data having an arbitrary word length of j bytes, the subtracter 13 outputs information on the byte number j (variable value) of the decoded instruction data, that is, the instruction decoding byte number information. It is given from the instruction decoding unit 4 together with the instruction decoding end signal, and each time, the queue memory pointer 14 is updated so that the queue memory read address is advanced by the byte number j of the decoded instruction data, and the same number of bytes j is updated. The number of valid bytes register 11 is updated so as to reduce the number of valid bytes.

The prefetch control unit 15 determines the number of valid bytes held by the valid byte number register 11 and the queue memory read address held by the queue memory pointer 14 in order to prefetch instruction data from the ROM 1 to the queue memory 2. The start address of the empty area in the queue memory 2 and the number of bytes of the empty area are calculated based on the above, and when the area of at least n bytes that matches at least the prefetch unit of instruction data is secured as the empty area, the ROM 1 , The start address of the instruction data to be prefetched next is specified as the ROM address, and the start address of the empty area is specified to the queue memory 2 as the queue memory write address for the instruction data to be prefetched next. It is a thing.

Next, the operation of the instruction prefetch device according to the present embodiment described above will be described. (A) When the instruction data is n bytes (b) When the instruction data is smaller than n bytes (c) When the instruction data is It will be described with reference to FIGS. 3 to 5 showing the change of the prefetch position of the instruction data in the queue memory 2 and the state of updating the queue memory pointer 14 in each of the three cases of larger than n bytes. . However, in FIG. 3 to FIG. 5, the non-hatched blank portion indicates a free area of the queue memory 2, and the hatched portion indicates a valid area of the queue memory 2 in which valid and undecoded instruction data is stored.

(A) When the instruction data is n bytes In FIGS. 3A1 to 3A5, the word length j (byte) of the instruction data to be prefetched is the standard instruction word length n (byte).
It is a figure in the case of matching with. First, as shown in (a1), in the initial state, all the instruction data temporary storage registers of the queue memory 2 are empty areas, and the content of the valid byte number register 11 is cleared to zero. In this way, when an area of n bytes or more is secured as a free area of the queue memory 2, prefetch from the ROM 1 to the queue memory 2 is executed by using the free cycle. However, in the initial state, the leftmost instruction data temporary storage register is the first prefetch position as shown in (a1).

When n-byte length instruction data is actually pre-fetched to this pre-fetch position as shown in (a2), the contents of the queue memory pointer 14 are set so as to specify the start address of the pre-fetched instruction data. At the same time, the adder 12 increases the content of the valid byte number register 11 by n. As a result, the prefetch position is updated as shown in (a2),
The n-byte length instruction data to be prefetched next is packed without any gap with respect to the previously prefetched n-byte length instruction data. The instruction data in the queue memory 2 is read out for decoding in parallel with the prefetching of the instruction data into the above empty area. However, when there are many empty cycles, the number of prefetches exceeds the number of reads. The queue memory 2 is filled with command data.

The instruction data prefetched in the queue memory 2 is read by the selector 3 from the queue memory read address designated by the queue memory pointer 14 and transferred to the instruction decoding unit 4 in parallel with the prefetch as described above. To be done. As shown in (a3), while all the instruction data temporary storage registers of the queue memory 2 are filled with the instruction data, the instruction data stored in the leftmost instruction data temporary storage register is read, When the decoding of the instruction data is completed, the queue management unit 5 receives the instruction decoding byte number information (n bytes in this case) from the instruction decoding unit 4, and the subtracter 13 advances the queue memory pointer 14 by n bytes. At the same time, the content of the valid byte number register 11 is reduced by n. As a result,
As an empty area of the queue memory 2, an area having an n-byte length that matches the prefetch unit of instruction data is secured, and the next prefetch can be performed.

By the way, when the content of the queue memory pointer 14 reaches the head address of the rightmost instruction data temporary storage register as shown in (a4), the queue memory pointer 14 is ring-shaped at the end of decoding of the next instruction. To update. That is, as shown in (a5), when the rightmost instruction data temporary storage register is located at the next prefetch position at the end of instruction decoding, the queue memory pointer 14 is set to the head of the leftmost instruction data temporary storage register. Updated to specify the address.

(B) When the instruction data is smaller than n bytes In (b1) to (b5) of FIG. 4, the word length j (byte) of the instruction data to be prefetched is the standard instruction word length n (byte).
FIG. RO as in the case of FIG.
The instruction data is read out from the queue memory 2 in parallel with the prefetch of the instruction data from the M1 to the queue memory 2 in units of n bytes. However, the number of prefetches exceeds the number of reads when there are many empty cycles. Therefore, the queue memory 2 is filled with command data.
However, the instruction data of j (<n) byte length that is prefetched later is packed without a gap with respect to the instruction data of j (<n) byte length that was previously prefetched. As a result, as shown in (b1), all the instruction data temporary storage registers of the queue memory 2 are filled with the instruction data, and the queue memory pointer 14 specifies the head address of the leftmost instruction data temporary storage register. It is assumed that you have advanced to.

At this point, as shown in (b2), j (<is stored in the leftmost instruction data temporary storage register.
n) When the selector 3 cuts out instruction data having a byte length and the decoding of the instruction data is completed, the queue management unit 5 causes the instruction decoding unit 4 to read the instruction decoding byte number information (in this case, j bytes, j < When n) is received, the subtractor 13 advances the queue memory pointer 14 by j bytes in the same manner as described above and decreases the content of the valid byte number register 11 by j. However, unlike the case of the above (a), the byte number j of the decoded instruction data is smaller than n, so that the decoding of one instruction data is completed and the instruction data is regarded as an empty area of the queue memory 2. An n-byte length area that is a prefetch unit is not secured, and the next prefetch is not executed immediately. As shown in (b3),
Further, the prefetch in the next n-byte unit becomes possible only when the decoding of the next instruction data is completed.

When the content of the queue memory pointer 14 has reached the rightmost instruction data temporary storage register as shown in (b4), the queue memory pointer 14 is updated in a ring shape at the end of decoding of the next instruction. . That is,
As shown in (b5), when the rightmost instruction data temporary storage register becomes the next prefetch position at the end of instruction decoding, the queue memory pointer 14 sets the address in the leftmost instruction data temporary storage register. Only j bytes are updated as indicated.

(C) When the instruction data is larger than n bytes In (c1) to (c4) of FIG. 5, the word length j (byte) of the instruction data to be prefetched is the standard instruction word length n (byte).
FIG. Since there are many empty cycles as in the case of (b), as shown in (c1), all the instruction data temporary storage registers of the queue memory 2 are filled with instruction data, and the queue memory pointer 14 is leftmost instruction data. It is assumed that the process has proceeded to specify the start address of the temporary storage register. However, in this case as well
Prefetch of instruction data from 1 to the queue memory 2 is performed in units of n bytes, and prefetched later.
The instruction data of (> n) byte length is packed without any gap in the previously prefetched instruction data of j (> n) byte length.

At this time, as shown in (c2), an instruction of j (> n) bytes in length stored in the leftmost instruction data temporary storage register and the instruction data temporary storage register adjacent thereto. When the data is cut out by the selector 3 and the decoding of the instruction data is completed, the queue management unit 5 receives the instruction decoding byte number information (j bytes in this case, j> n) from the instruction decoding unit 4 and subtracts it. The queue memory pointer 14 is advanced by j bytes in the same manner as described above by the device 13, and the content of the valid byte number register 11 is decreased by j. In this case, since the number j of bytes of the decoded instruction data is larger than n, the area of n-byte length, which is the prefetch unit of the instruction data, becomes a free area of the queue memory 2 only when the decoding of one instruction data is completed. Is secured and the next prefetch can be executed immediately.

When the contents of the queue memory pointer 14 have reached the middle of the rightmost instruction data temporary storage register as shown in (c3), the queue memory pointer 14 is ringed at the end of decoding of the next instruction. Update to the state. At this time, as shown in (c4), the designated address of the queue memory pointer 14 jumps over the leftmost instruction data temporary storage register and reaches the instruction data temporary storage register adjacent to the leftmost instruction data temporary storage register. In the case of advancing, an empty area of 2 × n bytes can be secured at one time, and therefore, the prefetch is performed twice in units of n bytes using the empty cycle.

As described above, according to the present embodiment, unlike the conventional data shift method, writing to an arbitrary address and reading from an arbitrary address can be performed as the queue memory 2 by the plural instruction data temporary storage registers 2a. Since a series of instruction data storage areas are formed, the prefetched instruction data in the queue memory 2 is immediately read out by the selector 3 without waiting for the queue memory 2 to be filled with the instruction data, and is sent to the instruction decoding unit 4. Transferred.
Therefore, even if the initial state or the branch prediction is missed, the waiting state for the instruction execution request is minimized, and the throughput is improved. Moreover, a simple data latch circuit can be used for the configuration of the queue memory 2, and the circuit scale can be reduced.

Further, a plurality of instruction data temporary storage registers 2a are connected to form the queue memory 2 to form a series of instruction data storage areas in which instruction data of arbitrary word length j bytes can be written and read. At the same time, since a plurality of instruction data of arbitrary word length j bytes are packed in the series of instruction data storage areas without any gap, the queue memory can be used without waste, and various instruction word lengths can be flexibly supported. You can Moreover, since the size of each instruction data temporary storage register 2a and the prefetch unit of the instruction data are matched with the standard instruction word length n bytes of the microcomputer, the structure of the interface circuit between the ROM 1 and the queue memory 2 is formed. Is easy, and the circuit scale can be reduced also in this respect. Also,
It is convenient to handle a large number of standard instruction word length n byte instruction data, and the highest throughput can be realized for the instruction data of the word length.

Furthermore, a valid byte number register 11 and a queue memory pointer 14 which are accurately updated at the time of prefetching and instruction decoding are provided, and based on the valid byte number and the read address of the queue memory 2 managed by them. Since the prefetch of the instruction data to the queue memory 2 and the reading of the instruction data from the queue memory 2 are controlled, the word length of the instruction data is the standard instruction word length n.
Even if it is different from the byte, the instruction data can be correctly prefetched, and the prefetched instruction data can be accurately transferred to the instruction decoding unit 4.

[0050]

As described above, according to the present invention , unlike the conventional data shift method, a plurality of instruction data temporary storage registers are connected to each other to write to and read from an arbitrary address. Since a structure of a queue memory that forms a series of instruction data storage areas that can be used is adopted, instruction data can be specified by addressing from any position of the queue memory in parallel with prefetching of instruction data to an empty area of the queue memory. Can be read. That is, when a free area with a byte length necessary for prefetch can be secured in the queue memory, the prefetch of the instruction data to the queue memory is immediately executed, and the prefetched instruction data is filled in the queue memory with the instruction data. It is immediately read and transferred to the instruction decoding unit without waiting for. Therefore,
Even if the initial state or the branch prediction is missed, the waiting state for the instruction execution request is minimized, and the throughput is improved. Further, since the queue memory can be configured by using a simple data latch circuit instead of the master-slave flip-flop in the case of the conventional data shift method, the circuit scale can be reduced.

Further, a structure is provided which includes a queue memory in which a series of instruction data storage areas capable of writing and reading instruction data of arbitrary word length j bytes are formed by a plurality of instruction data temporary storage registers connected to each other. In addition, since a plurality of instruction data of arbitrary word length j bytes are packed in the series of instruction data storage areas without any space therebetween, the queue memory can be used without waste and is flexible for various instruction word lengths. Can respond.

Moreover, since the size of each of the plurality of instruction data temporary storage registers constituting the queue memory and the prefetch unit of instruction data are matched with the standard instruction word length n bytes of the microcomputer, the program memory and the queue are The configuration of the interface circuit with the memory is easy, and the circuit scale can be reduced also in this respect. In addition, it is convenient for handling instruction data having a standard instruction word length of n bytes, which is generally large, and the highest throughput can be realized for the instruction data having the word length.

Further , according to the present invention , a queue memory pointer and a valid byte number register which are accurately updated at the time of prefetching and instruction decoding are provided, and based on the read address and the valid byte number relating to the queue memory managed by both. Since the prefetch of the instruction data to the empty area of the queue memory and the reading of the instruction data from the queue memory are executed, the word length of the instruction data is different from the standard instruction word length n bytes. Also, it is possible to correctly prefetch the instruction data and accurately transfer the prefetched instruction data to the instruction decoding unit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an instruction prefetch device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a queue management unit in FIG.

FIG. 3 shows a change in the prefetch position of instruction data in the queue memory in FIG. 1 and a state of updating the queue memory pointer when the word length of instruction data to be prefetched matches the standard instruction word length n (bytes). It is the conceptual diagram shown.

FIG. 4 is a diagram similar to FIG. 3 in the case where the word length of instruction data to be prefetched is smaller than the standard instruction word length n (byte).

FIG. 5 is a diagram similar to FIG. 3 in the case where the word length of instruction data to be prefetched is larger than the standard instruction word length n (byte).

FIG. 6 is a block diagram showing a configuration of a conventional instruction prefetch device.

7 is a conceptual diagram showing a detailed configuration of a queue in FIG. 6 and a flow of instruction data through the queue.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... ROM (program memory) 2 ... Queue memory 2a ... Register for temporary storage of instruction data 3 ... Selector 4 ... Instruction decoding unit 5 ... Queue management unit 11 ... Effective byte number register 12 ... Adder (update unit at prefetch) 13 ... Subtractor (update means during instruction decoding) 14 ... Queue memory pointer 15 ... Prefetch control unit

Claims (1)

(57) [Claims] 1. A program memory in which a plurality of instruction data that constitutes a microcomputer program having a standard instruction word length of n bytes is stored.
Any of n, j> n and j <n is allowed. ) An instruction prefetch device for sequentially prefetching byte instruction data in units of n bytes that match the standard instruction word length, and sequentially decoding the prefetched arbitrary word length j bytes of instruction data by an instruction decoding unit. , Three or more instruction data temporary storage registers each having the same n-byte length as the standard instruction word length, the three or more instruction data temporary storage registers being connected to each other and the program memory Are arranged in parallel with respect to each other, and a series of instruction data storage areas having a byte length three times or more of n bytes capable of writing to and reading from an arbitrary address are configured. Of the instruction data of arbitrary word length j bytes from the program memory to the empty area where valid and undecoded instruction data is not stored A queue memory that is sequentially prefetched in units of n bytes that matches the word length, and a plurality of instruction data of arbitrary word length j bytes are packed without gaps between them, and instruction data of arbitrary word length j bytes prefetched in the queue memory Is cut out from a specified address of the queue memory and is read out, and a selector for sequentially transferring the read instruction data of arbitrary word length j bytes to the instruction decoding unit; When an n-byte length area matching the prefetch unit is secured, prefetch of instruction data from the program memory to the queue memory is executed, and in parallel with the prefetch, it is valid and should be read next from the queue memory. Give the start address of undecoded instruction data to the queue memory In this way, a queue management unit for executing the reading of instruction data from the queue memory by the selector and the transfer of the instruction data is provided.
The queue management unit is provided with a valid and unread function to be read next from the queue memory.
Read the start address of decoding instruction data in the queue memory
Stored as an address and read the queue memory
To the queue memory by giving a reply to the queue memory.
And reading the instruction data from the queue memory
Queue memory for executing the transfer of the instruction data
The pointer and the valid and undecoded instruction data bar in the queue memory.
Bytes to keep the total number of bytes as valid bytes.
Number register and the standard instruction word length of instruction data to the queue memory
Each time n-byte unit prefetch is completed,
Valid bytes for the number n of bytes of refetched instruction data
Update the number of valid bytes register to increase
Updating means for prefetching and instruction data of arbitrary byte length j bytes by the instruction decoding unit
Number of bytes of the decoded instruction data each time decoding is completed
j is given from the instruction decoding unit, and the decoded instruction data
Each time the number of data bytes j is given, the decoded instruction data
The queue memory read address for byte number j of data
Update the queue memory pointer to proceed, and
The number of valid bytes corresponding to the byte number j of the decoded instruction data
Update the valid bytes register to reduce
For decoding the instruction for decoding, the queue memory read address and the number of valid bytes
And the start address of the empty area in the queue memory
Calculate the number of bytes in the free area and reduce the free area.
If there is no n-number that matches the prefetch unit of instruction data
When the program length area is secured, the program memo
Ahead of the instruction data that should be prefetched next
Life to specify head address and next prefetch
As a queue memory write address for command data
The start address of the empty area is set to the queue memory
By specifying, the program memory
-For prefetching instruction data to memory
And a prefetch control unit for the instruction prefetch device.