JPS6072030A - Information processing device - Google Patents

Abstract

PURPOSE:To improve the performance of a branch instruction, etc. by detecting a fact that an instruction address exceeds a page boundary on the way of fetching in instruction if it occurs, and inhibiting storage of the subsequent data. CONSTITUTION:Data from a storage control device SUC is set to instruction buffer registers (hereinafter called IBR) 1-4 of 4-byte length each by the SUC and a WTIBR signal of 4 bytes. Also, an instruction buffer pointer (hereinafter called IBP) 5 indicates from which IBR an instruction to be executed in the next time is fetched. When a instruction address is in a 2-byte boundary and instruction length is above 2 bytes, the IBP5 indicates the head of the next instruction by 2-byte unit and is set to an instruction register IR6, the instruction length is added to the IBR by a 2-byte unit and updated so as to indicate the head of the next instruction. In this way, 16 bytes from an optional 4-byte boundary address can be fetched, and detched data can be stored in order from the IBR used most frequently in the past.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an information processing device, and particularly relates to a plurality of instruction buffer registers and a method for storing fetched data in the plurality of instruction buffer registers by fetching an instruction once. The present invention relates to an information processing device that has functions that can perform the following functions.

[Prior art]

Since it takes a lot of time to read instructions from the main memory, instructions are preliminarily stored in a buffer memory in a processing device. Here, there are four 4-byte instruction buffer registers (hereinafter referred to as IBRs) connected to the main memory device by 4-byte data lines (these are called IBRo, IBRl, and I structure).

IBR5) and 16-byte instruction fetch function (
Using an information processing device as an example, which has the function of reading 16 bytes from the main memory at once from the 16-byte boundary of the address,
The conventional method will be explained.

Conventionally, in the above-mentioned information processing device, instruction fetch is performed by
It fetched 16 bytes from a 16-byte boundary address and stored the data from IBRO to IBR5.

However, in such a system, if the branch destination address of a successful branch instruction is not on a 16-byte boundary, the instruction fetch is performed from the 16-byte boundary, so only the valid 16-byte instruction fetch data is used. less data. For example, 1 branch destination address is 16yb+12
When starting from a byte boundary, only 4 bytes of 16 bytes of fetch data are valid data.

Furthermore, in addition to branch instructions, in an instruction that cancels the contents of IBH, valid fetch data may be 12 bytes or less when fetching the next instruction, as in the case of a branch instruction.

Here, assuming that an instruction exists at an arbitrary 2-byte boundary address on memory with equal probability, the instruction fetch that occurs with the next instruction of a successful branch instruction or an instruction that cancels the instruction buffer register, The average effective data length is 'i, 1-6 soil 1 raw soil L traverse canter traverse belly traverse bhihishishi - = 9 (bytes). If the instruction in which the instruction fetch occurs is, for example, a 4-byte long instruction with a 16r++12-byte boundary address, the instruction cannot be decoded because valid information is not launched into the IBH until the fourth data transfer is completed. This is shown in the time chart of FIG. In FIG. 1, MDATA is instruction fetch data sent from the main memory, and is sent in cycles φ1 to φ4, taking 4 machine cycles for each 4 byte. At the fourth machine cycle φ4 in Figure 1, IBI
Fetch the target instruction to B, 5th machine cycle φ5
You can decode instructions without any serious effort.

Furthermore, if the instruction is a 4-byte long instruction with a 1, 16n + 12 hide boundary address, 6 byte length instruction 2, R++z + 14 pie) f2 boundary address, and a 6 byte, byte length instruction 5.16yb + 14 byte boundary address, the instruction is fetched again. must be carried out.

Normally, the frequency of branch instructions in a program is about 20%, and the above-mentioned overhead greatly affects the performance of the information processing device.

For large machines, there is a technique of having two IBRs, one for current use and one for branch, to prevent a decrease in processing speed, but for small machines, such an increase in hardware is difficult to tolerate.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an instruction fetch method that can improve the performance of branch instructions and instructions that cancel instruction buffer registers.

[Summary of the invention]

The present invention performs an N-byte instruction fetch from an arbitrary N-byte boundary address, and fetches an IB whose data was used most recently among m instruction buffer registers (where m≧t).
Fetch data is stored in order from R. In addition, in the case of an information processing device that performs address translation and memory protection on a page-by-page basis in the storage area, if an instruction address or page boundary is crossed during an instruction fetch, this is detected and the subsequent data is not stored in the IBH. It is a fetch method.

[Embodiments of the invention]

In the present invention, it is assumed that the main memory device consists of four banks, each of which is read by 4 bytes. Since such a so-called multi-puncture storage device is well known, it will not be described in detail. From such a storage device, 16 consecutive heights can be read from any 4-byte boundary.

Conventionally, information other than instructions was read in this way, but in the case of instructions, it is difficult to store them in the IBR and control their reading when those 16 bytes span a page boundary, so it is only read from 16-byte boundaries. was not carried out.

In the present invention, even in instructions, 16
Bytes are read, 4 bytes are successively transmitted to the information processing device, and stored in the IBR.

The present invention provides a pointer for storage in an IBR, and a pointer for storage in an IBR.
A pointer is provided for reading instructions from the program, and control is performed to enable the above-mentioned reading method, thereby eliminating delays in execution such as when branching.

An embodiment of the control circuit according to the present invention will be described below with reference to the drawings.

Figure 2 is a block diagram of the data system centered on IBR.
FIG. 3 is a block diagram of the control system, and FIG. 4 is a time chart. In the figure, 1 to 4 are instruction buffer registers IBRO to 6 each having a length of 4 bytes, and each inputs a storage control device (referred to as SCV) and a 4 byte data line.
"Set the data from the SCU to the IBRo~6 signal. IBpO~2 of 5 is a pointer that indicates where in IBRo~6 the instruction to be executed first is retrieved from, and 6 is 4 bytes. This is a long instruction register, IR.Assuming that the instruction address is 2 pi! boundary and the instruction length is 2 bar fl. or more, IBPO ~ 2 indicates the beginning of the next instruction in 2 byte units. 2-'1' (
(hexadecimal display), the latter two bytes of IBRO and IBRl
The first 2 bytes of
The last two bytes of BR5 and the first two bytes of IBRO are set in Otsu's JR. When an instruction is set in IR6, the instruction length is added to JBRD~2 in units of 2 bytes and updated to point to the beginning of the next instruction.

7 in FIG. 6 is a counter that is counted up by the data set instruction signal (ENI) sent from the SCU in conjunction with the transfer of 4-byte data, and as shown in FIG. '→'2'→'3'→'4→'0. The 3-bit output signal is CNTAO~2. 8 is the same (counter CNTB is incremented by END), but CNTA of 7 is reset to O when END runs out, whereas 8 is not reset and holds the last value, and IBRo~3 The -f6 bit pointer indicates how far the instruction has been stored in the previous instruction 7 etching, and the output signal CNTBo~2 is set.CNTBF3 is the initial value of ``4'' when END is sent 4 times. Then, as shown in Fig. 4, r4r→'1'→'
The signal RIBR changes from 2' to 3' to 4', and when the signal RIBR sent from the instruction execution unit to reset IBR is issued by a branch instruction, etc., it is reset to 0, and then,
When ENI) is sent four times by instruction fetch, the sequence changes as IO'→'1'→'2'→'5'→'4'.

IPEND of 9 is a flip-flop that latches CNTAo (the most significant pin of the output of CNTA of 7'), and is set when the fourth transfer occurs.07? IFl of the latch through gate 10 to indicate that an instruction is being fetched.
Reset l. 11 IF is an instruction fetch start signal 5TR generated when the IBR becomes empty.
It is set by TIF and reset by IFEND9. That is, the output of IFll becomes @Is i l/ when the command fetch is performed, and is a signal that enables the decoder 14. 12 CNTBld.

cJvrB2Dra, CNTBl-2f, Tsuba jl'l''1BRD-5 is 1 to 4 IBRO to 5 respectively
This is the seven T-signal. If the initial value of CNTH is '4', as shown in Fig. 4, IHR5i in order from IBRIJ,
Data from the ECU is set during cycles φl-φ4.

In this method, which fetches 16 bytes of data with one instruction fetch and water hold, if address conversion or storage checking is necessary, it is performed only on the page containing the first address.

However, when performing a 16-height fetch from an arbitrary 4-byte boundary, a page boundary may be crossed in the middle of 16 bytes. In such a case, address translation and memory protection checks must be performed again for the new page.

Therefore, if a page boundary is crossed during an instruction fetch,
The SCU generates the pAGEEND signal to reset the IFll, and also suppresses subsequent END signals.

FIG. 5 shows a time chart in the case of an instruction fetch whose address is the beginning of the last 4 bytes of a page. The first END is sent, then in the cycle where the second END would normally be sent, pAGE-END is sent and END is sent.
will not be sent after this cycle. The initial value of CRTH is
4', data is stored only in IBRO and CN
TB is counted up only once and becomes '1', indicating that valid data exists only in IBRO. When an instruction fetch occurs after executing an instruction stored in IBRo,
Since the initial value of CRTH is '1', as shown in the latter half of Figure 5, IBH2, IBH3,
IBRO and data are stored, and CNTB also changes from '1' to '2
It changes as '→1'5'→・4'→'1'.

By controlling in this way, the data is stored in the IBR in the order starting from the IBR that was used in the past.

As described above, by performing an instruction fetch from an arbitrary 4-byte boundary, it is possible that a page boundary exists in one fetch, and that an instruction larger than the size of the instruction register is handled. For this reason, instructions are stored in ll3R from immediately after the previously fetched location, that is, from the location containing the oldest information, and if a page boundary is detected, subsequent storage is prohibited. .

After that, reading is performed again.

As described above, in this embodiment, it is possible to perform a 16-byte 7 fetch from an arbitrary 4-byte boundary address, and the fetch data can be stored in order from the IBR used most recently.

As a result, while the average effective data length was 9 bytes in the 16-byte offset method from the 16-byte boundary, in this method D=μ5±15 (bytes).

Furthermore, if the instruction length is 2 bytes, it is the first END, if it is 4 bytes, it is the first or second time, and if it is 6 bytes, it is the second END, regardless of the instruction address. instructions can be stored in the IBR,
The decoding operation can be performed with φ2 or φ3.

According to the present invention, it is possible to fetch an N-byte instruction from an arbitrary N-byte boundary address, and store the fetched data in order from JBd that used the data in the past. Cancel 1
- The effect of improving the performance of the instructions is reduced.

[Brief explanation of drawings]

Figure 1 is a time chart showing the conventional IBR set and decoding operation, Figure 2 is a block diagram of data systems such as IBH, Figure 6 is a block diagram of Commiror system, and Figure 4 is a block diagram of P
Time chart when AGEEND does not occur, 5th
The figure is a time chart when PAGEEND occurs. 1 to 4...Instruction buffer register IBRO to 6
．． 5...Instruction buffer pointer IBPO~2.
6...Instruction register IR, 7...Counter A1B...Counter B. 9...Flip-flop IFEND. 10...OR gate, 11...Flip-flop IF. 12---=-C? NTB1~2 (7) Te4 L
'IRAN f CNTBID, 2D. 13...AND gate, 14...decoder. Representative Patent Attorney Akira Takahashi Fugyu 1 Figure Sheep 311B Horned Sheep 4 Figure Evening

Claims (1)

[Claims] A buffer register stores M (M≧2) instructions of N bytes each, and the oldest instruction is stored in the buffer register, which is an instruction that has been successively transferred t (tvt) times by N bytes from the main memory. and means for storing subsequent instructions in the buffer register when there is a page boundary of a main memory address in the continuously transferred instructions. Information processing equipment.