JPS59189448A - Operand buffer - Google Patents

Abstract

PURPOSE:To execute efficiently instructions using memory read data by providing a storage pointer, the first and the second read pointers, a pointer updating means, and an aligner in an operand buffer body. CONSTITUTION:An operand buffer body 1 is provided with 8 entries, and they are connected to a storage pointer 2 and the first and the second read pointers 3 and 4. Contents of the storage pointer 2 are counted up by +1 by an adder 7 each time when memory read data is received from a main storage device. Contents of the read pointer 3 are updated each time when data of the operand buffer body 1 is used and each time when outputs of adders 8 and 9 are selected by a selector 11. The difference between pointers 4 and 3 is added to contents of the pointer 4 in an adder 10 by a register 12 to update contents of the pointer 4 simultaneously with update of the pointer 3. Read output signals 5 and 6 from the body 1 are sent to an operating device through an aligner 13. Thus, data prefetch is unnecessary, and entries are indicated by plural pointers to supply instructions efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the connection of an operand buffer for storing memory read data as arithmetic input operands to an arithmetic unit.

(Prior art) Conventionally, when the arithmetic unit of a computer is not configured with a pipeline, operanton etch is rarely the limit in terms of arithmetic performance. In normal cases, an operand buffer for storing 7nds is not provided.

In this case, if the arithmetic unit is configured with a pipeline, operands are correspondingly supplied to the arithmetic unit, so that operands and instructions are usually prefetched together with a prefetching device. However, if the look-ahead unit and the arithmetic unit operate in perfect synchronization with the wake-up to the arithmetic unit and the operand fetch, there is no need to use an operand buffer.

However, when executing variable length instructions, the execution time changes depending on the operand length, so it is often difficult to completely synchronize the prefetch unit and the arithmetic unit. Therefore, if the prefetch device and the arithmetic device are operated asynchronously,
A buffer is required for passing between the two,
The existence of an operand buffer to store operands is required.

As explained above, it is sufficient for the conventional operand buffer to have the function of sequentially taking out operands stored in a first-in, first-out format as operation input data.

Looking at the types of operands supplied from the standpoint of the instruction format, it is RR type.

There are RX type, RS type, SS type, and other types. Except for the RR type, there is a drawback in that it is not necessarily efficient to execute all instructions that use memory operands as input operands according to the function of the operand buffer.

(Object of the Invention) An object of the present invention is to provide an operand buffer body having a plurality of entries in order to asynchronously deliver instructions to an arithmetic unit without using first-in or first-input. , and by providing a plurality of pointers for pointing to a plurality of entries, and by providing a means for updating the contents of these pointers by a preset value, the above drawback is eliminated, and the memory can be used as an operation input operand. An object of the present invention is to provide an operand buffer that efficiently executes instructions using read data.

(Structure of the Invention) The operand buffer according to the present invention includes an operand buffer body, a storage pointer, first and second read pointers, and pointer updating means.

It is configured to include an aligner.

The operand buffer body has a plurality of entries for storing memory read data used as operation input operands to the arithmetic unit.

The storage pointer is used to indicate a write entry to the operand buffer body.

The first read pointer is used to indicate a read entry to the operand buffer body, and the second read pointer is used to indicate a value obtained by adding a certain value to the contents of the first read pointer. It is.

The pointer update means is for updating the contents of the storage pointer and the first and second read pointers by a preset value, and consists of a plurality of comparators, a selector, and a difference register. It is something.

The aligner is the first and second aligner from the operand buffer body.
This is a device that rearranges and aligns the upper byte and lower byte of instructions that have been updated and read out sequentially by the pointer update means according to the instructions of the read pointer to a specified boundary or to the left. Embodiment Next, a block configuration of an embodiment of an operand buffer according to the present invention is shown in FIG. In FIG. 1, the operand buffer includes an operand buffer body 1, a storage pointer 2, first and second read pointers 3 and 4, first to fourth adders 7 to 10, and a 1 selector 11. and the difference register 12.

This configuration includes an aligner 13.

In the above description, the first and second adders 7°8tr
The third adder 9 is for adding 2, and the fourth adder 10 is a difference adder.

Next, the present invention will be explained in detail according to FIG. In this embodiment, memory read data t/'i from the main memory is 8-byte wide data starting from an 8-byte boundary. Therefore, if the memory operands are not placed on defined boundaries, it becomes necessary to align the data.

In FIG. 1, an operand buffer body 1 has eight entries and is connected to a storage pointer 2 and first and second read pointers 3, 4. Outputs indicating the read positions are obtained from the first and second read pointers 3 and 4, respectively.

Each time the storage pointer 2 receives memory read data from the main storage device as a reply, the first adder 7 adds the contents by 1. Each time the memory read data stored in the operand buffer main body 1 is used, the first read pointer 3 is sent to the second adder 8,
Alternatively, one of the outputs of the third adder 9 is output to the selector 11.
The contents are updated each time it is selected.

Note that in the selector 11, the first read pointer 3
It is also possible to select the original value before updating. Second
The timing at which the contents of the read pointer 4 are updated is the same as the timing at which the contents of the first read pointer 3 are updated. The contents of the second read pointer 4 are updated from the output of the fourth adder 10, which generates a difference with the contents of the first read pointer 3. Contents of the difference register 12 (This is a register for setting the difference between the low temperature 1 and second read pointers 3 and 4, and can be set in response to an instruction.The difference register 12 usually contains
1 is set, and the contents of the second read pointer 4 are greater than the contents of the first read pointer 3 by one. Read output signal line 5 from operand buffer main body 1,
6 is rearranged through an aligner to a predetermined boundary or to the left, and then sent to the arithmetic unit. The arithmetic unit is 8 bytes wide. Here, the aligner and the arithmetic unit are of the prior art.

FIG. 2 is a diagram showing read data set in the operand buffer main body 1 shown in FIG. 1, and in FIG. 2, memory read data A.

Assume that B and C are set in operand buffer body 1 and that the following pair of floating point instructions are executed sequentially.

That is, (1) double precision 1 multiplication (RX type, non-defined bounds) (2
) Double precision, additive (RX type, defined bounds).

Since l is normally set in the difference register 12, the first read pointer 3 points to entry 01 and the second read pointer 4 points to entry 1. therefore,
aA is output to the output signal line 5 from the operand buffer main body 1, and triB is output to the output signal line 6.

Since the memory operand in a double-precision multiplication instruction is on an undefined boundary, both memory read data A and Bfl are sent to the arithmetic unit via the aligner, and the contents of the first read pointer 3 are transferred to the third adder 9. is incremented by 2 and updated. Therefore, the contents of the first read pointer 3 point to entry 2, and the contents of the second read pointer 4 point to entry 3. Since the memory operand in the double-precision add instruction is on the specified boundary, the contents of the first read pointer 3 are updated by incrementing by 1 using only the memory read data C, and the contents of the first read pointer 3 are The contents of the second read pointer 4 point to entry 4.

FIG. 3 is a diagram showing read data set in the operand buffer main body 1 shown in FIG. 1. In FIG. 3, memory read data AO to A2. - Assume that BO-B2 is set to operand buffer body 1 and that a variable-length logical comparison instruction (SS type, assuming the operand length is 15 bytes and does not start on an 8-byte boundary) is executed. do.

First, it is assumed that the look-ahead device alternately fetches the first and second operands and that the memory read data is set in the operand buffer body 1 according to the form shown in FIG. Therefore, when the content of the difference register 12 is reset from 1 to 2 and the original value is selected for the first read pointer 3 by the selection device 11 and an update instruction is sent, the content of the first read pointer 3 is The contents of the second read pointer 4 point to entry 5. Therefore, operand 1 and operand 2 are both left justified and sent to the arithmetic unit.

Send 8 bytes of data as operand 1 from Ao and A1 to the arithmetic unit, increment the contents of the first and second read pointers 3 and 4 by 1, and then send 8 bytes of data as operand 2 from BO and B1. Send data to a computing device. Next, after incrementing the contents of the first and second read pointers 3 and 4 by 1, operand 1 is extracted from A1 and A2.
After sending 7 bytes to the arithmetic unit and incrementing the contents of the first and second read pointers 3 and 4 by 1, B1
and B2 to the arithmetic unit as operand 2, the contents of the first and second read pointers 3 and 4 are incremented by 1 again, and the logical comparison instruction is executed. Finally, the contents of the first read pointer 3 point to entry 7, and the contents of the second read pointer 4 point to entry 1.

Here, the pointer HMOD8 is used to circulate. Reset the contents of the difference register 12 from 2 to 1,
When the selection device 11 selects the output of the third comparator 9 to update the contents of the pointer, the contents of the first read pointer 3 point to entry 1, and the contents of the second read pointer 4 point to entry 2. Instruct. Thereafter, post-processing for subsequent instructions is performed and the operation ends.

(Effects of the Invention) As explained above, the present invention provides an operand buffer having a plurality of entries in order to asynchronously deliver instructions to an arithmetic unit without preloading or prefetching the operand buffer main body. a main body, and a plurality of pointers for pointing to a plurality of entries;
By providing means for updating the contents of these pointers by a predetermined value and configuring the upper byte and lower byte of the instruction read from the operand buffer body in the above manner, the instruction This has the effect that it can be efficiently supplied to the arithmetic device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of an operand buffer according to the present invention. 2 and 3 are diagrams showing the correspondence between entry numbers in the operand buffer shown in FIG. 1 and memory read data during instruction execution, respectively. 111--Operand buffer body 2-4...Pointer 5.6...Signal lines 7-10...Adder 11...Selector 12φ...Difference register 13-a@aligner patent applicant NEC Agent Co., Ltd. Patent attorney Inoro Jusai 2 figures 3 figures 267-

Claims (1)

[Claims] an operand buffer body having a plurality of entries for storing memory read data used as an operation input overside to an arithmetic unit; a storage pointer for instructing a write entry to the operand buffer body; a first read pointer for indicating a read entry for the operand buffer body; a second read pointer for indicating a value obtained by adding a certain value to the contents of the first read pointer; pointer updating means comprising a plurality of comparators, selectors, and difference registers for updating the contents of the storage pointer and the first and second read pointers by a preset value; and from the operand buffer body. defining a boundary between the upper byte and lower byte of the instruction that has been updated and read by the pointer updating means in accordance with the instructions of the first and second read pointers;
or an aligner for rearranging and aligning to the left.