JPH0436455B2 - - Google Patents
Info
- Publication number
- JPH0436455B2 JPH0436455B2 JP22067183A JP22067183A JPH0436455B2 JP H0436455 B2 JPH0436455 B2 JP H0436455B2 JP 22067183 A JP22067183 A JP 22067183A JP 22067183 A JP22067183 A JP 22067183A JP H0436455 B2 JPH0436455 B2 JP H0436455B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- melting point
- doped
- point metal
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000002844 melting Methods 0.000 claims description 19
- 239000012535 impurity Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 14
- 230000008018 melting Effects 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 229910001507 metal halide Inorganic materials 0.000 claims description 3
- 150000005309 metal halides Chemical class 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 229910015275 MoF 6 Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical group 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- -1 Mo and W Chemical class 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 150000004820 halides Chemical class 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は高融点金属のハロゲン化物により、Si
を高融点金属に置換する方法を用いて、高融点金
属を主体とする電極配線を形成する半導体装置の
製造方法に関するものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention is directed to the use of high melting point metal halides.
The present invention relates to a method of manufacturing a semiconductor device in which an electrode wiring mainly made of a high-melting point metal is formed using a method of substituting a high-melting point metal with a high-melting point metal.
従来半導体装置の電極配線にはAl膜や多結晶
Si膜が用いられている。しかし、Al膜は融点が
低くAl形成後の高温処理は行なえないという制
約があり、一方、多結晶Si膜は高濃度に不純物を
添加しても電気抵抗が大きく、半導体装置の高速
度動作には不適当であるという欠点がある。ま
た、MoやＷなどの高融点金属、またはそのシリ
サイドが電極配線として用いられつつあるが、該
電極とゲート酸化膜あるいはゲート酸化膜とSi基
板との界面特性および該電極とSi基板とのコンタ
クト特性が多結晶Siに比べて悪いという欠点があ
る。そこで、下層をSi膜、上層を高融点金属また
はそのシリサイドとする二層膜を電極配線とする
方法が提案されている（特開昭56−62339号）。
Conventional semiconductor device electrode wiring uses Al films and polycrystalline
A Si film is used. However, Al films have a low melting point and are limited by the inability to perform high-temperature treatment after Al formation.On the other hand, polycrystalline Si films have high electrical resistance even when doped with high concentrations of impurities, making them difficult to operate at high speeds in semiconductor devices. has the disadvantage of being inappropriate. In addition, high melting point metals such as Mo and W, or their silicides are being used as electrode wiring, but the interface characteristics between the electrode and the gate oxide film or the gate oxide film and the Si substrate, and the contact between the electrode and the Si substrate It has the disadvantage that its properties are worse than that of polycrystalline Si. Therefore, a method has been proposed in which the electrode wiring is a two-layer film in which the lower layer is a Si film and the upper layer is a high melting point metal or its silicide (Japanese Patent Laid-Open No. 56-62339).
上記特許においては、高融点金属またはそのシ
リサイドを形成する方法として、スパツタ法、蒸
着法、CVD法が挙げられているが、スパツタ法
および蒸着法はCVD法に比べて形成された金属
膜の純度が悪いという欠点があり、さらに段差被
覆形状が悪いため断線等の問題が生じる。また
CVD法においては、高融点金属の塩化物を用い
るため、一般に高融点金属の塩化物は常温で固体
であるので、蒸気圧制御が難しく、したがつて原
料ガスの濃度制御が難しいという欠点がある。 In the above patent, the sputtering method, vapor deposition method, and CVD method are cited as methods for forming high-melting point metals or their silicides, but the sputtering method and vapor deposition method have higher purity of the metal film formed than the CVD method. It has the disadvantage of being poor, and furthermore, the shape of the step covering is poor, leading to problems such as wire breakage. Also
In the CVD method, the chloride of a high-melting point metal is used, and as the chloride of a high-melting point metal is generally solid at room temperature, it is difficult to control the vapor pressure, and therefore it is difficult to control the concentration of the raw material gas. .
本発明はこれらすべての欠点を解決し、界面特
性が良好で配線抵抗の低い高速度動作に適した半
導体装置の製造方法を提供することを目的とす
る。
SUMMARY OF THE INVENTION An object of the present invention is to solve all of these drawbacks and provide a method for manufacturing a semiconductor device that has good interface characteristics, low wiring resistance, and is suitable for high-speed operation.
本発明は上記目的を達成するために、高濃度に
不純物をドープした第１のSi膜上に不純物をドー
プしない、もしくは不純物濃度が上記第１のSi膜
の不純物濃度より低い第２のSi膜を堆積し、高融
点金属のハロゲン化物雰囲気中で熱処理すること
により、上記第２のSi膜を高融点金属に置換し、
高濃度に不純物をドープした上記第１のSi膜と高
融点金属膜の二層膜を電極配線とするものであ
る。
In order to achieve the above object, the present invention provides a second Si film which is not doped with impurities on a first Si film doped with impurities at a high concentration, or whose impurity concentration is lower than the impurity concentration of the first Si film. is deposited and heat treated in a high melting point metal halide atmosphere to replace the second Si film with a high melting point metal,
The two-layer film of the first Si film doped with impurities at a high concentration and a high melting point metal film is used as an electrode wiring.
以下、図面に基づいて本発明の実施例を説明す
る。
Embodiments of the present invention will be described below based on the drawings.
第１図Ａ〜Ｃは本発明による一実施例である
MOSFETのゲート電極の製造工程の概略図であ
る。図中１はSi基板、２はフイールド酸化膜、３
はゲート酸化膜、４はＰドープ多結晶Si膜（第１
のSi膜）、５は不純物をドープしない多結晶Si膜
（第２のSi膜）、６はMo膜である。 Figures 1A to 1C are one embodiment of the present invention.
FIG. 3 is a schematic diagram of the manufacturing process of a gate electrode of a MOSFET. In the figure, 1 is the Si substrate, 2 is the field oxide film, and 3 is the Si substrate.
4 is a gate oxide film, 4 is a P-doped polycrystalline Si film (first
5 is a polycrystalline Si film (second Si film) not doped with impurities, and 6 is a Mo film.
まず、一般に知られている工程により、フイー
ルド酸化膜２およびゲート酸化膜３を形成し、そ
の後第１図Ａに示すように、低圧気相成長法によ
り、反応炉内圧力6.9×10-4atm、温度650℃、反
応炉内へ導入するガスとしてSiH4の流量600c.c.／
min、PH3（He希釈濃度0.5％）の流量227c.c.／
minの条件で、Ｐ濃度４×1020cm-3のＰドープ多
結晶Si膜４を約2000Å堆積し、続いて、PH3の流
量を０にし、不純物をドープしない多結晶Si膜５
を約2000Å堆積させる。次に、第１図Ｂに示すよ
うに、上記二層の多結晶Si膜をマスクを用いてエ
ツチング加工しゲート電極を形成する。その後、
反応炉内圧力４×10-4atm、温度300℃の条件で
MoF6とH2（MoF6／H2＝１／５（モル比））の混
合ガス雰囲気中で約30分間熱処理し、第１図Ｃに
示すように、不純物を含まないSi膜をMoに置換
する。このようにして、Si基板１上のゲート酸化
膜３上に高濃度にＰをドープした多結晶Si膜４と
Mo膜６の二層構造のゲート電極を形成した。 First, a field oxide film 2 and a gate oxide film 3 are formed by a generally known process, and then, as shown in FIG . , temperature 650℃, flow rate of SiH 4 as gas introduced into the reactor 600c.c./
min, PH 3 (He dilution concentration 0.5%) flow rate 227c.c./
A P-doped polycrystalline Si film 4 with a P concentration of 4×10 20 cm -3 is deposited to a thickness of approximately 2000 Å under conditions of
Deposit approximately 2000Å. Next, as shown in FIG. 1B, the two-layer polycrystalline Si film is etched using a mask to form a gate electrode. after that,
Under the conditions of reactor pressure 4×10 -4 atm and temperature 300℃
Heat treatment is performed for approximately 30 minutes in a mixed gas atmosphere of MoF 6 and H 2 (MoF 6 /H 2 = 1/5 (molar ratio)), and the impurity-free Si film is converted to Mo as shown in Figure 1C. Replace. In this way, a polycrystalline Si film 4 doped with P at a high concentration is formed on the gate oxide film 3 on the Si substrate 1.
A gate electrode having a two-layer structure of Mo film 6 was formed.
第２図にAs、ＰおよびＢをイオン注入した後
熱処理（300℃、20分）を行なつたSi基板上へ、
Mo膜の堆積を行なつたときの、Mo堆積量とド
ーズ量の関係を示す。図から明らかなように、
Mo堆積量はドーズ量の増加に伴い減少し、Asお
よびＰドーズ量が６×1015cm-2以上ではMoの堆
積は観察されない。この結果から、多結晶Si膜上
へのMo膜の堆積速度は、多結晶Si膜上へのMo
膜の堆積速度は、多結晶シリコンの製作条件によ
り多少異なるが、高濃度に不純物をドープすれば
やはりMoの堆積は観察されないことが容易にわ
かる。したがつて上記二層の多結晶Si膜では、下
層のSi膜（第１のSi膜）は高濃度にＰがドープさ
れているためMoとの置換速度は極めて遅く、上
層のSi膜（第２のSi膜）のみMoに置換され、高
濃度に不純物をドープしたSi膜とMo膜の二層膜
をゲート電極として形成することができる。 Figure 2 shows a Si substrate that has been ion-implanted with As, P, and B and then heat-treated (300°C, 20 minutes).
The relationship between the amount of Mo deposited and the dose when depositing a Mo film is shown. As is clear from the figure,
The amount of Mo deposited decreases as the dose increases, and no Mo deposition is observed when the As and P doses are 6×10 15 cm -2 or more. From this result, the deposition rate of Mo film on polycrystalline Si film is
Although the deposition rate of the film varies somewhat depending on the manufacturing conditions of polycrystalline silicon, it is easy to see that no Mo deposition is observed if the impurity is doped at a high concentration. Therefore, in the above-mentioned two-layer polycrystalline Si film, the lower Si film (first Si film) is doped with P at a high concentration, so the replacement rate with Mo is extremely slow, and the upper Si film (first Si film) is doped with P. Only the Si film (No. 2) is replaced with Mo, and a two-layer film of a Si film and a Mo film doped with impurities at a high concentration can be formed as a gate electrode.
第３図に本発明の方法により、温度300℃、
MoF6分圧7.5×10-5atm、H2分圧3.7×10-4atmの
条件でSi基板上に堆積したMo膜中の膜厚方向の
Si濃度の分布をSIMS（Secondary Ion Mass
Spectrometry）法により分析した結果を示す。
本発明の方法は、拡散により、Mo膜の表面に達
したSiとMoF6との反応を利用したものであるた
め、この図に示すように、Mo膜中にSiが含まれ
ていることがわかる。 Figure 3 shows the method of the present invention at a temperature of 300°C.
The thickness direction of the Mo film deposited on the Si substrate under the conditions of MoF 6 partial pressure 7.5×10 -5 atm and H 2 partial pressure 3.7×10 -4 atm.
The distribution of Si concentration was measured using SIMS (Secondary Ion Mass).
The results of analysis using the Spectrometry method are shown.
The method of the present invention utilizes the reaction between Si that has reached the surface of the Mo film through diffusion and MoF 6 , so as shown in this figure, it is possible to confirm that Si is contained in the Mo film. Recognize.
なお、本発明において、第１のSi膜と第２のSi
膜を形成する方法は何ら規制するものではない。
例えば、第１のSi膜を形成する方法として、蒸着
法で不純物を含まないSi膜を形成し、その後、不
純物をイオン注入してもよい。 Note that in the present invention, the first Si film and the second Si film
There are no restrictions on the method of forming the film.
For example, as a method of forming the first Si film, an impurity-free Si film may be formed by vapor deposition, and then impurity ions may be implanted.
以上説明したように、下層が高濃度に不純物を
ドープしたSi、上層がMoの二層膜をゲート電極
として形成できるから、界面特性は良好であり、
配線抵抗も低く、半導体装置の高速度動作に適し
ている。また、本発明ではCVD法により形成し
た多結晶Siを高融点金属のハロゲン化物中で熱処
理し、Siを高融点金属に置換するものであるから
形成された高融点金属の純度は良好であり、また
段差の被覆形状が良好で断線等の問題も生じな
い。さらに、CVD法による多結晶Si膜の形成に
おいては、膜厚の制御は、容易であり、かつ高濃
度に不純物をドープしたSiとMoとの置換速度は、
不純物をドープしないSiとMoとの置換速度に比
べ、２桁以上低いため、上層の高融点金属膜の膜
厚の制御は容易である。このように本発明の効果
は顕著である。
As explained above, since the gate electrode can be formed using a two-layer film consisting of Si doped with a high concentration of impurities in the lower layer and Mo in the upper layer, the interface characteristics are good.
It also has low wiring resistance and is suitable for high-speed operation of semiconductor devices. In addition, in the present invention, polycrystalline Si formed by the CVD method is heat-treated in a halide of a high-melting point metal to replace Si with a high-melting point metal, so the purity of the formed high-melting point metal is good. In addition, the step is covered in a good shape, and problems such as wire breakage do not occur. Furthermore, in forming polycrystalline Si films by the CVD method, the film thickness can be easily controlled, and the replacement rate of highly doped Si with Mo is
Since the substitution rate is more than two orders of magnitude lower than that of Si and Mo that are not doped with impurities, it is easy to control the thickness of the upper layer high melting point metal film. As described above, the effects of the present invention are remarkable.
第１図は本発明による一実施例である
MOSFETのゲート電極の形成工程の概要を示す
断面図、第２図はAs、ＰおよびＢのドーズ量と
Moの堆積量の関係を示すグラフ、第３図はSi基
板上に堆積したMo膜中の膜厚方向のSiおよび
Mo濃度分布を示すグラフである。
１…Si基板、２…フイールド酸化膜、３…ゲー
ト酸化膜、４…Ｐドープ多結晶Si膜（第１のSi
膜）、５…ノンドープ多結晶Si膜（第２のSi膜）、
６…Mo膜。
FIG. 1 is an embodiment according to the present invention.
A cross-sectional view showing the outline of the MOSFET gate electrode formation process, Figure 2 shows the dose amounts of As, P, and B.
A graph showing the relationship between the amount of Mo deposited, and Figure 3 shows the amount of Si in the film thickness direction in the Mo film deposited on the Si substrate.
It is a graph showing Mo concentration distribution. DESCRIPTION OF SYMBOLS 1...Si substrate, 2...Field oxide film, 3...Gate oxide film, 4...P-doped polycrystalline Si film (first Si
film), 5... non-doped polycrystalline Si film (second Si film),
6...Mo film.
Claims (1)
形成した不純物を含まないか、もしくは不純物濃
度が上記第１のSi膜の不純物濃度より低い第２の
Si膜を有する基板を、高融点金属のハロゲン化物
雰囲気中で熱処理することにより、上記第２のSi
膜のみ高融点金属に置換する工程を含む半導体装
置の製造方法。1 A first Si film containing a high concentration of impurities and a second Si film formed thereon that does not contain impurities or has an impurity concentration lower than the impurity concentration of the first Si film.
By heat-treating the substrate having the Si film in a high melting point metal halide atmosphere, the second Si
A method for manufacturing a semiconductor device including a step of replacing only the film with a high melting point metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22067183A JPS60113928A (en) | 1983-11-25 | 1983-11-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22067183A JPS60113928A (en) | 1983-11-25 | 1983-11-25 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60113928A JPS60113928A (en) | 1985-06-20 |
| JPH0436455B2 true JPH0436455B2 (en) | 1992-06-16 |
Family
ID=16754629
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22067183A Granted JPS60113928A (en) | 1983-11-25 | 1983-11-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60113928A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100319888B1 (en) | 1998-06-16 | 2002-01-10 | 윤종용 | Method of forming selective metal layer and method of forming capacitor and filling contact hole using the same |
| TW403991B (en) * | 1998-06-16 | 2000-09-01 | Samsung Electronics Co Ltd | Method of forming selective metal layer and method of forming capacitor and filling contact hole using the same |
-
1983
- 1983-11-25 JP JP22067183A patent/JPS60113928A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60113928A (en) | 1985-06-20 |
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