JPH04361448A - Carrier signal reproduction circuit - Google Patents

Abstract

PURPOSE:To prevent the deterioration in the synchronization lock characteristic. CONSTITUTION:A carrier phase control signal generating circuit 68 generates a carrier phase control signal based on quadrant signals 118,119 and error signals 120,121 from an A/D converter when a carrier asynchronous alarm signal 125 indicates 'an asynchronous state', and a loop filter 69 is operated to make the band wide. On the other hand, when the carrier asynchronous alarm signal 125 indicates 'a synchronous state', the carrier phase control signal generating circuit 68 generates a carrier phase control signal based on quadrant signals 114, 115 and error signals 116, 117 from a digital filter and the loop filter 69 is operated to make the band narrow.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier wave signal regeneration circuit included in a demodulator that performs orthogonal phase detection and demodulation of a multilevel digital modulation signal.

0002

2. Description of the Related Art As is well known, in a receiving side demodulator of a multi-level digital radio communication device, in order to obtain a demodulated baseband signal from a multi-level digital modulated signal, the received multi-level digital modulated signal is transmitted. A carrier wave signal regeneration circuit for reproducing a signal synchronized with the carrier wave signal of the side modulator is provided as a part of the circuit of the demodulator, and as this type of carrier wave signal regeneration circuit, for example, the one shown in FIG. 3 is conventionally known. There is.

In FIG. 3, an input multilevel digital modulation signal 101 is branched into two by a branch circuit 51. One branch signal 102 is transmitted to a multiplier 52 by converting a carrier wave signal 122 reproduced and outputted by a voltage controlled oscillator 66 to a phase shifter 67.
The demodulated baseband signal 104 is multiplied by the orthogonal regenerated carrier signal 123 phase-shifted by 90°. Further, the other branched signal 103 is multiplied by a reproduced carrier signal 122 directly supplied from the voltage controlled oscillator 66 in a multiplier 53 to become a demodulated baseband signal 105. That is,
Quadrature phase detection was used.

[0004] The demodulated baseband signals 104 (105) are respectively band-limited to remove harmonics by low-pass filters 54 (55) to become signals 106 (107), and further processed by DC amplifiers 56 (57). It is amplified to a predetermined level necessary for A/D conversion and becomes a signal 108 (109), which is input to the A/D converter 58 (59), and a digital signal string 110 (111) which is a digital signal before band limitation.
is converted to Next, the digital signal string 110 (11
1) are respectively input to digital filters 60 (61) and subjected to band limiting for reducing intersymbol interference, that is, band limiting that satisfies Nyquist symmetry. (113).

[0005] Then, the main data signal sequence 112 (113)
is output to the demodulator main body side (not shown), but a part (quadrant signal) 114 of the main data signal string 112 and the main data signal string 1
13 (error signal) 117 is the exclusive OR circuit 62
Also, part of the main data signal sequence 113 (quadrant signal) 115 and part of the main data signal sequence 112 (error signal) 1
16 is input to the exclusive OR circuit 63, and subjected to exclusive OR operation to become the signal 118 (119), which is added in the adder circuit 64 to produce a carrier wave phase control signal indicating the phase error of the receiving side carrier wave signal. It becomes 120. The carrier wave phase control signal 120 is processed by a loop filter 65, in which harmonic components unnecessary for carrier wave phase control are removed, and the signal 121 is
and is given to the voltage controlled oscillator 66 as a control signal. Thereby, the voltage controlled oscillator 66 reproduces and outputs the carrier signal 122 necessary for quadrature phase detection.

As explained above, the carrier wave signal regeneration circuit constitutes a so-called PLL and controls the phase of the carrier wave signal based on the demodulated baseband signal. This is widely known to the public as described in publications and the like.

[0007]

In the conventional carrier wave signal reproducing circuit described above, since a digital filter having multiple taps is included in the loop, the delay time within the loop becomes significantly longer than the period of the carrier wave signal. Therefore, when the frequency of the input multilevel digital modulation signal is different from that of the regenerated carrier wave signal, it takes a significant amount of time for the phase error signal to reach the voltage controlled oscillator. As a result, there are problems such as the synchronizable frequency difference range (so-called capture range) becoming extremely narrow, and even within the capture range, the time until synchronization (so-called pull-in time) becomes longer.

An object of the present invention is to provide a carrier signal reproducing circuit that can always obtain optimal carrier signal reproducing characteristics by improving the characteristics of both the synchronization process and the steady state.

[0009]

Means for Solving the Problems In order to achieve the above object, a carrier wave signal reproducing circuit of the present invention has the following configuration. That is, the carrier wave signal regeneration circuit of the present invention includes: a voltage controlled oscillator that reproduces and outputs a carrier wave signal according to a carrier wave phase control signal that has been subjected to a filtering process; a circuit that performs quadrature phase detection using the recovered carrier signal having a phase difference of 90°; two A/D converters that convert the detection outputs of the quadrature phase detection circuit into pre-band-limited digital signals; and the two A/D converters. two digital filters each receiving an output of an A/D converter, performing band-limiting processing, and outputting a digital signal after band-limiting; in a carrier wave signal regeneration circuit comprising; A circuit that receives a quadrant signal and an error signal of each of the restricted digital signals, performs a logical operation on one of the quadrant signals and error signal, and generates a carrier phase control signal before filtering. When the carrier wave asynchronization alarm signal (signal indicating whether or not the reproduced carrier wave signal is synchronized with the input multilevel digital modulation signal) indicates asynchrony, the quadrant signal and error signal of the digital signal before band limitation are detected. a carrier phase control signal generation circuit that selects a quadrant signal and an error signal of the band-limited digital signal when indicating synchronization; filtering the output of the carrier phase control signal generation circuit; A loop filter that outputs a processed carrier wave phase control signal, the loop filter that operates to widen the band when the carrier wave asynchronization alarm signal indicates non-synchronization, and narrows the band when the carrier wave asynchronization alarm signal indicates synchronization. It is characterized by having the following features.

0010

[Operation] Next, the operation of the carrier wave signal reproducing circuit of the present invention constructed as described above will be explained. In the present invention, the quadrant signal and error signal required to generate the carrier phase control signal are switched depending on whether the regenerated carrier signal is synchronized with the input multilevel digital modulation signal, and the band of the loop filter is changed. change. That is, when the carrier asynchronization alarm signal indicates asynchronization, the quadrant signal and error signal of the digital signal before inputting the digital filter (before band limitation) are selected to shorten the delay time in the loop, and to widen the band of the loop filter. The characteristics of the synchronization process are improved by expanding the capture range and shortening the pull-in time. On the other hand, when indicating synchronization, the quadrant signal and error signal of the digital signal are selected after the digital filter output (after band limiting) to generate a more accurate carrier phase control signal, and the band of the loop filter is narrowed. to suppress phase jitter and improve steady-state characteristics. As a result, optimal carrier signal reproduction characteristics can always be obtained.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a carrier signal regeneration circuit according to an embodiment of the present invention. In FIG. 1, the same components as those in the conventional example shown in FIG. 3 are designated by the same reference numerals. Hereinafter, parts related to the present invention will be mainly explained.

In the present invention, the conventional exclusive OR circuit 62
, 63 and the adder circuit 64, a carrier wave phase control signal generation circuit 68 is provided, and a digital filter 60 is provided in this.
In addition to the quadrant signals (114, 115) and error signals (116, 117) from the same 61, the A/D converter 58 and the same 59
Quadrant signals (118, 119) and error signals (120, 121), which are part of the output, are input. In addition, a carrier wave asynchronization alarm signal 125 is obtained from the demodulator main body side (not shown),
This is inputted to the carrier phase control signal generation circuit 68 and the loop filter 69 as a control signal. This carrier wave asynchronization alarm signal 125 is a signal indicating whether or not the reproduced carrier wave signal 122 is synchronized with the input multilevel digital signal 101.

Specifically, the carrier phase control signal generation circuit 68 is composed of a switching circuit 71, an exclusive OR circuit 72, an exclusive OR circuit 73, and an addition circuit 74, as shown in FIG. The switching circuit 71 receives a quadrant signal (118
, 119) and error signals (120, 121), quadrant signals (114, 115) and error signals (116, 117) from the digital filter are input, and a carrier asynchronous alarm signal 125 is input as a switching control signal. Ru. That is, the carrier phase control signal generation circuit 68 is constructed by providing a switching circuit 71 on the input side of the conventional exclusive OR circuits 62 and 63.

[0014] Carrier wave asynchronous alarm signal 125 is "asynchronous"
, the switching circuit 71 switches between the quadrant signal and error signal of the digital signal before inputting the digital filter (before band limiting), that is, the quadrant signal (118, 11) from the A/D converter.
9) and error signals (120, 121). As a result, the in-loop delay time is shortened, the carrier phase control signal 120 is generated early, and is provided to the loop filter 69. At this time, the loop filter 69 operates to widen the band. Therefore, the capture range is expanded and the pull-in time is shortened, and the characteristics of the synchronization process are improved.

On the other hand, when the carrier asynchronous alarm signal 125 indicates "synchronization", the switching circuit 71 outputs the quadrant signal and the error signal of the digital signal after outputting the digital filter (after band limiting), that is, the quadrant signal from the digital filter. (1
14, 115) and the error signal (116, 117). As a result, a more accurate carrier phase control signal 120 is generated and provided to the loop filter 69. At this time, the loop filter 69 operates to narrow the band. Therefore, phase jitter is suppressed and steady state characteristics are improved.

[0016]

As explained above, according to the carrier wave signal regeneration circuit of the present invention, a carrier wave phase control signal is generated depending on whether or not the regenerated carrier wave signal is synchronized with the input multilevel digital modulation signal. By switching the quadrant signal and error signal necessary for the process, and changing the band of the loop filter, it is possible to improve the characteristics of the synchronization process and the steady state, and always achieve optimal carrier signal regeneration. It has the effect of allowing you to acquire characteristics.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram of a carrier signal regeneration circuit according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a carrier phase control signal generation circuit.

FIG. 3 is a configuration block diagram of a conventional carrier signal regeneration circuit.

[Explanation of symbols]

51 Branch circuit 52 Multiplier 53 Multiplier 54 Low pass filter 55 Low pass filter 56 DC amplifier 57 DC amplifier 58 A/D converter 59 A/D converter 60 Digital filter 61 Digital filter 66 Voltage controlled oscillator 67 Phase shifter 68 Carrier phase control signal generation circuit 71 Switching circuit 72 Exclusive OR circuit 73 Exclusive OR circuit 74 Adder circuit

Claims (1)

[Claims] 1. A voltage controlled oscillator that reproduces and outputs a carrier signal in response to a filtered carrier phase control signal;
a circuit that branches an input multilevel digital modulation signal into two and performs orthogonal phase detection on each of the regenerated carrier signals having a phase difference of 90 degrees; two A/D converters that convert the outputs of the two A/D converters into two A/D converters; two digital filters that respectively receive the outputs of the two A/D converters, perform band-limiting processing, and output band-limited digital signals; In a carrier wave signal regeneration circuit comprising; receiving the quadrant signal and error signal of the pre-band-limited digital signal and the band-limited digital signal, and performing logical operations on either quadrant signal and error signal; This is a circuit that generates a carrier wave phase control signal for a carrier wave asynchronization alarm signal (
When the signal indicating whether or not the reproduced carrier signal is synchronized with the input multilevel digital modulation signal indicates asynchronous, the quadrant signal and error signal of the pre-band-limited digital signal are selected to indicate synchronization. a carrier phase control signal generation circuit that selects a quadrant signal and an error signal of the band-limited digital signal; filtering the output of the carrier phase control signal generation circuit to obtain the filtered carrier phase control signal; a loop filter that outputs a carrier wave asynchronization alarm signal, which operates to widen the band when the carrier asynchronous alarm signal indicates asynchronous, and narrow the band when the carrier wave asynchronous alarm signal indicates synchronization; Characteristic carrier signal regeneration circuit.