JPH0316318A - Phase locked loop - Google Patents

Abstract

PURPOSE:To reduce the scale of the circuit by multiplying a phase error signal by 1st and 2nd filter coefficients, integrating the result, and adding the integrated result to an output being the result of multiplying the phase error signal by the 1st filter coefficient to obtain a control signal. CONSTITUTION:A reference input Di and a reproduced carrier from a voltage controlled oscillator 3 in a phase locked loop are fed to a phase comparator 1, in which the phases are compared to obtain a phase error signal, a 1st multiplier 6 multipliers the phase error signal by the 1st filter coefficient in a loop filter 2 and a 2nd multiplier 5 multiplies the output of the 1st multiplier 6 by the 2nd filter coefficient. Then an integration device 4 integrates the output of the 2nd multiplier 5, an adder 7 adds the output of the 1st multiplier 6 and the output of the integration device 4 to obtain a control signal for a voltage controlled oscillator 3. Thus, the scale of the circuit is reduced.

Description

[Detailed Description of the Invention] [Summary] Regarding the phase-locked loop, there is no need to control the integrator when switching the bandwidth.
The aim is to provide a phase-locked loop with a small number of bits in the multiplier and which can reduce the number of multipliers. The phase-locked loop obtains the regenerated carrier wave phase-synchronized with the reference input by passing the phase error signal obtained through a loop filter and feeding back the obtained control signal to the voltage-controlled oscillator. a first multiplier that multiplies the output of the first multiplier by a second filter coefficient; and an integral that integrates the output of the second multiplier. and an adder that adds the output of the first multiplier and the output of the integrator to obtain the control signal.

[Industrial Field of Application] The present invention relates to a phase-locked loop, and particularly to a phase-locked loop whose bandwidth can be switched.

A phase-locked loop is used as a digital carrier regeneration circuit of a digital demodulator that demodulates a digitally modulated wave.

A digital demodulator on the receiving side of a digital radio satellite communication system includes a digital carrier regeneration circuit and demodulates a digital modulated wave using a carrier regenerated from a received signal.

In a digital phase-locked loop used as such a digital carrier regeneration circuit, etc., in order to demodulate a received signal consisting of a burst wave, it is necessary to synchronize with the carrier during a short preamplule signal period at the beginning of the burst signal. It is necessary to widen the bandwidth and narrow the bandwidth in the subsequent data signal part to suppress the jitter of the reproduced carrier. A modified phase-locked loop is used.

In such a bandwidth switching type phase-locked loop, there is no need to control the integrator used in the phase-locked loop when switching filter coefficients, and the number of bits required in the multiplier is small. It is desired that the number of multipliers be small.

[Conventional technology]

FIG. 8 shows an example of the structure of a conventional phase-locked loop, in which a phase comparator 1, a loop filter 2. A digital phase locked loop is shown in which a voltage controlled oscillator (digital ■C○) 3 is connected in a closed loop.

A phase comparator l compares the phases of the reference input D1 and the reproduced carrier wave DO, and generates a phase error signal C.

Loop filter 2 removes noise from the output of phase comparator 1 and generates control signal A for voltage controlled oscillator 3.

The voltage controlled oscillator 3 performs an oscillation operation in response to the control signal A, thereby generating a reproduced carrier wave Do whose frequency changes in accordance with the reference input Di.

Loop filter 2 is interpolated from integrator 4, multiplier 5.6 and adder 7. The integrator 4 has a well-known structure consisting of an adder 8 and a delay section (T) 9.

In the loop filter 2, the phase error signal C is applied to the integrator 4, and the adder 8 integrates the output signal by adding it to the signal delayed by the delay section 9. By multiplying the output signal of the integrator 4 by a coefficient α in the multiplier 5, the illustrated signal B is generated.

Adder 7 adds this signal B and phase error signal C,
Furthermore, a control signal A for the voltage controlled oscillator 3 is generated by multiplying the output signal of the adder 6 by a coefficient β in a multiplier 6.

Here, the coefficients α, β are the time constants τ1, . If we have τ2, α=T/τ1, β=T/τ
2 (T is the calculation period in the phase-locked loop).

In a steady state, that is, in a state in which phase synchronization between the reference input Di and the reproduced carrier wave Do is established, the bandwidth BL of the loop filter 2 is determined by the coefficient α. It is known that the following relationship exists between the natural frequency ωn,@attenuation rate ζ of the phase-locked loop and the bandwidth B, which is determined by β.

mn=k+Fi'? −(1
). =k2F771 ・−・(2
) where k+, kz are constants The phase-locked loop shown in FIG. 8 also includes an integral element in the voltage controlled oscillator 3, and exhibits second-order lag characteristics due to the integrator 4 in the loop filter 2. In digital radio satellite communication, there are parts of the received signal that are in the form of bursts. During this period, you must perform synchronization pull-in with your carrier. Therefore, the bandwidth of the phase-locked loop must be widened during this period. On the other hand, in the subsequent data signal period, it is necessary to narrow the bandwidth in order to suppress the jitter of the reproduced carrier.

In this way, in order to switch the bandwidth of the phase-locked loop during synchronization pull-in and in the steady state after synchronization pull-in, the loop filter 2 is used as a two-mode filter. What is necessary is to switch the coefficients α and β.

In other words, from the relationships in equations (1) to (3) above, if the attenuation rate ζ is constant, in order to widen the bandwidth BL, the coefficients α,
In order to increase β and narrow the bandwidth Bt, the coefficient α,
It is sufficient to reduce β.

On the other hand, the voltage value Vo of the control signal A in a steady state in the phase-locked loop shown in FIG. 8 is determined by the accumulated charge q in the integrator 4, and it is known that the following relationship exists.

Vo=a-β. 9 ・One・(4
) From equation (4), even if the coefficients α and β are switched to change the bandwidth, the magnitude of the control signal to the voltage controlled oscillator 3 is not changed, and the phase synchronization state before and after switching is maintained. To do this, the accumulated charge of the integrator is changed according to the switching of the coefficients α and β.
Control must be performed so that the control voltage Vo does not change. If in a two-mode filter, simply the coefficient α・
If you try to control the bandwidth by switching only β, the control voltage Vo will suddenly change due to switching, resulting in loss of synchronization, and it will take a certain amount of time to establish phase synchronization again after switching, and the bandwidth will change in a short time. This means that switching will not be possible.

FIG. 9 shows another configuration example of a conventional phase-locked loop, in which the same parts as in FIG. 8 are designated by the same numbers, 10, 18. 19 is a switch, and 1l is a magnification unit.

In FIG. 9, switch 18. By switching filter coefficients α1, α2, and β1β2 using 19, the bandwidth of the loop filter 2 can be switched. The switch 1o connects the output of the delay section 9 directly to the input of the adder 8, or connects the output of the delay section 9 to the adder 8 via the multiplier section l1, depending on the switching of the filter coefficients.
Connect to the input of

The multiplying unit 10 functions to multiply the accumulated charge in the delay unit 9 by X and output it.

FIG. 10 is a time chart showing the operation in the phase-locked loop of FIG. 9, and shows the control signal of the filter coefficient β, the corresponding change in the value of the coefficient β, and the multiplier 1l with respect to the operation clock CLK. The control signal that defines the quiring ξ to impose and the corresponding change in the value of the signal B are shown.

Therefore, in the digital demodulator using the phase-locked loop shown in FIG. 9, the bandwidth is widened in order to synchronize with the carrier during the short preamble signal period at the beginning of the burst signal, and the subsequent data In the signal part, control to widen the bandwidth in order to suppress the jitter of the reproduced carrier can be stably performed in a short time without causing the phase-locked loop to go out of synchronization.

Regarding such a phase-locked loop, patent application No. 1983
It is described in detail in No.-222432.

[Problem to be Solved by the Invention] In the conventional phase-locked loop described above, each time the filter coefficient is switched in order to switch the bandwidth, the integrator is controlled in response to the change, and its charge accumulation characteristics are switched. Therefore, there is a problem that control becomes complicated.

Furthermore, in the above-mentioned conventional phase-locked loop, a multiplier is placed after the integrator, so there is a problem that the number of operation bits required in the multiplier increases.

Furthermore, since two multipliers are required, there is a problem that the circuit scale becomes large.

The present invention aims to solve the problems of the prior art, and by placing the multiplier after the integrator, there is no need to control the integrator in response to switching the bandwidth. It is an object of the present invention to provide a phase-locked loop that requires a small number of bits in a multiplier and can reduce the circuit scale by reducing the number of multipliers.

[Means for Solving the Problems] The present invention, as shown in its principle structure in FIG. In addition, in the phase-locked loop which obtains the regenerated carrier wave which is phase-synchronized with the reference input by passing the obtained phase error signal through the loop filter 2 and feeding back the obtained control signal to the voltage-controlled oscillator 3, the loop filter 2 1 multiplier 6, second multiplier 5, and integrator 4
and an adder 7.

Here, the first multiplier 6 multiplies the phase error signal by the first filter coefficient, and the second multiplier 5 multiplies the first filter coefficient by the phase error signal.
The output of the multiplier 6 is multiplied by the second filter coefficient. The integrator 4 integrates the output of the second multiplier 5, and the adder 7 adds the output of the first multiplier 6 and the output of the integrator 4 to generate voltage controlled oscillation 'H3. This is to obtain a control signal for.

In addition, in such a phase-locked loop, the first and second filter coefficients each have a plurality of values, so that they can be switched and applied to the first multiplier 6 and the second multiplier 5. It is something.

Furthermore, as shown in FIG. 1(b), the present invention applies the reference input and the regenerated carrier wave from the voltage controlled oscillator 3 to the phase comparator 1, and loops the obtained phase error signal. In a phase-locked loop that obtains the regenerated carrier wave that is phase-synchronized with the reference input by feeding back a control signal obtained through the filter 2 to the voltage-controlled oscillator 3, the loop filter 2 includes a first selector 51 and a second selector. 5
2, a multiplier 53, a storage section 54, an integrator 4, and an addition B7.

Here, the first selector 51 switches and outputs the first and second filter coefficients, and the second selector 52 switches and outputs the phase error signal and the output of the multiplication word 53. be. The multiplier 53 multiplies the output of the first selector 51 and the output of the second selector 52, and the storage unit 54 stores the phase error signal in the output of the multiplier 53 and one of the filter coefficients. It holds and outputs the multiplication result. Further, the integral H4 integrates and outputs the result of multiplying the phase error signal at the output of the multiplier 53 by the first filter coefficient and the second filter coefficient, and the adder 7 integrates and outputs the result of multiplying the phase error signal at the output of the multiplier 53 by the first filter coefficient and the second filter coefficient. The above-mentioned control signal is generated by adding the output of the integrator 4 and the output of the integrator 4.

(Function) In the phase-locked loop, the phase error signal obtained by adding the reference input and the regenerated carrier wave from the voltage controlled oscillator 3 to the phase comparator 1 and comparing the phases is passed through the loop filter 2 to generate a voltage. A control signal is obtained for the controlled oscillator 3, and this control signal is fed back to the voltage controlled oscillator 3 to control it, thereby obtaining a regenerated carrier wave that is phase-synchronized with the reference input from the voltage controlled oscillator 3. , in the loop filter 2, the first multiplier 6 multiplies the phase error signal by the first filter coefficient, and the second multiplier 5 multiplies the output of the first multiplier 6 by the second filter coefficient. and the second
The output of the first multiplier 5 is integrated, and the output of the first multiplier 6 and the output of the integrator 4 are added by an adder 7 to obtain a control signal for the voltage controlled oscillator 3.

Further, in such a phase-locked loop, the first and second filter coefficients each have a plurality of values, and can be switched and applied to the first and second multipliers 5.6.

Therefore, in the phase-locked loop of the present invention, in order to prevent the magnitude of the control signal to the voltage controlled oscillator from changing even when the filter coefficients are switched and the bandwidth is switched, the integrator is There is no need to control the system, making the precepts easier. Furthermore, in the phase-locked loop of the present invention, since the multiplier is placed before the integrator, the number of operation bits required in the multiplier is reduced, and the circuit scale can be reduced.

Furthermore, in the phase-locked loop of the present invention, the reference input and the regenerated carrier wave from the voltage-controlled oscillator 3 are applied to the phase comparator l, the obtained phase error signal is passed through the loop filter 2, and the obtained control signal is sent to the voltage-controlled oscillator. In the loop filter 2, for the phase-locked loop that obtains the regenerated carrier wave that is phase-synchronized with the reference input by feeding back to the reference input.
The first selector 51 switches and outputs the first and second filter coefficients, the second selector 52 switches and outputs the phase error signal and the output of the multiplier 53, and the multiplier 53 switches and outputs the first and second filter coefficients. Multiplying the output of the selector 51 and the output of the second selector 52, holding and outputting the multiplication result of the phase error signal in the output of the multiplier 53 and one of the filter coefficients by the storage unit 54,
The integrator 4 integrates and outputs the result of multiplying the phase error signal at the output of the multiplier 53 by the first filter coefficient and the second filter coefficient, and the adder 7 integrates and outputs the multiplication result of the phase error signal at the output of the multiplier 53 .
4 and the output of integrator 4 are added together to generate a control signal for voltage controlled oscillator 3.

Therefore, according to the present invention, even if the filter coefficients are switched to switch the bandwidth, there is no need to control the integrator correspondingly, and the configuration is simplified, and the multiplier is placed before the integrator. Therefore, the number of operation bits required in the multiplier is reduced, the circuit scale can be reduced, and the number of required multipliers can be reduced.

〔Example〕

FIG. 2 shows one embodiment of the present invention, and FIG.
The same parts are shown with the same numbers as in the figure, but the 8th
Compared to the case shown in the figure, the position of the multiplier 5.6 is different.

In FIG. 2, a phase comparator 1 compares the phases of a reference input Di and a reproduced carrier wave Do, and generates a phase error signal C.

Loop filter 2 removes noise from the output of phase comparator 1 and generates control signal A for voltage controlled oscillator 3.

The voltage controlled oscillator 3 is composed of a digital ■c○, and performs an oscillation operation in response to the control signal A to generate a reproduced carrier wave Do whose frequency changes in accordance with the reference input Di.

The loop filter 2 is composed of an integrator 4, a multiplier 5.6, and an adder 7. The integrator 4 has a well-known structure consisting of an adder 8 and a delay section (T) 9.

- In the loop filter 2, a multiplier 6 multiplies the phase error signal C by a coefficient β to produce an output βC.

Further, in multiplier 5, this signal is multiplied by a coefficient α to produce an output αβC. Integrator 4 integrates this signal to produce the signal B' shown.

Adder 7 adds this signal B' and phase error signal C to generate control signal A for voltage controlled oscillator 3.

In the phase-locked loop of the present invention, when controlling the bandwidth in response to a burst signal, the loop filter 2 is used as a two-mode filter as in the conventional case. What is necessary is to switch the coefficients α and β.

In the phase-locked loop shown in FIG. 2, the integrator 4 is placed after the multiplier 6.5 and generates the control signal A by integrating the signal αβC resulting from the multiplication.

In this case, even if the coefficients α and β are switched in order to change the bandwidth of the loop filter 2, the output voltage value 0 held by the integration action in the integrator 4 remains unchanged and remains the previous value. Therefore, there is no risk of the phase locked loop becoming out of synchronization due to a sudden change in the oscillation frequency in the voltage controlled oscillator 3.

Therefore, according to the present invention, in the phase-locked loop, there is no need to control the integrator as the filter coefficients are switched. Bandwidth switching can be performed quickly and quickly.

Furthermore, in the case of the present invention, since the multiplier is placed before the integrator, the number of operational bits required in the multiplier is reduced.

FIGS. 3(a) and 3(b) show an example of a comparison of the number of bits of a multiplier between the present invention and the prior art, where (a) shows the conventional case shown in FIG. (b)
shows the case of the embodiment of the invention shown in FIG.

In FIG. 3(a), it is assumed that an 8-bit phase error signal C from a phase comparator is integrated in an integrator 4 to produce, for example, a 16-bit output signal. Multiplier 5 multiplies the 8-bit filter coefficient α to obtain 2
A signal B is generated as a 4-bit multiplication result. Both output signals are added in an adder 7 to produce a 24-bit output signal, ignoring carry, for example. In the multiplier 6,
This signal is multiplied by an 8-bit filter coefficient β to generate a 32-bit output signal A.

In FIG. 3(b), a multiplier 6 multiplies the 8-bit phase error signal C from the phase comparator by an 8-bit filter coefficient β to generate a 16-bit output signal βC. Further, the multiplier 5 multiplies the signal by an 8-bit filter coefficient α to generate a 24-bit multiplication result signal αβC. The integrator 4 integrates this signal to produce, for example, a 32-bit output signal B'. The adder 7 adds the two output signals to generate a 32-bit output signal A, ignoring carry, for example.

In the case of the prior art shown in FIG. 3(a), the multiplier 5 is 8×1
A 6-bit operation is performed, and the multiplier 6 performs an 8×24-bit operation. On the other hand, in the case of the present invention shown in FIG. 3(b), the multiplier 6 performs an operation of
performs an 8×16 bit operation. As described above, in the case of the present invention, the number of operational bits required for the multiplier can be reduced compared to the conventional case.

FIG. 4 shows an example of the application of the present invention, in which carrier wave regeneration (
This example illustrates a carrier recovery circuit.

In FIG. 4, the same parts as in FIG. 2 are designated by the same numbers. The phase comparator 1 consists of a phase rotation section 15 and a Costas-type phase error detection section 16, and the phase rotation section 15 includes multipliers 21, 22, 23, 24, 25, a -■ generator 26, and an adder. 27. 28.

Further, the phase error detection section 16 includes a multiplier 33, 34, an adder 35, a 3-1 selector 36, etc.
It has The loop filter 2 has a similar structure to that shown in FIG. Note that in the loop filter 2, a ×29 multiplier 12 is inserted in the multiplier 6 and the adder 7. Voltage control'<ffll oscillator (digital VCO) 3 includes an adder 4L delay unit 4 constituting an integrator.
2, a read only memory (ROM) 43 that generates a sine wave (SIN), and a read only memory (ROM) 44 that generates a cosine wave (COS).

In Fig. 4, the reference input is 4φPS consisting of 8 bits.
Orthogonal component 1 of K signal = Acos ((2k-1) z
/4+θi) and Q=Asin ((2k-1) π/
4+θi). These signals are input to the phase rotation unit 15 after having their phases adjusted in delay units (T) 13 and 14, respectively.

In the phase rotation unit 15, the multipliers 21 and 22 multiply both inputs by the cosine wave component cosθ0 of the 8-bit recovered carrier wave from the voltage controlled oscillator 3, and the multipliers 23 and 22 multiply the cosine wave component cosθ0 of the recovered carrier wave consisting of 8 bits from the voltage controlled oscillator 3.
At 24, both inputs are multiplied by the sine wave predetermined sin θ0 of the recovered carrier wave consisting of 8 bits from the voltage controlled oscillator 3 as is, and the other is multiplied by the -1 signal of the -1 generator 26 at the multiplier 25 and inverted. and multiply. Then, the output signals of multipliers 21 and 23 are added in adder 27, and multipliers 22 and 22. By adding the 24 output signals in the adder 28, an 8-bit signal 1'=Acos ((2k-L) z
/4+θi-θ0) and Q'=Asin ((2k-1
)π/4+θi−θ0).

In the phase error detection section 16, the amplitude of the signals 1' and Q' is limited by limiters 31 and 32, and the multiplier 33
In the multiplier 34, the input signal I' is multiplied by the output of the limiter 31, and in the adder 35, both multipliers 33 and 34 are multiplied.
By adding the outputs of , a phase error output for the 4φPSK signal is generated.

Further, from the output of the multiplier 34, an output of a phase error with respect to the 2φPSK signal is generated. Furthermore, the input signal Q' is lφP
It forms the output of the phase error with respect to the SK signal.

The 3-1 selector 36 indicates that the digital demodulator is 4φPSK.
Depending on whether it is for a signal, a 2φPSK signal, or a 1φPSK signal, select one of the corresponding phase error signals and perform 8.
Output signal f(θc) consisting of bits (signal C described above)
occurs.

In the loop filter 2, the phase error signal f(θC)
is multiplied by a coefficient β consisting of 8 bits in a multiplier 6 to produce an output βr (θC) consisting of 6 bits. This signal is multiplied by a coefficient α consisting of 8 bits in multiplier 5 to produce an output αβf(θC) consisting of 24 bits. Integrator 4 integrates this signal to produce the illustrated signal B' consisting of 28 bits. The adder 7 adds this signal B' and the signal βf(θC) from the multiplier 6 to obtain the control signal Vc(t) for the voltage controlled oscillator 3 (the signal A described above).
) occurs. At this time, the ×29 multiplier l2 multiplies the output signal βr (θC) of the multiplier 6 by 29 to generate a 27-bit signal, and performs decimal point matching between it and the output signal B' of the integrator 4. conduct.

The voltage controlled oscillator 3 has an integrator consisting of an adder 41 and a delay section 42, and has a signal V c (
After integrating t), the upper 10 bits of this integrated signal are used as an address to read out the data pre-stored in the ROM 43.44, and the cosine wave component cos θ0 of the above-mentioned 8-bit reproduced carrier wave is obtained. , a sine wave with a certain sin θ0.

The phase-locked loop in the embodiment shown in FIG. 2 includes two multipliers as control elements.

Multipliers generally have a complex configuration and use a large number of gates, so it is desirable to reduce the number of gates.

Therefore, it is conceivable to use l multipliers in a time-division manner to perform the same operation as the phase-locked loop of the embodiment shown in FIG.

FIG. 5 shows another embodiment of the invention, in which the same parts as in FIG. 2 are designated by the same numbers, and 18.19
is a switch.

The embodiment shown in FIG. 5 shows an example of a structure in which filter coefficients are switched. α2 can be switched, and filter coefficients β1 and β2 can be switched by a switch l9.

Therefore, in the phase-locked loop shown in FIG. By controlling the loop filter 19, the loop filter 2 can be made into a two-mode filter and its bandwidth can be switched, so that carrier wave regeneration corresponding to the burst wave as described above can be performed.

FIG. 6 shows still another embodiment of the present invention, in which the same parts as in FIG. 2 are designated by the same numbers, and l7
is a buffer (FF). Further, in the loop filter 2, 51 is a first selector consisting of a 2-1 selector;
52 is a second selector consisting of a 2-1 selector, 53 is a multiplier, and 54 is a storage section.

Further, FIG. 7 is a time chart showing signals of various parts in the embodiment of FIG. 6.

As shown in the time chart ■ in FIG. 7, the first selector 51 outputs the filter coefficient β during T/2 3iJI in the first half of the calculation period T, and outputs the filter coefficient α in the second half T/2 period. do. The second selector 52 selects T/T in the first half of the calculation period T, as shown in the time chart ■.
The signal C from the phase comparator 1 is output during two periods, and the second half T
The multiplier 53 outputs the multiplication result βC of the output of the second selector 52 and the output of the first selector 51 during the /2 period. The multiplier 53 calculates the calculation frequency! Since the filter coefficient α from the first selector 51 is multiplied by the calculation result βC from the second selector 52 during the T/2 period in the latter half of IT, the multiplier 53 outputs the result as shown in the time chart of FIG. As shown in the figure, the multiplication result βC is output during the T/2 period in the first half of the operation period T, and the multiplication result αβC is output during the T/2 PJ period in the second half.

As shown in the time chart (■) in FIG. 7, the storage unit 54 stores the output βC of the multiplier 53 in the T/2 period in the first half of the operation period T, and the output βC in the T/2 period in the second half of that period and in the next period. It is held for the lower period consisting of the first half T/2 period. Further, the integrator 4 accumulates the output αβC of the multiplier 53 during the T/2 period in the latter half of the calculation cycle jiJ1T during the next calculation cycle T, as shown in the time chart (2) in FIG.

Adder 7 adds output βC of storage unit 54 and output αβC of integrator 4. The FF 17 holds the addition result of the adder 7 every calculation period T, and uses this as a control signal A for voltage control. IIl is given to the oscillator 3. As a result, an operation as a phase locked loop is performed, and the voltage controlled oscillator 3 outputs a reproduced carrier wave Do whose frequency is controlled in accordance with the reference input Di.

According to the embodiment shown in FIG. 6, the filter coefficient α. Since one multiplier can perform two multiplications of β and the phase error signal, it is possible to reduce the circuit scale.

〔Effect of the invention〕

As explained above, according to the present invention, in a phase-locked loop in which the bandwidth can be switched by switching the filter coefficients in the loop filter, it is necessary to control the integrator in the loop filter in accordance with the switching of the filter coefficients. In addition, the number of operation bits of the multiplier in the loop filter can be reduced, reducing the circuit scale and reducing power consumption. This makes it possible to reduce costs, which is particularly advantageous when integrated into an LSI.

Furthermore, since two multiplications in the loop filter can be performed by time-sharing use of one multiplier,
It becomes possible to further reduce the circuit scale.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is (a). (b) is a diagram showing an example of a comparison of the number of bins of multipliers in the present invention and the prior art, FIG. 4 is a diagram showing an example of application of the present invention, and FIG. 5 is a diagram showing another embodiment of the present invention. FIG. 6 is a diagram showing still another embodiment of the present invention, FIG. 7 is a time chart showing various signals in the embodiment of FIG. 6, and FIG. 8 is a diagram of a conventional phase-locked loop. 9 is a diagram showing another example of the configuration of the conventional phase-locked loop, and FIG. 10 is a time chart 1 showing the operation of the phase-locked loop in FIG. 9.
It is. 1 is a phase comparator, 2 is a loop filter, 3 is a voltage controlled oscillator, 4 is an integrator, 5 is a first multiplier, 6 is a second multiplier, 7 is an adder, 51 is a first selector, 52 is a second selector, 53 is a power W-BS, and 54 is a storage section. Patent originator Fujitsu Limited

Claims (3)

[Claims] (1) The reference input and the regenerated carrier wave from the voltage controlled oscillator (3) are applied to the phase comparator (1), the obtained phase error signal is passed through the loop filter (2), and the obtained control signal is sent to the voltage controlled oscillator. (3) in a phase-locked loop that obtains the regenerated carrier wave that is phase-synchronized with the reference input by feeding back to the reference input, the loop filter (2) comprising a first
a multiplier (6) that multiplies the output of the first multiplier (6) by a second filter coefficient; It is characterized by comprising an integrator (4) that performs integration, and an adder (7) that adds the output of the first multiplier (6) and the output of the integrator (4) to obtain the control signal. phase-locked loop. (2) In the phase-locked loop according to claim 1, each of the first and second filter coefficients has a plurality of values, and is switched between the first and second multipliers (5, 6). A phase-locked loop characterized in that it is configured to be able to apply a voltage to the phase-locked loop. (3) The reference input and the regenerated carrier wave from the voltage controlled oscillator (3) are applied to the phase comparator (1), the obtained phase error signal is passed through the loop filter (2), and the obtained control signal is sent to the voltage controlled oscillator. (3) in which the loop filter (2) obtains the regenerated carrier wave phase-synchronized with the reference input by feeding back to the reference input, the loop filter (2) includes a first selector ( 51), a second selector (52) that switches and outputs the phase error signal and the output of the multiplier (53), and a switch between the output of the first selector (51) and the output of the second selector (52). the multiplier (53) that multiplies the output of the multiplier (53); and a storage unit (54) that holds and outputs the result of multiplying the phase error signal at the output of the multiplier (53) by one of the filter coefficients; an integrator (4) that integrates and outputs a multiplication result of the phase error signal at the output of the multiplier (53), a first filter coefficient, and a second filter coefficient; and an output of the storage section (54). and an adder (7) that adds the output of the integrator (4) and the output of the integrator (4) to generate the control signal.