JPH0271614A - Band width switching type secondary phase locked loop circuit - Google Patents

Abstract

PURPOSE:To switch band width in a short time and also as keeping a phase locked loop by varying the band width coefficient of a loop filter and the accumulation quantity of an integral element corresponding to the band width. CONSTITUTION:The coefficient switching means 24 of a loop filter means 20 consists of coefficient parts 241 and 242 on which coefficients alpha1 and alpha2 are set and a change-over switch 243, and a coefficient switching means 22 also consists of coefficient parts 221 and 222 on which coefficients beta1 and beta2 are set and a change-over switch part 223. The coefficients alpha1, alpha2, beta1, and beta2 regulate the band width of the PLL, and are switched corresponding to the switching of the band width. When the coefficient is switched, an electric charge control means 40 is varied corresponding to the degree of the band width to switch the accumulation quantity of the integral element. In such a way, the phase locked loop established once can be maintained extending over before and after the switching of the coefficient.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to provide a phase comparison means for a secondary phase-locked circuit (PLL), with the purpose of switching the bandwidth while maintaining phase synchronization in a short period of time. , a bandwidth switching type second-order phase-locked circuit using a second-order phase-locked loop consisting of a loop filter means including an integral element and having a first-order lag characteristic, and a voltage-controlled oscillation means including a first-order lag element, The coefficient defining the bandwidth of the loop filter means is switched according to the degree of the bandwidth to be switched, and the amount of accumulation of integral elements in the loop filter means is changed according to the bandwidth to be switched.

[Industrial application field]

The present invention relates to a secondary phase-locked circuit (CPLL), and in particular to a secondary PLL that can switch bandwidth for a short period of time while maintaining phase synchronization.

The secondary PLL of the present invention is suitable for changing the bandwidth, for example, when it is desired to change the band before and after synchronization pull-in when regenerating a carrier wave on the receiving side of a digital wireless satellite communication system. used.

[Conventional technology]

For example, in the case of a digital radio satellite communication system, when performing synchronous detection on the receiving side, noise must be removed from the received signal and the carrier wave (carrier) must be regenerated. For this carrier regeneration, a phase comparator 10' is used as shown in FIG.
, loop filter 20', voltage-controlled optical oscillator (VCO)
30' uses a secondary PLL connected in a closed loop.

The loop filter 20' includes an integrator 201 and a first coefficient unit 2.
04, is composed of a second coefficient multiplier 202 and an adder 203, and the coefficients of the first and second coefficient multipliers are α and β.

In a steady state, that is, in a state where phase synchronization is established by regenerating the carrier from the input received signal, the VCO 30
In order to oscillate ' at a frequency equal to the carrier, the control voltage of the VCO depends on the charge q stored in the integrator 201 of the loop filter 20', and the voltage in the integrator 201 is multiplied by coefficients α and β to control the VCO 30'. transmitted to.

Therefore, the coefficients α and β in the loop filter 20' determine the bandwidth BL of the loop filter, and the natural angular frequency ωn, the damping factor ζ, and the bandwidth B in the PLL.

The following relationship holds true between (for example, F, M.

'Phaselock Techn.'
iques”+ 2nd ed,).

ωn-ktfi ... (1) However, k, , is a constant.

The PLL shown in FIG. 6 also includes an integral element within the VCO 30', and an integrator 201 within the loop filter 20'.
Since it exhibits a second-order delay characteristic, it is called a second-order PLL.

In digital wireless satellite communications, there are parts of the received signal that are in the form of bursts, and carrier regeneration involves synchronizing the carrier during a limited number of symbols called the "preamble" at the beginning of the burst signal. Must. For this purpose, the bandwidth BL of the PLL must be widened. On the other hand, in order to suppress the jitter of the reproduced carrier and the frequency of cycle slips, the bandwidth Bt must be narrowed. In this way, shortening the synchronization pull-in time and reducing noise and stabilizing the steady state after the synchronization pull-in impose contradictory demands from the perspective of the PLL bandwidth BL. Therefore, it is necessary to change (switch) the bandwidth of the same PLL before and after synchronization pull-in.

[Problem to be solved by the invention]

As a device for switching the bandwidth, it is known to use a loop filter as a so-called "two-mode filter" and to switch the coefficients α and β. In equations (1) to (3) above, if the attenuation rate ζ is constant, for example, to widen the bandwidth BL, α and β are increased, and to narrow the bandwidth BL, α and β are decreased. do. However, career regeneration
When implementing the following PLL, there are problems described below.

The reference for the control voltage of the VCO in a steady state is the charge q accumulated in the integrator in the loop filter.
VCOOCOO antistatic 4B voltage is given by the V formula.

V0=α・β・q (4) What is clear from this is that even if the coefficients α and β are switched,
■ Constant control voltage. In order to maintain phase synchronization before and after switching, the charge q must also be changed accordingly. However, since the conventional two-mode filter simply switches the coefficients α and β, the phase synchronization that has already been established may be lost due to the switching. Therefore, switching from wideband to narrowband requires a considerable amount of time, especially when it takes time to establish phase synchronization again after switching.

Therefore, an object of the present invention is to provide a secondary PLL that can switch bandwidth stably and in a short time without causing synchronization.

[Means to solve the problem]

FIG. 1 shows the basic principle of the bandwidth-switchable secondary PLL of the present invention.

In the figure, the PLL includes a phase comparison means 10, a loop filter means 20, a voltage controlled oscillation means 30, and a loop filter means 2.
Charge control means 40 are provided which are connected to the integral element 21 within 0. The loop filter means 20 includes an integral element 21, a first coefficient switching means 24, an adding means 23, and a second coefficient switching means 24.
A coefficient switching means 22 is connected as shown. 1st
The coefficient switching means 24 each have a coefficient α1. Coefficient sections 241 and 242 where α2 is set and changeover switch section 24
It consists of 3. The second coefficient switching means 22 also includes coefficient sections 221 and 222 and a changeover switch section 223, in which coefficients β and β2 are respectively set.

Coefficient α0. α2. β1. βt is a parameter that defines the bandwidth of the PLL, and is switched by the changeover switch sections 243 and 223 in accordance with the switching of the bandwidth.

At the time of this coefficient switching, the charge control means 40 changes the accumulation amount of the integral element according to the degree (ratio) of the switching bandwidth.

[For production]

The coefficient corresponding to the wide bandwidth BLw is α1. β1, the coefficient corresponding to the narrow bandwidth BLN is α2. When β2 is assumed, the following relationship is assumed.

α1=a°α2...(5) β, -
b・β2...(6) However, a is a constant, all.

b is a constant, b>1°.If the accumulated charges of the integral element 21 in a steady state when the same frequency difference in both the bandwidths 13LW and 13LN is taken as qt+qz, the following relational expression holds true.

vo dry α1・β,・ql = α2・β2・q2 ...(7) qg =
a-b-q+ m (8) From the above, the charge control means 40 connected to the integrating means 21 has the coefficient α1.
After phase synchronization is established in wideband BLW by β, the coefficients α2. When switching to β2, the charge in the integral element 21 changes from ql to q! , that is, Q
Multiply t by (a・b), and in the opposite case, divide by (a−b) by q2.

As described above, the previously established phase synchronization is maintained before and after the coefficient switching.

The above switching can be performed in multiple stages (number of times). In this case, it is sufficient that the above-mentioned relationship is maintained between adjacent switches. Of course, only one of α or β may be switched.

〔Example〕

As an embodiment of the bandwidth-switchable secondary PLL of the present invention, referring to FIG.
R: Carrier Recover) circuit will be described.

In the figure, the phase comparison circuit 10a is the phase rotation circuit 11.
and a Costas type phase error detection circuit 12. The phase comparator circuit 10a has 79
4. After the MHz IF is dropped to baseband by quasi-synchronous detection and A/D converted. IIIPsK signal 1z
, Qt are applied, and the phase is rotated by the signal 1°Q from the VCO 30a, resulting in a 4-phase PSK demodulated signal (2). , Qo. The loop filter means and the charge control means 40 are shown as the filter means 20a, and include a delay section 211, an addition section 212.2' multiplication section 4111, a switch section 412, a delay section 21a, a multiplication section 25a, an addition section 23a,
The multiplier 26a, the first coefficient switching unit 243a, and the coefficient β3. First coefficient section 241 in which β2 is stored (set)
a, 242a, the second coefficient switching unit 223a, and the coefficient α1. Second coefficient section 221a in which α2 is stored
, 222a are constructed as shown. Delay section 21
5 and the addition section 212 are the integrating means 21 of the loop filter.
constitute a. Further, the 2'1 multiplier section 411 and the switch section 412 constitute charge control means 40a. VCO30a
is composed of a delay section 31, an addition section 32, a delay section 33, a cosine signal generation section 34, and a sine signal generation section 35. The addition section 32 and the delay section 33 constitute an integration section. The cosine signal generator 34 and the sine signal generator 35 generate orthogonal sine wave signals.
.

Output Q.

In the figure, the number of crossed lines indicates the number of bits in that part.

FIG. 3 shows the structure of the charge control means 40a, which consists of a 2'' multiplication section 411 and a switch section 412. This charge control means 40a is designed to multiply the accumulated charge q of the integrating means 21a by 2''. In digital signal processing, using a power of 2 is simply a bit shift, i.e.
This is because if n is positive, it is sufficient to shift to the upper digit, and if n is negative, it is sufficient to shift to the lower digit. Figure 3 illustrates the shifting concept. The solid line shows the normal state, and the broken line shows the state at the time of bandwidth switching. From equation (8), the case where n is positive means the case where the wide bandwidth is switched to the narrow bandwidth, and the case where n is negative means the opposite case. This circuit uses two's complement representation. In other words, when multiplying by 2″ (n・
Correct), add n “O”s after the LSB. That is, "0" is added to the lower n pinpoints of the data in the delay unit 215 and shifted to the upper n bits. A margin is set aside in the number of bits so that the upper bits are not lost due to this shift to the upper bits.

2'' times the charge control means 40a is the bandwidth switching degree BL.
No. (8) according to p/BLw or B tw/ B LN
This is done based on the constants (a - b) of the equation. However, in this embodiment, switching is performed by a power of two.

FIGS. 4(a) to 4(g) show operation timing diagrams of the circuit of FIG. 2. This circuit uses the clock CLK (Figure 4(a))
It is designed to operate at the rising edge of .

This operation example shows switching from wide band BLW to narrow bandwidth B. At time t1, a switching signal SW is output (FIG. 4(b)), and the switch section 243 in FIG.
a, 223a respectively change the coefficients from β1 to β2, α1
(Fig. 4(c))
, (d)). Further, the charge control means 40a also has a wide bandwidth BLW.
A multiplier of "2" is output according to the ratio of the narrow bandwidth B and the narrow bandwidth B (FIG. 4(e)).This multiplier is output every period of one operation clock. The charge q instantaneously changes from ql immediately before switching to Q+X2'', and phase synchronization is maintained even when the new loop bandwidth is reached after switching (FIG. 4(f)). Control voltage of VCO30a ■.

is compensated by multiplying the change in α1β by 2fi by ql, and Vo
= V, is kept constant before and after switching the bandwidth (Fig. 4 (g)
)), if such charges are not compensated for, then Fig. 4 (
f), q as shown by the dashed line in (g).

(2) Once the phase synchronization is lost, the phase synchronization is established again, and it takes a long time to establish the phase. Such a change causes a temporary loss of phase synchronization, and thereafter an asymptotically transition toward establishment of phase synchronization.

FIG. 5 shows the coefficient product α and β (horizontal axis) and the accumulated current r? in the integrating means when phase synchronization is established for a certain frequency. Actual measurement data regarding the relationship with FIq (I axis) is shown. FIG. 5 is a logarithmic scale. Carrier frequency f of human signal
c=IKHz, and the operating speed of the circuit is 66.5KHz. For example, α+=32°β, =80, so α1
・Charge q=55 (β1 point) when β, -2560,
α2 after switching = 8. β2=20, therefore α2・8g”1
60, the charge q#830 (β2 points). If,
If the coefficients are simply switched as in the conventional case, there is a large difference between the charge q=ss and Lq=830, and an out-of-synchronization occurs while the charge q shifts from 55 to 830. In this example, this charge q is expressed as (αl/α2)(
By multiplying β1/β, )-2''·2'' = 2', loss of synchronization is prevented. That is, as the coefficients α and β change, the charge q moves along the straight line in FIG. 5, thereby preventing period deviation.

In the above embodiment, the charge control means 40a changes the charge by a power of 2, but this multiplier (or divisor) can be set arbitrarily depending on the degree of bandwidth switching.

Further, in the above embodiment, the case of a four-phase PSK signal and a digital type has been described, but the present invention is not limited to this, and for example, a single-phase, CA
It can be applied to M signals and may be realized in an analog manner.

Furthermore, although the above embodiments have been described with reference to the case where the PLL is applied to carrier regeneration, it goes without saying that the PLL of the present invention can be applied to various circuits that switch bandwidth.

〔Effect of the invention〕

As described above, according to the present invention, the coefficients that define the bandwidth of the loop filter means are switched according to the switching of the bandwidth, and the accumulated charge of the integrating means in the loop filter means is also switched according to the switching of the bandwidth. By changing this, it is possible to realize a second-order PLL in which the bandwidth can be switched stably and in a short time without losing phase synchronization.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of a bandwidth switching type secondary phase-locked circuit according to the present invention, FIG. 2 is a diagram of a quasi-synchronous carrier regeneration circuit according to an embodiment of the present invention, and FIG. 3 is a charge control means in FIG. 2. 4(a) to (g) are operation timing diagrams of the circuit in Figure 2, Figure 5 is a diagram showing the characteristics of the circuit in Figure 2, and Figure 6 is a conventional 2nd-order PLL circuit diagram. , (Explanation of symbols) 10... Phase comparison means, 20... Loop filter means, 22, 24... Coefficient switching means, 40... Charge control means. 21... Integral element, 3O-VCO. It is.

Claims (1)

[Claims] 1, including phase comparison means (10) and integral element (21);
A bandwidth switching type second-order phase-locked circuit using a second-order phase-locked loop consisting of a loop filter means (20) having a first-order lag characteristic and a voltage-controlled oscillation means (30) including a first-order lag element, The coefficients (α_1, α_2; β_1, β_2) that define the bandwidth of the loop filter means are switched according to the degree of the bandwidth, and the amount of accumulation of integral elements in the loop filter means is switched according to the bandwidth. A bandwidth switching type secondary phase synchronization circuit characterized in that the bandwidth is changed.