JPH04360274A - Automatic formation processing system for area pattern - Google Patents

Abstract

PURPOSE:To remove the warp of a printed substrate or the ununiformity of etching by providing this automatic formation processing system with a partial area dividing step for dividing the wired area of the printed substrate, a pattern density comparing step, a pattern density adjusting step, and so on. CONSTITUTION:The partial area dividing step 1 divides the wired area of the printed substrate into plural partial areas and a pattern density calculating step 2 finds out the pattern density of each partial area. The pattern density comparing step 3 compares the found pattern density values of respective partial areas and an area pattern forming step 4 forms the area pattern of an optional net in a partial area whose pattern density is low. The pattern density adjusting means 5 adjusts the density of the formed area pattern. Consequently the pattern density of the printed substrate can be uniformed, the warp of the printed substrate or the ununiformity of etching can be removed and noise can be reduced.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a method for generating area patterns in the automatic design of printed circuit boards, and in particular to a method for automatically inputting area patterns for power, ground, etc. into empty areas of arbitrary layers on a board. The present invention relates to an area pattern automatic generation processing method.

[0002] With the recent demand for high-density packaging,
Circuits based on different technologies are often mounted on the same printed circuit board, and as a result, pattern densities may vary in different parts of the printed circuit board. For example, the wiring pattern density is generally high in a portion where a surface mount device (SMD) is mounted, but the wiring pattern density is not so high in a portion where other components are mounted.

[0003] When the wiring pattern densities differ on the same printed board as described above, problems such as warping of the printed board and uneven etching are likely to occur.

On the other hand, when automatically designing printed circuit boards, area patterns are generated in vacant areas on the printed circuit board to make the wiring pattern density uniform, thereby solving the above-mentioned problems. An automatic generation processing method is desired.

[0005]

2. Description of the Related Art Conventionally, differences in wiring pattern densities on printed circuit boards have often not been particularly considered. In some cases, a method is also used in which a dummy pattern without a net, that is, is not connected to anything, is input by searching for an empty area.

[0006]

[Problem to be Solved by the Invention] However, when the wiring pattern density on the printed circuit board is different,
There is a problem in that the printed board is likely to warp. Further, when the wiring pattern densities are different, there is a problem that over-etching occurs in areas where the pattern density is low, and under-etching occurs in areas where the pattern density is high, resulting in non-uniform etching.

On the other hand, the method of providing a dummy pattern without a net in an empty area has a problem in that noise may increase based on this pattern.

[0008] The present invention aims to solve the above-mentioned problems of the prior art, and by automatically generating area patterns on a printed circuit board for which pattern design has been completed, the pattern density of each part can be made uniform. In addition to eliminating warping of printed circuit boards and non-uniform etching, by using the automatically generated area pattern as a ground net or power net, noise is reduced and characteristics are improved compared to the case of conventional dummy patterns. can,
The purpose is to provide a region pattern automatic generation processing method.

[0009]

[Means for Solving the Problems] The present invention is a method for automatically generating an arbitrary net area pattern on a printed circuit board having elements such as lands, area patterns, wiring lines, wiring vias, etc. of components placed on the board. , a partial area dividing step in which the wiring area of a printed circuit board is divided into a plurality of partial areas, a pattern density calculation step in which the pattern density in each partial area is calculated, and a pattern density comparison step in which the pattern densities of the calculated pattern densities in each partial area are compared. a region pattern generation step of generating a region pattern of a designated net in a partial region with a low pattern density, and a pattern density adjustment step of adjusting the density of the generated region pattern. .

The present invention also provides that the above-mentioned area pattern generation step searches for an empty area within a partial area with low pattern density using the component land or wiring via of the specified net as a base point. This method is characterized in that the process of generating an area pattern in this empty area is executed by repeating the process for the number of component lands and wiring vias of the specified net until a specified pattern density is reached.

Furthermore, the present invention provides that the above-mentioned region pattern generation step is performed in a partial region with a low pattern density.
Using the wiring line of the specified net as a base point, the process of generating an area pattern within this area by searching for an empty area or an area where the width of the wiring line is widened within this partial area is performed for the number of wiring lines of the specified net. , is characterized in that it is executed by repeating it until a prescribed pattern density is reached.

0012

[Operation] FIG. 1 shows the basic structure of the present invention. In the area pattern automatic generation processing method of the present invention, in the partial area division step 1, the wiring area of the printed board is divided into a plurality of partial areas, and in the pattern density calculation step 2, the pattern density in each partial area is calculated, and the pattern In the density comparison step 3, the pattern densities of the obtained partial regions are compared, and in the region pattern generation step 4, an arbitrary net region pattern is generated within the partial region with low pattern density, and in the pattern density adjustment step 5. Since the density of the generated area pattern is adjusted, the pattern density of the printed board can be made uniform to eliminate warping of the printed board and uneven etching, and the automatically generated area pattern can be used as an earth net or power net. By doing so, it is possible to reduce noise and improve characteristics.

The automatic region pattern generation processing method of the present invention will be explained in detail below at each stage.

In partial area division step 1, the wiring area (rectangular or arbitrary polygon) of the printed board is divided into a plurality of partial areas according to a predetermined dividing method. For example, dividing into 2 equal parts, 3 equal parts, 4 equal parts, 6 equal parts, etc.
There are equal parts, 8 parts, etc. When dividing, the area of each partial region is usually made equal.

FIG. 2 shows an example of a method of dividing a wiring region into partial regions, and (a) shows the case of dividing the wiring region into two equal parts.
(b) is divided into three equal parts, (c) is divided into four equal parts, (
d) shows the case of 6 equal parts.

In the pattern density calculation step 2, the pattern density of each partial region determined in the partial region division step 1 is determined.

FIG. 3 is a flowchart showing the procedure for calculating pattern density. As shown in FIG. 3, after determining the area of the partial region (S1), the total area of the wiring pattern in each partial region, that is, the sum of the areas of component lands, lines, vias, and area patterns, is determined (S2). By dividing this by the area of the partial region (S3), the pattern density [%] is calculated.

In the pattern density comparison step 3, the pattern densities of the respective partial regions obtained in the pattern density calculation step 2 are compared to determine in which partial region the region pattern is to be generated. Usually, area patterns are generated in other partial areas so that the pattern density is the same as that of the partial area with the highest density.

FIG. 4 is a flowchart showing the procedure for pattern density comparison. As shown in FIG. 4, the comparison of the pattern densities of the partial regions is performed by determining the maximum value of the pattern density in each partial region (S11), and then determining how much area should be added to the partial region other than the partial region with the maximum pattern density. This is done by calculating whether to add a region pattern for each partial region (S12).

In the area pattern generation step 4, an area pattern is generated within the low density partial area determined in the pattern density comparison step 3. The area pattern is generated using a known area pattern generation method.

FIG. 5 shows a method of generating an area pattern, and shows a conventional method of obtaining an area pattern by graphical operations. That is, the partial area 11 is used as the area pattern input area of the specified net, and the elements 12 (lines, lands, vias, area patterns,
The area pattern 14 is obtained by determining the difference between the pattern input prohibited area) and the figure 13 which is enlarged by the electrically required clearance.

FIG. 6 is a flowchart showing the procedure for generating an area pattern. That is, the area pattern is generated by repeating the process of generating the area pattern of the specified net using the known technique as described above in the empty area in the low-density partial area by the number of low-density partial areas.

In the pattern density adjustment step 5, the density of the region pattern generated in the region pattern generation step 4 is adjusted for each partial region. In other words, if you calculate the pattern density after generating an area pattern within a partial area, the target pattern density may be exceeded, so in this case, calculate the minimum rectangle that includes the generated area pattern. , the reduction process is performed in order of decreasing area.

FIG. 7 shows an example of the area pattern reduction process, in which (a) shows the area pattern before the reduction process, the hatched area represents the area pattern, and the dotted line represents the minimum rectangle surrounding this area pattern. It shows. (b) shows the reduction process, and the solid lines ■ to ■ indicate that the area pattern is reduced by deleting the area pattern outside this line. (c) shows the area pattern after reduction processing.

In this case, a range that can be reduced with one area pattern is determined, and if the range is exceeded and there are multiple area patterns, reduction processing is performed on other area patterns.

FIGS. 8 and 9 are diagrams showing the first half and the second half of a flowchart showing the pattern density adjustment procedure. As shown in both figures, the number of area patterns generated in a low-density partial area, the area of each area, and the total area are calculated (S31), and the pattern area after area pattern generation is the pattern of the area with the maximum density. If it is larger than the area (S32)
If there are multiple generated area patterns (S33), they are sorted in descending order of area (S34), and the area pattern with the largest area is targeted for processing (S35). Next, find the minimum rectangle that includes the area pattern (S37), and, assuming that the area pattern is cut by the specified unit length from the top, bottom, left, and right, check the direction in which the area to be deleted from each direction is the minimum. (S37). When the number of generated regions exceeds the reducible range of one region pattern (S38), the region pattern with the next largest area is processed (S39). Such processing is repeated until the reduced pattern area becomes smaller than the pattern area of the maximum density region (S40), and ends when the number of low density partial regions has been processed (S41).

[0027]

Embodiment FIGS. 10 to 15 show an embodiment of the method of the present invention, in which a simple model is used to generate an area pattern using the above-mentioned graphic operation method.

FIG. 10 shows an example of how a printed circuit board is divided according to an embodiment of the present invention, and one partial area when divided into four is shown by a thick solid line.

FIG. 11 shows an example of partial areas in one embodiment of the present invention. The wiring density is calculated for each such partial region. As described above, the wiring density is calculated by dividing the total area of the land, line, via, and region pattern by the area of the partial region. In the figure, □, ■ are lands for connecting and installing parts, ○
, ● indicate vias (relay holes) for interlayer connection, ● and ■ indicate specified nets, and ○ and □ indicate nets other than the specified nets. Here, the designated net indicates a portion at the same potential (designated potential). Further, solid lines indicate lines (wiring).

FIG. 12 shows the generation of area patterns in one embodiment of the present invention. In the figure, hatched portions 21, 22, 23, and 24 indicate generated area patterns. Comparison of pattern densities is performed for each partial region whose region pattern has been generated in this manner.

FIG. 13 shows deletion of an isolated area pattern in one embodiment of the present invention. If the calculated wiring density exceeds the target wiring density, the isolated area pattern that cannot be connected to the specified net is deleted. In this case, it is necessary to calculate and compare the wiring density each time a region pattern is deleted. In Figure 13, Figure 1
It is shown that the area patterns 23 and 24 shown in No. 2 have been deleted.

FIG. 14 shows area reduction processing in one embodiment of the present invention. The largest area pattern 21 of the area patterns in FIG. 13 with isolated patterns removed
, the minimum rectangle is found as shown by the dotted line in FIG. 14, and within this rectangle, certain values are deleted from the outside of the rectangle as shown by ■ to ■. Delete 4 up, down, left, and right
Start from the opposite direction and gradually scrape inward. FIG. 14 shows a case where control is performed so that the areas to be deleted are arranged in descending order.

FIG. 15 shows a region pattern after region reduction processing according to an embodiment of the present invention.
) is the area pattern after deletion processing of ■ in Fig. 14,
(b) shows the area pattern after the deletion process of ■ in FIG. 14, and (b) shows the area pattern after the deletion process of ■ in FIG. 14, respectively.

When deleting such a region pattern, control is performed so that the region pattern is not isolated from elements of the same net. However, lines of the same net as the designated net may be included in the area.

FIGS. 16 to 19 show another embodiment of the method of the present invention, in which an area pattern is created by searching for an empty area using a component land or via of a specified net in a partial area as a base point. This shows a case in which the generation of isolated patterns is prevented by generating them.

FIG. 16 shows an example of partial areas in another embodiment of the present invention. For each such partial area, the wiring density is calculated as described above. In the figure, 31 indicated by a star indicates a land or via of interest of the designated net.

FIG. 17 shows the generation of area patterns. In this case, start the search from the land or via 31 of interest, consider the boundary of the partial area or other nets as obstacles, and when you come across this, move 90 degrees in the specified direction.
An empty area is searched for by repeating the process of performing a search with 0° rotation, and an area pattern is generated in the searched empty area. In this case, when an obstacle is encountered, control is performed so that the search is performed along the obstacle, and a certain clearance from the obstacle is provided around the obstacle. Lands and vias of the same net are usually treated like obstacles, but lines of the same net are not considered obstacles. When lands or vias of other nets are included in the formed area pattern, a punching process is performed to set a clearance around the lands or vias. In this way, a region pattern 32 shown with diagonal lines is generated.

FIG. 18 shows the generation of another area pattern in another embodiment of the present invention. In this case, an area pattern 34 shown with diagonal lines is generated by searching from the noted land or via 33 of the designated net indicated by ★ while avoiding other nets by regarding them as obstacles. In this case, if there is an already generated area pattern, the search is not performed in the direction connected to this area pattern.

FIG. 19 shows the end of the search for all area patterns in another embodiment of the present invention, and shows that area patterns 32 and 34 have been generated. For information on how to generate such area patterns, see
Patent application No. 61-255172 (Unexamined patent application No. 63-108466)
), Japanese Patent Application No. 62-49188 (Japanese Patent Application No. 63-21617)
6) is described in detail.

FIGS. 20 to 24 show still another embodiment of the method of the present invention, in which an area pattern is generated by searching for an empty area using the designated net line in the divided area as a base point. It shows the case.

FIG. 20 shows an example of partial areas in still another embodiment of the present invention. For each such partial area, the wiring density is calculated as described above. In the figure, solid lines 41 and 42 indicate designated net lines.

FIG. 21 shows the generation of an area pattern in still another embodiment of the present invention, in which an area pattern 43 is created by searching for an empty area from lines 41 and 42 in the same manner as described above. has been shown to generate. In this example, the calculation result of the wiring density of the partial area exceeds the target wiring density, so it is necessary to delete the area pattern.

FIG. 22 shows another example of partial areas in still another embodiment of the present invention. In this case, the wiring density is high and the method of generating an area pattern in a vacant area as described above cannot be used, so the area pattern is generated by widening the line width of the designated net.

FIG. 23 shows generation of area patterns in still another embodiment of the present invention, and FIG.
The line 44 of the specified net in the partial region shown in
It is shown that the width of 45 is widened to generate area patterns 46 and 47. In this case, the target wiring density is not exceeded.

FIG. 24 shows another example of region pattern generation in still another embodiment of the present invention. This case shows a case where the generation of the area pattern is limited to the area around the line. In the figure, area patterns 48, 4
9 shows an area pattern generated exclusively around the lines 44 and 45 of the designated net. In this case as well, the target wiring density is not exceeded.

[0046]

[Effects of the Invention] As explained above, according to the present invention, when inputting area patterns for power, ground, etc. to any layer on a printed circuit board, the pattern density is almost uniform for each divided partial area. Therefore, it is possible to eliminate warping of the printed board and non-uniformity of etching, thereby improving print quality and yield, as well as reducing noise.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention.

FIG. 2 is a diagram illustrating a method of dividing a wiring area into partial areas, in which (a) is a case where the area is divided into two equal parts, (b) is a case where it is divided into three equal parts, and (c) is a case where it is divided into four equal parts. , (d) respectively show the case of 6 equal divisions.

FIG. 3 is a diagram showing a procedure for pattern density calculation using a flowchart.

FIG. 4 is a diagram showing a procedure for pattern density comparison using a flowchart.

FIG. 5 is a diagram illustrating a region pattern generation method.

FIG. 6 is a diagram illustrating a procedure for region pattern generation using a flowchart.

FIG. 7 is a diagram illustrating area pattern reduction processing, in which (a) shows the area pattern before reduction processing, and (b)
) shows the reduction process, and (c) shows the area pattern after the reduction process.

FIG. 8 is a diagram showing the first half of a flowchart showing a procedure for adjusting pattern density.

FIG. 9 is a diagram showing the second half of a flowchart showing a procedure for adjusting pattern density.

FIG. 10 is a diagram showing division of a printed board in an embodiment of the present invention.

FIG. 11 is a diagram showing an example of a partial area in an embodiment of the present invention.

FIG. 12 is a diagram illustrating generation of area patterns in one embodiment of the present invention.

FIG. 13 is a diagram illustrating deletion of an isolated area pattern in an embodiment of the present invention.

FIG. 14 is a diagram showing area reduction processing in an embodiment of the present invention.

FIG. 15 is a diagram showing a region pattern after region reduction processing in an embodiment of the present invention.

FIG. 16 is a diagram showing an example of a partial area in another embodiment of the present invention.

FIG. 17 is a diagram showing generation of area patterns in another embodiment of the present invention.

FIG. 18 is a diagram illustrating generation of another area pattern in another embodiment of the present invention.

FIG. 19 is a diagram showing the end of searching all area patterns in another embodiment of the present invention.

FIG. 20 is a diagram showing an example of a partial area in still another embodiment of the present invention.

FIG. 21 is a diagram showing generation of area patterns in still another embodiment of the present invention.

FIG. 22 is a diagram showing another example of a partial area in still another embodiment of the present invention.

FIG. 23 is a diagram showing generation of area patterns in still another embodiment of the present invention.

FIG. 24 is a diagram showing another example of region pattern generation in still another embodiment of the present invention.

[Explanation of symbols]

1 Partial region division step 2 Pattern density calculation stage 3 Pattern density comparison stage 4 Area pattern generation stage 5　Pattern density adjustment stage

Claims (3)

[Claims] Claim 1: A method for automatically generating an arbitrary net area pattern on a printed circuit board having elements such as lands, area patterns, wiring lines, wiring vias, etc. of components placed on the board. A partial area dividing step (1) of dividing the partial area into a plurality of partial areas, and a pattern density calculation step (1) of calculating the pattern density in each partial area.
2), a pattern density comparison step (3) of comparing the pattern densities of each of the obtained partial regions, and a region pattern generation step (4) of generating a designated net region pattern in the partial region with low pattern density. , a pattern density adjustment step (5) of adjusting the density of the generated area pattern. 2. The area pattern generation step (4) comprises:
In a partial area with low pattern density, a process of generating an area pattern in the empty area by searching for an empty area in the partial area using the component land or wiring via of the specified net as a base point is performed. 2. The area pattern automatic generation processing method according to claim 1, wherein the area pattern automatic generation processing method is executed by repeating the process for the number of wiring vias until a predetermined pattern density is reached. 3. The area pattern generation step (4) comprises:
A process of generating an area pattern within a partial area with low pattern density by searching for an empty area within the partial area or an area where the width of the wiring line is widened using the wiring line of the specified net as a base point. 2. The area pattern automatic generation processing method according to claim 1, wherein the area pattern automatic generation processing method is executed by repeating the process for the number of wiring lines of the designated net until a prescribed pattern density is reached.