JPH0863515A - Layout design method for integrated circuit - Google Patents

Abstract

PURPOSE: To take precedence over the area of a whole chip compared to the area of a block and to optimize the chip area by controlling the quantity of a longitudinal direction wiring in a standard cell block and minutely controlling the longitudinal lateral sizes of the block. CONSTITUTION: A standard cell 15 being a hierarchy lower than the block becoming a candidate is re-laid out after the block being the candidate is selected. When a wasteful area exists in a horizontal direction, laying out with many wirings in the vertical directions is executed. Namely, many field through cells 17 are inserted by enlarging the weight of the wiring in a horizontal direction in a target function at the time of an automatic wiring processing, and the respective cells are used as much as possible at the time of wiring. When the wasteful area exists in the vertical direction, the number of the stages of cell strings is left as it is from similar consideration Laying out with few field through cells is executed and laying out with many field through cells is executed by increasing one stage of the cell string. Then, laying out with better result is adopted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout designing method for an integrated circuit, and particularly to reduce the area of the entire chip in a hierarchical layout of a standard cell type LSI, and to a standard cell block (hereinafter also simply referred to as a block). The present invention relates to a design method for finely controlling the vertical and horizontal sizes of blocks in the automatic placement and routing process in ().

[0002]

2. Description of the Related Art In a large-scale layout design of a standard cell type LSI, a hierarchical layout design in which data is divided into partial circuits (blocks) and replaced with a hierarchical data structure and a layout is performed for each hierarchical layer is mainstream. ing. The procedure of the hierarchical layout design is that after generating layout data with a hierarchical structure, the area of each block is estimated, the block layout is roughly determined, and the number of standard cells in the block is determined in the upper hierarchy. The standard cell automatic placement and routing process is performed in the lower layer, and then the blocks are routed in the upper layer. However, the shape of each block after layout is
Since this is different from the initial estimate, useless areas are often scattered in the area of the entire chip. Therefore, it is necessary to properly set the aspect ratio of each block in order to further reduce the area of the entire chip. Since the aspect ratio of the standard cell block can be controlled by changing the number of cell columns, the optimization process of the number of cell columns, that is, changing the number of cell columns and laying out the inside of the block again, and repeating it Small areas,
The chip area can be reduced.

[0003]

In the conventional method, in order to change the shape of the block, the number of cell rows in the block is changed and the layout is rearranged to control the aspect ratio of the block. However, rough control is possible only by changing the number of cell rows.

The present invention can perform finer control of the block aspect ratio than the conventional method of optimizing the number of cell column stages, thereby making it possible to further reduce the area of the entire chip in an integrated circuit. It is intended to provide a layout design method.

[0005]

The present invention is a method for controlling the vertical and horizontal sizes of a standard cell block in order to achieve the above-mentioned object. Is applied. This is to check if there is a dead area in the vertical and horizontal directions for each block from the result of the upper layer of the layout data after the optimization of the number of cell columns obtained by the conventional method, and if there is a dead area. Calculates the area width, selects a standard cell block that has no dead area in one of the vertical and horizontal directions and has a dead area in the other, and the standard cell block from the value of the dead area width. In the automatic block layout process, the process of inserting the feed-through cell and controlling the objective function to re-execute the layout process of the block is performed again, and these processes are performed to improve the overall chip area. It is characterized by repeating until it disappears.

[0006]

[Function] The standard cell wiring is composed of vertical and horizontal wiring elements. When the vertical wiring is used a lot, the horizontal wiring is reduced, and when the vertical wiring is reduced, the horizontal wiring is increased. There is a property. That is, if there are many vertical wirings, many feed-through cells for passing the wirings between the cells are required, and as a result, the horizontal block size becomes large as shown in FIG. 4B. If there are many wirings in the horizontal direction, the channel (wiring region) width increases and the block size in the vertical direction increases, as shown in FIG. For this reason, usually, optimum feedthrough cells are inserted so that vertical and horizontal line segments are balanced and placement and wiring are performed so as to minimize the block area, and an efficient wiring result is obtained. However, even if the area of the block is minimized, the area of the entire chip is not always minimized. In the present invention, the size of the block is controlled by intentionally increasing or decreasing the number of wirings in the vertical direction in consideration of the waste area of the entire chip, thereby facilitating the optimization of the chip area.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is realized as a part of a function of a design support apparatus using an electronic computer and is executed by the processing procedure shown in FIG. First, in step 1, the layout data after the optimization of the number of cell row stages obtained by the conventional method is loaded, and st
In ep2, the required channel width is calculated from the main line data in each channel (wiring area) 11, two constraint graphs in the horizontal direction and the vertical direction are created from these values and the block size, and the critical path (longest route) and its Find the length. Here, the graph node represents a block, and represents the adjacency relation of the graph edge block. The length of the graph edge is the minimum required distance between two block centers calculated from the block size and the channel width. The length of the critical path corresponds to the size of this layout data. Then, for each node, the difference between the path length passing through the node and the critical path length is set as the dead area 13 width in that direction of the block corresponding to that node, and the waste in both the horizontal and vertical directions for all blocks is set. Calculate the area width.

For example, in the example of FIG. 2, FIG. 3 is a constraint graph in each direction, and the solid line is the critical path.
Where the vertical constraint graph critical path (bott
The difference between the length of (om)-(C)-(A)-(top) and the length of the path (bottom)-(C)-(B)-(top) passing through (B) is wv1 and is horizontal. Path (left)-(C)-(right) and path (left) -of the constraint graph of
The difference between the path lengths of (A)-(B)-(right) is wh1. Since the block A is on the critical path in the vertical direction, the dead area width is 0, and the horizontal dead area width is wh1. Block B has a vertical direction wv1 and a horizontal direction wh1, and both blocks C have a value of 0.

Next, in step 3, a standard cell block, one of which is on the critical path and the waste area 13 of which is on the other, is selected. If it does not exist, the process ends, and if it exists, one block is selected in step 4. In the example of FIG. 2, only block A is selected.

After the candidate block is selected, the layout of the standard cell 15 which is the lower hierarchy is re-executed. At this time, there are two possible cases, namely, the case where the waste area is in the horizontal direction and the case where it is in the vertical direction. First, when there is a waste area in the horizontal direction, a layout with many wirings in the vertical direction is performed. That is, by increasing the weight of the horizontal wiring in the objective function during the automatic placement processing, many feedthrough cells 17 are inserted, and these are used as much as possible during the wiring. However, the increase of the cell column length due to the insertion of the feedthrough cell 17 is limited so as not to exceed the dead area width. As a result, the number of line segments in the horizontal direction is reduced as shown in FIG. 4B, and the channel width is reduced. As a whole, the block size in the horizontal direction becomes smaller as shown in FIG. 5B, and the chip size also becomes smaller. However, if the original layout already used enough feedthrough cells, this method alone would not be fully effective. Therefore, the number of cell columns is reduced by one and the weight in the vertical direction is increased to reduce the number of feedthrough cells. And adopt the one with the best results.

Next, when there is a dead area in the vertical direction,
From the same idea, the layout with the same number of cell columns and a small number of feedthrough cells (FIG. 4A, FIG.
As shown in (a)), the number of cell columns is increased by one, and a layout with a large number of feed-through cells is performed and the one with a better result is adopted. By repeating these processes, the block size adjustment can be controlled more finely than the conventional method, and as a result, the chip area can be further reduced.

[0012]

According to the present invention, by controlling the amount of vertical wiring in a standard cell block to finely control the vertical and horizontal sizes of the blocks affected by them, the area of the entire chip rather than the area of the block can be controlled. It becomes easy to optimize the chip area by giving priority to.

[Brief description of drawings]

FIG. 1 is a flowchart illustrating an embodiment of the present invention.

FIG. 2 is a layout diagram of an upper layer of a standard cell block type LSI for explaining an embodiment of the present invention.

FIG. 3 is a constraint graph illustrating an example of the present invention.

FIG. 4 is an explanatory diagram illustrating wiring of an A block according to the embodiment of this invention.

FIG. 5 is a layout diagram of one block of a standard cell block type LSI for explaining an embodiment of the present invention.

[Explanation of symbols]

 11 Wiring area 13 Waste area 15 Standard cell 17 Feedthrough

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location W

Claims (1)

[Claims] 1. A standard cell block is arranged in a method for controlling the size of the standard cell block at the time of re-layout in automatic placement and routing processing in the standard cell block in a hierarchical layout design of a standard cell LSI. Based on the layout result of the upper hierarchy, whether or not there is a dead area in the vertical and horizontal directions for each standard cell block, and if there is a dead area in that direction, calculate the area width, and In the process of selecting a standard cell block that has no dead area in one of the horizontal and horizontal directions and a dead area in the other, and the value of the dead area width, the feedthrough cell in the automatic placement and routing process of the standard cell block is selected. Insertion process and control of the objective function And a step of re-executing the layout process of the standard cell block, and repeating these steps until there is no room for improvement of the entire chip area.