JPH06124322A - Wiring method for equal-length specified network - Google Patents

Abstract

PURPOSE:To reduce influence on a via hole which is already designed and other wiring patterns, and to suppress radiation noises and reduce the distortion of a signal waveform when the equal-length specified network which is already designed and wired is equalized in length as to the wiring method for the equal- length specified network of a wiring pattern which is wired on a printed circuit board. CONSTITUTION:This wiring method for the equal-length specified network nearly equalizes signal delay times between plural equal-length series which are already designed in terms of the length of wiring, etc.; and equal-length series which are shorter in wiring length than the longest equal-length series among plural equal-length series which are already designed are divided into orthogonal X-directional and Y-directional layers, and wirings (a) and (b) which are arranged between the start points and end points of the equal length series by the X-directional layer and Y-directional layer are folded and extended for by-passing once from at least one point to outside the prolongations connecting the start points and end points, so that the electric conductors become nearly equal in wiring length.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for wiring an isometric designated net to be wired on a printed circuit board, and more particularly to a method for correcting an already laid out isometric designated net.

The equal-length designation net on the circuit is, for example, a designation to make the signal delay time of the sequence A from the component terminal A1 to the component terminal A2 and the sequence B from the other component terminal B1 to the component terminal B2 the same. When the layout of the wiring pattern is designed, the signal delay time is converted into the wiring having the same line width and the number of via holes, and the wiring lengths of both are made substantially the same.

In the equal-length designating technique, the wiring having the longer theoretical length of the series A and B is first wired in the conventional layout method, and then the wiring length is calculated, and then the shorter theoretical length has the same length. There is a method of laying out the same designating net, and a method of post-processing after modifying the layout of all nets having the same length, and modifying the shorter designed wiring length so that the wiring length becomes almost the same.

As a tendency in recent years, the amount of circuit functions to be packed in a printed circuit board is bloated, so that adjustment of the equal-length designated series must be solved in parallel with accommodation of the entire wiring pattern. ing. Also, from the wiring condition side, specify a wiring grid that divides the basic grid (2.5 mm intervals) into 3 to 8 and set the via hole generation grid only on the basic grid intersections or the grid intersections at 1.27mm intervals. The specified wiring specifications are the mainstream. Under these conditions, if the wiring pattern length of the equal-length designated series is adjusted without considering the wiring accommodability of other series as in the conventional method, it is possible to crush the position where via holes can be generated in other general series wiring. A via hole neck or a wiring channel neck due to the crushing of the pattern wiring grid is generated, and many lines cannot be completely wired. In addition, if the detour is performed in a blind manner, the number of right-angled bending points is increased, radiation noise is increased, and the signal waveform is disturbed.

In view of the situation as described above, when the layout of all the equal-length designated nets is designed and the adjustment of the equal-length designated series is performed, there is little influence on the designed via holes and other wiring patterns, and the radiation noise is suppressed. It is desired to reduce the distortion of the signal waveform.

[0006]

2. Description of the Related Art FIGS. 13 (a), 13 (b) and 13 (c) are wiring diagrams for explaining a conventional method for wiring an equal-length designated net.

FIG. 13 (a) shows an equal length designation net, and the equal length series A and B of the designed wiring are from the start point A1 to the end point A, respectively.
2 and wirings a and b from the start point B1 to the end point B2 are shown. The multilayer printed circuit board is formed by dividing each wiring layer into an X-direction layer and a Y-direction layer which are orthogonal to each other, and the wiring is usually arranged on a grid line having an interval of 2.54 mm or 1.27 mm. The starting point and the ending point of the equal-length series A and B are component terminals and via holes.

FIG. 13 shows wiring in the X direction layer. As shown, the series A has a longer wiring length than the series B. In this case, in order to make the wiring length the same, the wiring length of the series B is corrected with reference to the wiring length of the series A.

As shown in the modified wiring diagram of FIG. 13 (b),
Extend the wiring route around the line connecting the start point B1 and the end point B2 in zigzag in the direction of the line, or zigzag in the direction perpendicular to the line direction as shown in the corrected wiring diagram of Fig. 13 (c). The wiring length is made almost the same as that of the series A by performing detour extension.

In addition to the X-direction layer, the Y-direction layer is similarly corrected for the wiring length. When connecting to another layer in the Y direction, a via hole provided on the intersection of the lattice lines is used for relay connection.

[0011]

However, according to the above wiring method, the points of interest are detoured in a zigzag manner as shown in FIGS. 13 (b) and 13 (c). Since there are many opportunities to interfere with other designed via holes and wiring patterns, it is necessary to crush these designed via holes and wiring patterns and move them to other places, and since there are many bending points in the wiring patterns, radiation noise and signals There is a problem that the waveform is distorted and other influences are large.

In view of the above problems, the present invention has a small influence on a designed via hole and other wiring patterns when the equal length designation net of the designed wiring is made equal, and suppresses the radiation noise to suppress the signal waveform. It is an object of the present invention to provide a wiring method for an equal-length designated net that can reduce the distortion of the.

[0013]

In order to achieve the above object, in the wiring method of the equal length designation net of the present invention, the signal delay time between a plurality of predesigned equal length sequences is converted into the wiring length or the like. In the wiring method for equal-length designated nets, the equal-length series having a short wiring length among the plurality of previously designed equal-length sequences are orthogonalized in the X-direction layer. , The Y-direction layer, and the wiring disposed between the start point and the end point of the isometric sequence for each of the X-direction layer and the Y-direction layer, from at least one point to the outside on the extension line connecting the start point and the end point. It is configured to have almost the same wiring length by performing detour extension and wiring by turning back once.

[0014]

In this way, an equal length series with a short wiring length is connected to the start point ~
By performing detour extension from at least one point to the outside on the extension line connecting the end points by detouring extension and wiring, the interference with the already designed via hole and other wiring patterns is reduced compared to the conventional correction method, The via hole neck and the wiring channel neck can be suppressed as much as possible, and since the right-angled bending points of the wiring pattern are reduced, it is possible to suppress the radiation noise and the disturbance of the signal waveform in terms of electrical conditions.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The gist of the present invention will be described in detail below with reference to the embodiments shown in the drawings. 1 (a), 1 (b) and 1 (c) are wiring diagrams for explaining the wiring method of the equal length designation net according to the present invention, and FIG. 2 is a delay time conversion diagram used for the correction.

The wiring method of the equal-length designated nets in which the signal delay time between a plurality of pre-designed equal-length sequences is converted into the wiring length or the like to be almost the same is shown in FIG. 1 (a). Of a series A of starting points A1 to A2, that is, a wiring a and a series B of starting points B1 to B2, that is, a wiring b, which are predesigned isometric sequences of
Series B with the shortest wiring length based on the series A with the longest wiring length
1 is divided into an X-direction layer and a Y-direction layer which are orthogonal to each other (if the wiring is in one of the unidirectional layers without straddling the X-direction layer and the Y-direction layer, the wiring is corrected in that layer). b) As shown in the figure, first, for example, the start point B of the series B having a short wiring length in the X-direction layer
The wiring between the end point B1 and the end point B2 is extended from B2 to the one outside on the extension line connecting B1 to B2, and when the extension exceeds the limit length as shown in FIG. Only one turn is required.) The line is extended from B1 to the other outside on the extension line connecting B1 to B2, and is connected to B1 again by only one turn so that the wiring lengths are almost the same.

The starting point and the ending point are the component terminals 1 (or via holes), and when the wiring connecting them extends over multiple layers such as the X-direction layer and the Y-direction layer, there is little effect on other wiring and via holes. To consider. The wiring shape of Fig. 1 (b) is less likely to cause a wiring channel neck, and
In the wiring shape, the wiring channel neck and the via hole neck are less likely to occur.

The adjustment of the equal length designated series is performed by an automatic correction processing program using an electronic computer system. The conditions (information) necessary for this correction are as follows. Difference between the longest series and the line length conversion (according to the delay time conversion diagram of FIG. 2) is L ₀ , the radius of the via hole is Vr, and half of the line width is P.
r ₀ , the gap between the wires of the same series is d1, and the gap between the wires of the same series and the component terminal (or via hole) is d
2. Let PL be the allowable distance in the parallel section of the wiring, ΔL be the allowable error range for delay time correction, and Ln be the designed wiring length to be corrected.

FIG. 3 shows a pre-designed wiring diagram which is modified by the present invention and before modification. The conditions for adjusting the length of already designed wiring are:
Ln + L ₀ −ΔL ≦ correction result ≦ Ln + L ₀ + ΔL. The correction results based on this condition are shown in the corrected wiring diagrams of FIGS. 4, 5, 6, 7, and 8.

FIG. 4 shows a case where the virtual via hole 2 is removed and extended to the side thereof. FIG. 5 shows a case in which the allowable dimension of d1 is larger than that in FIG. 4, or the route of FIG. 4 cannot be secured due to the designed wiring and the designed via hole, and the virtual via hole 2 is extended in a shape enclosing it.

FIG. 6 shows a case where the permissible dimension of PL is shorter than that in FIG. 4, and a case where the virtual via holes 2 are removed to the left and right to extend. 7 and 8 are special examples in the case where the virtual via hole 2 is a minute via hole and has wiring specifications that can be formed on a 1.27 mm grid.

The automatic correction processing program for correcting in this way is based on the following correction procedure. (1) Recognize the longest sequence in an isometric sequence group. (Longest is the maximum of delay time conversion) (2) Focusing on each sequence other than the longest sequence, find the delay time difference from the longest sequence.

(3) Focusing on the position of each component terminal (or via hole) in the series, it is divided into an X-direction layer and a Y-direction layer,
The wiring is detoured and extended for each of the X-direction layer and the Y-direction layer. (4) If the difference in wiring length conversion can be extended at this point, the adjustment process is completed.

If the necessary length cannot be extended due to obstacles such as the detour allowable limit length or the designed wiring pattern, component terminals, via holes, and wiring prohibited areas, a schematic perspective view of each wiring layer in FIG. As shown in (4), the same adjustment process is repeated for each of the points of interest A to E in another layer and another via hole position.

Now, description will be made with reference to a predesigned wiring diagram of another embodiment shown in FIG. This Figure 10 shows A1 (starting point)
-A2 (end point) series A and B1 (start point) -B2 (end point) series B are shown on a grid line with 2.54 mm intervals, which is indicated by a chain line. In the figure, the thick line is the X direction layer, and the thin line is Y.
Wiring in the direction layer, circles with dots indicate via holes, and open circles indicate component terminals. If the wiring shown in FIG. 10 is modified by the conventional technique, the wiring diagram shown in FIG. 11 is obtained. According to this wiring diagram, the shorter wirings B1 to B2 are extended across the X-direction layer and the Y-direction layer, and each layer is extended and corrected in a zigzag shape. The four wires, the four wires in the Y-direction layer, and the four via holes with a dot circle are crushed.

However, when the wiring of FIG. 10 is modified by the method of the present invention, the wiring diagram shown in FIG. 12 is obtained. According to the wiring diagram after this correction, one wiring in the X-direction layer with a circle and Y
It is possible to repair without sacrificing the three wirings in the directional layer and the four via holes having a dot circle.

According to such a correction method, the interference with the designed via hole and other wiring patterns can be reduced as compared with the conventional correction method, the via hole neck and the wiring channel neck can be suppressed as much as possible, and the wiring can be suppressed. By wiring the pattern with few right-angled bending points, it is possible to prevent the radiation noise and the signal waveform from being disturbed in terms of electrical conditions.

[0028]

As described above in detail, according to the present invention,
It can be applied to wiring boards such as exchanges with a large number of equal-length specified series to support high-density wiring and high-speed signals, and can also contribute to reducing wiring man-hours, which is extremely useful in the industry. To do.

[Brief description of drawings]

FIG. 1 is a wiring diagram for explaining a method for wiring an equal-length designated net according to an embodiment of the present invention.

FIG. 2 is a delay time conversion diagram used for correction of FIG.

FIG. 3 is a pre-designed wiring diagram to be modified according to the present invention.

FIG. 4 is a wiring diagram after correction of FIG. 3 (No. 1)

5 is a wiring diagram after the modification of FIG. 3 (No. 2)

FIG. 6 is a wiring diagram after correction of FIG. 3 (No. 3)

FIG. 7 is a wiring diagram after correction of FIG. 3 (No. 4)

FIG. 8 is a modified wiring diagram of FIG. 3 (Part 5).

FIG. 9 is a schematic perspective view of each wiring layer according to the present invention.

FIG. 10 is a pre-designed wiring diagram before correction of another embodiment according to the present invention.

11 is a wiring diagram after correction according to the conventional technique of FIG.

FIG. 12 is a wiring diagram after correction according to the present invention in FIG.

FIG. 13 is a wiring diagram for explaining a method for wiring a specified length net according to the related art.

[Explanation of symbols]

 a and b are wiring

Claims (1)

[Claims] 1. A wiring method for an equal-length designated net, wherein the signal delay time between a plurality of predesigned isometric sequences is made substantially the same by converting the signal delay time into a wiring length or the like. Among them, the isometric series having a short wiring length based on the longest isometric series is used as an orthogonal X-direction layer, Y
Wirings (a) and (b) arranged between the start point and the end point of the equal length series for each of the X direction layer and the Y direction layer are at least outside on the extension line connecting the start point and the end point. A wiring method for an equal-length designated net, which is characterized in that the wiring length is made substantially the same by performing detour extension and wiring at one turn from one point.