JPH1173443A - Pattern design processing method for printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the influence of an adjacent pattern and to lighten the burden of designing on a person by arranging clock system signal lines to prescribed line length, making those lines thick and no other wires nearby those lines, and then automatically wiring general signal lines. SOLUTION: A clock wiring means 1 sets the wiring patterns of the clock system signal lines first with line width (a) similar to that of normal general signal lines. Then a clock wiring width expanding means 2 expands the line width of the clock system signal lines to width wider than one grid on both the sides adjoining to at least the clock system signal lines. Other wiring is inhibited within this expanded signal line width. Then other general signal lines are wired by an automatic wiring means 3 as usual. At this time, they are arranged outside the range of the expanded clock system signal width, so the limit of the prescribed parallel line length is not exceeded. After the automatic wiring, the clock system signal lines are put back to the normal signal line width.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a printed wiring board (P)
(T board) pattern wiring design processing method. 2. Description of the Related Art Printed circuit boards are used in various types of electronic devices, and among them, printed circuit boards mounted with digital circuits for performing various logical processes using a clock signal as one of the inputs are widely used in information processing apparatuses and the like.

The wiring of such a clock signal causes mutual interference with the pattern of another adjacent signal line.
The length of the line parallel to the pattern of the other signal lines is strictly limited to be as short as possible. It is desired to establish a design method on how to wire such a signal having a strict parallel line length.

[0003]

2. Description of the Related Art FIG. 7 shows an example of a circuit including a clock signal. The output of an oscillator is input to a clock driver to generate a clock signal having a reference frequency. Clock signals of various frequencies are generated by the frequency divider from the reference clock signal. The clock signal is supplied to various circuits that perform digital processing, and synchronizes the processing of the digital signal in each circuit. In the example of FIG. 7, the clock signal output from the frequency divider is supplied to the FF1 (flip-flop circuit 1) and performs a synchronous operation with the signal output from another FF2. Circuits including such clock signals are generally and widely used in the fields of communication and information processing.

As a printed wiring board, a multilayer board having a large number of wiring layers is widely used, and a clock signal wiring is often provided in an inner layer which is hardly affected by the outside. In that case, the clock signal is supplied to a plurality of layers because it is used for various circuits. In addition, if only the clock signal system is collected and wired in one layer, the number of wirings in other layers increases, making wiring difficult, and there is a problem in terms of miniaturization of the device and cost. Therefore, a clock signal system and a general signal (control signal, data signal, etc.) are often mixed in the same layer.

In a printed wiring board, clock system wiring is strictly restricted, and the line length is defined from the relation of delay, and the parallel line length with an adjacent pattern is not affected by noise from the parallel line. Is constrained.

Conventionally, for a net having a strict wiring length, a method as shown in FIGS. 8 and 9 has been used.
FIG. 8 is an explanatory diagram of Conventional Example 1, and FIG. Indicates a wiring pattern; Shows a processing flow. In the first conventional example, first, a clock system pattern (clock signal line) is first manually drawn according to the prescribed wiring length. This clock system pattern is described in A. Is shown as a in FIG. Note that the printed wiring board has a large number of parallel vertical or horizontal straight lines (called grids or tracks) arranged at regular intervals at which wiring can be drawn in advance in accordance with the specifications of the printed board. ) Is prepared, and the clock signal line is set using one of the lines.

Next, general signal lines are provided by automatic wiring. This automatic wiring is executed by a conventionally known program. The pattern of this general signal line is described in A.I. Are shown as b1 and b2. In this case, with respect to the clock signal line grid, the general signal line is fixed to an adjacent grid (a distance between one grid is referred to as d) or a line of a grid next to the adjacent grid (separated by a distance of 2d). Stretch with line width.

After the automatic wiring, a parallel line check with the adjacent pattern is performed by displaying the result on a display or the like, and if the length exceeds the specified parallel line length, a correction such as moving the adjacent pattern is performed. Do. FIG. In the example, it is understood that the general signal lines b1 and b2 violate the rules,
The lines are respectively corrected to lines b1 'and b2' by line movement.

FIG. 9 is an explanatory diagram of Conventional Example 2, and FIG. Indicates a wiring pattern; Shows a processing flow. Conventional example 2
, The clock pattern is manually drawn according to the wiring length regulations. FIG. In the example, the clock pattern shown in a is drawn. Next, a ground (GND) pattern having a somewhat wide line width is provided around the grid immediately adjacent to the clock pattern a so that the general signal pattern cannot run. FIG. In the example, c1 and c2 are ground patterns. Then, general signal lines are automatically wired. In this case, wiring is performed avoiding the ground pattern. Next, a work for obtaining a ground pattern is performed.

[0010]

In the method of the prior art 1 described above, it takes time and effort to correct the pattern after automatic wiring, and in the case of complicated wiring, it may be difficult to find the destination. There is.

Further, in the method of the conventional example 2, since a ground pattern must be provided on both sides of each clock system signal, the operation is complicated. Finally, it is necessary to remove the ground pattern.
There is a problem that the burden on the designer is large.

According to the present invention, there is provided a printed wiring which can reduce the work of a signal line, such as a clock signal line, in which a signal line length or a parallel line length with an adjacent pattern is restricted due to noise or the like by a human. An object of the present invention is to provide a method of processing a pattern design of a plate and a recording medium.

[0013]

FIG. 1 is a diagram showing the principle configuration of the present invention. FIG. Indicates the configuration; Indicates the original line width and the expanded line width of the clock signal line. FIG. , 1 is a clock wiring means for wiring a clock signal line, 2 is a clock wiring width expanding means for expanding a wiring width of a clock signal line, and 3 is a general signal line automatic wiring means for automatically wiring a general signal line. , 4 are clock wiring width returning means for returning the clock signal line to the original line width.

In this principle configuration, a case is described where a signal whose signal line length or parallel line length with an adjacent pattern is limited is a clock signal, but the same applies to a signal line having similar characteristics. Can be.

First, based on the wiring pattern design data, the clock wiring means 1 sets a wiring pattern of a clock signal line on a printed wiring board with a line width similar to that of a general signal line. The wiring pattern of this clock system signal line is shown in FIG. A. Next, with respect to the pattern data of the printed wiring board on which the clock signal lines are set, a process of expanding the line width of the clock signal lines is performed by the clock wiring width expanding means 2. In this case, the expanded line width of the clock signal line is set to be wider than at least one grid on both sides adjacent to the clock signal line. Other wiring is prohibited within the enlarged signal line width. FIG. An example in which the expanded clock signal line width is wider than at least one adjacent grid is shown by hatching.

When the clock wiring width expanding means 2 detects a state in which wiring of adjacent pins of a component cannot be performed due to the expansion of the line width, the line width is returned to the original line width for a part thereof. Wiring is enabled for parts. Thereafter, wiring of other general signal lines is performed by the automatic wiring means 3 similar to the conventional one. At this time, since the wiring is performed outside the range of the expanded clock signal line width, the specified limit of the parallel line length is not exceeded. When the automatic wiring is completed, the clock wiring width restoring means 4 is activated to return the enlarged clock signal line in the wiring data obtained by the automatic wiring to the normal signal line width. Using the wiring setting data obtained as a result, manufacturing data of the printed wiring board is created.

[0017]

FIG. 2 shows a flow chart of the embodiment. FIG. 3 is an eight-layer printed wiring board to which the present invention is applied, FIG. 4 is an example of an increase in the clock signal line width, FIG. 5 is a diagram for explaining the relationship between adjacent pins after the line width is increased, and FIG. FIG. 11 is a diagram illustrating a relationship with another clock signal line after the width is enlarged.

This embodiment can be implemented by an information processing apparatus including a CPU, a memory, a display, a keyboard, a mouse, a tablet, and the like. In FIG. 2, according to the circuit diagram input, various signal lines are formed according to the specifications of the printed wiring board (layers and sizes of the printed wiring board, widths and intervals of mounted component pins and external connection pins, grid intervals, and the like). The printed wiring board is designed using the design program in terms of the name and the connection relation of the wiring.
0 is obtained (S1 in FIG. 2). For example, as shown in FIG. 3, an eight-layer printed wiring board is used as a printed wiring board, and layers for providing signal lines are a first layer, a second layer, a seventh layer, and an eighth layer. Clock signal lines are provided in the second and seventh layers as inner layers (general signal lines are also provided in these layers), and the line width of the normal signal line is set to d1 (for example, 1).
00 μm (micron)) and the grid interval is d2 (for example, 300 μm).

Next, using the wiring design data 20, the wiring of the clock signal is arranged on the determined layer (S2 in FIG. 2). At this time, the clock signal wiring is
As shown in the figure, the second and seventh layers of the printed wiring board have a line width d.
1, the wiring is arranged so as to have a length in accordance with the wiring length rule.
Data including the clock signal wiring is wiring data 2
Obtained as 1. Next, the line of the clock signal of the line data 21 is subjected to line width expansion processing (S in FIG.
3) The data of the clock signal line of the wiring data 21 is updated. Specifically, in order to prevent other lines from running in the same layer in the immediate vicinity of the clock signal line (width d1),
The clock signal line width is increased to several grids. The width of the enlargement differs depending on the printed wiring board, the grid interval, and the like. If it is desired to prohibit the wiring of the immediately adjacent line, the width may be enlarged to two grids including the adjacent grids. In the example of FIG. 4, wiring is prohibited for the next grid and the next grid (two grids), and the line width is expanded from d1 to a range of four grids.

Following the enlargement of the line width, the wiring design data 20 is used to check and correct the relationship between the pin connection of components and the arrangement of vias for connecting layers between layers based on the enlarged line width. (S4 in FIG. 2).

The relationship between a component and an adjacent pin will be described with reference to FIG. When the pins of the component 32 are mounted on the printed wiring board, the clock signal line 30 of the printed wiring board is enlarged to provide an enlarged line width 31 including a total of four grids including two grids on both sides thereof. Indicates the status. In this case, the clock signal line 30 and the pin p1
Is connected, the pins p2 and p3 adjacent to the pin p1 are included in the range of the enlarged line width 31 because the interval between the pins p1 and p3 is small. Impossible. Therefore, only the wiring portion of these pins is subjected to a process of returning the enlarged clock signal line 30 to the original normal line width d1, and FIG.
B. Shows the state returned to.

The relationship between adjacent clock lines will be described with reference to FIG. This is an example in which another clock signal line CL2 is arranged near the clock signal line CL1 on the same layer. A. Indicates a state where each line width is expanded to four grids. In this state, each of the clock signal lines CL1 and CL2 can develop a pattern in another layer.
The space area at the boundary of the enlarged line width becomes extremely narrow. At this time, for example, when there is a design requirement that wiring of another layer, for example, a via for connecting a specific signal between the first layer and the eighth layer needs to be provided at this boundary portion. In this state, there is a possibility that connection between other layers cannot be made. Also in this case, the line width of the enlarged clock signal line of the corresponding portion is restored to the original line width d1, and a via can be placed near the clock signal line. By performing other wiring only in the outer layer (not used), the wiring ratio can be further increased.

Next, the wiring of the general signal lines excluding the clock signal lines is executed by the conventional automatic wiring processing using the wiring design data 20 (S5 in FIG. 2). In this case, since the area of the expanded line width of the clock line is prohibited from being routed, the pattern of the general signal line is provided in the area other than the area. Thus, the wiring pattern data 21 including the clock signal lines and the general signal lines is obtained. Subsequently, for the wiring pattern data 21, processing is performed to return the line widths of all the enlarged clock signal lines to the original line widths (S in FIG. 2).
6).

The wiring pattern data 2 obtained as a result
1, the production data 22 of the printed wiring board is created (S7 in FIG. 2). In the above embodiment, the enlargement is performed when a failure in the connection with the adjacent pin of the component is detected after the enlargement of the clock signal line or when there is a failure in the arrangement of the vias for the signal connection between the layers. The initial line width is restored, but at the time of the first clock system signal line expansion process, the part where each fault exists is detected in advance, and the line width is expanded excluding those parts. Is also good.

[0025]

According to the present invention, before performing other wiring, the clock system signal lines are arranged according to the prescribed line length, and these lines are thickened beforehand, and the other wiring is placed near these lines. By automatically routing the general signal lines while avoiding this, it is possible to satisfy the strict conditions of specifying the line length for the clock signal lines and making it less susceptible to the influence of the adjacent pattern, and at the same time, the burden on the design. Can be reduced or eliminated.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a diagram showing a flowchart of the embodiment.

FIG. 3 is a diagram showing an eight-layer printed wiring board to which the present invention is applied.

FIG. 4 is a diagram illustrating an example of expansion of a clock system signal line width.

FIG. 5 is a diagram illustrating a relationship with an adjacent pin after the line width is enlarged.

FIG. 6 is an explanatory diagram of a relationship with another clock signal line after the line width is enlarged.

FIG. 7 is a diagram illustrating an example of a circuit including a clock signal.

FIG. 8 is an explanatory diagram of Conventional Example 1.

FIG. 9 is an explanatory diagram of Conventional Example 2.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Clock wiring means 2 Clock wiring width expanding means 3 General signal line automatic wiring means 4 Clock wiring width returning means

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yuji Kansaka 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Satoshi Sakai 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Limited (72) Inventor Hitari Ogura 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor Yasumasa Honjo 4 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture 1-1 1-1 Fujitsu Co., Ltd. (72) Inventor Tomohiro Kai 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Co., Ltd. (72) Inventor Eiji Kanaya 4 Kamikadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (72) Inventor Toshio Yasutake 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Inside the formula company (72) Inventor Yumi Hirasawa 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (72) Inventor Mitsuru Sasaki 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu (72) Inventor Masato Semii 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Co., Ltd. (72) Akiko Oshimi 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture No. Within Fujitsu Limited (72) Inventor Hiroki Miyata 98 Uno-Ki-nu, Unoki-cho, Kawakita-gun, Ishikawa Prefecture 2 PFU Inc. 2 PFU Corporation

Claims (3)

[Claims] In a method for designing a pattern of a printed wiring board including a clock signal line, a clock signal line is first wired on a printed wiring board with a normal line width, and the line width of the line is set to at least the adjacent normal line width. Widen more than the wiring position (grid), then wire other general signal lines with normal line width, then return the clock signal line to the original normal line width and print based on the obtained wiring data A method for processing a pattern of a printed wiring board, the method comprising creating manufacturing data of the board. 2. An apparatus according to claim 1, wherein when the presence of an obstacle is detected within the enlarged line width after the line width of the clock signal line is enlarged, the portion is returned to a normal line width and the other line width is changed. And a method for designing a pattern of a printed wiring board. 3. The clock signal line according to claim 1, wherein before the line width of the clock signal line is increased, a part which becomes an obstacle due to other components or connection is detected in advance, and the detected signal part is excluded. A pattern design processing method for a printed wiring board, characterized by enlarging a line width.