JP2007258331A - Design support device and method for multilayer substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a design support device and a design support method for multilayer substrate, capable of detecting and correcting a portion with high possibility of producing pattern failure from wiring design information of the multilayer substrate, without performing trial production of the multilayer substrate in a multilayer substrate formed by forming a laminate yielded, by laminating in layers a plurality of substrates having a wiring pattern and heating or pressurizing the laminate. <P>SOLUTION: The design support device (1) of a multilayer substrate comprises an input part (2) for acquiring wiring design information of the multilayer substrate; an extractor (12) for extracting a danger region, where pattern failure might happen by heating or pressurizing the laminate from the acquired wiring design information; and an estimator (13) for deciding whether the pattern failure happens on the basis of an amount of displacement, by estimating the amount of displacement from the design position of a wiring pattern caused, by heating or pressurizing the laminate for the wiring pattern involved in the danger portion extracted in the extractor (12), on the basis of the wiring design information. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a design support apparatus and a design support method for a multilayer board, and more specifically, a multilayer board that supports circuit design of a multilayer board by evaluating a displacement of a wiring pattern during the bonding process of the multilayer board. The present invention relates to a design support apparatus and a design support method.

  2. Description of the Related Art In recent years, high-density mounting of electronic circuits has further progressed, and as a result, there is an increasing need for a multilayer substrate on which electronic circuit elements can be mounted in multiple layers. Such a multilayer substrate includes, for example, a laminating step of laminating a resin film serving as an insulating base, an arranging step of arranging an electric element between the resin films, and a laminating of the laminated resin films after the laminating step and the arranging step. By heating the body while applying pressure from both sides, the body is manufactured by using a method for manufacturing a multilayer substrate having an adhesion process for bonding the resin films to each other (see Patent Document 1).

  Here, a wiring metal (for example, copper foil) is patterned on each laminated resin film. Therefore, at the stage where the above-described lamination process is completed, a step (the presence or absence of voids) occurs between the resin films due to the presence or absence of the copper foil. This step is filled by melting the resin in the bonding step and flowing into the gap. However, depending on the design result of the multilayer substrate, a region where the copper foil is present in most of the laminated resin films and a region where the copper foil is not present in the respective resin films are generated. When areas with greatly different amounts of copper foil are adjacent (that is, areas with a lot of voids and areas with few voids are adjacent), if pressure and heating are applied to the laminate in the bonding process, a large resin flow will occur. appear. If there is an isolated small land pattern or thin wiring pattern in a place where this large resin flow occurs, the wiring pattern is greatly deformed by the resin flow, and the position of the via differs from one board to another adjacent wiring pattern. There is a risk of pattern defects such as contact or disconnection of the wiring pattern.

  Conventionally, such a pattern defect is discovered for the first time by actually manufacturing a multilayer substrate and then performing electrical inspection, fluoroscopic observation with X-rays, or destructive inspection by cutting the multilayer substrate and observing a cross section. It was a thing. Furthermore, such countermeasures against pattern defects are trial and error relying on experience, and require a lot of time and cost.

  On the other hand, a board design support apparatus that predicts a displacement amount due to a temperature change of a multilayer board has been developed for such a problem (see Patent Document 2). The substrate design support apparatus described in Patent Document 2 obtains an average thickness with respect to the substrate area for the main material constituting each layer constituting the multilayer substrate by the layer thickness calculation unit, A simple lamination model is created by laminating layers having the layer thicknesses calculated by the layer thickness calculator. And the displacement amount calculation part calculates the displacement amount which arises with a process temperature change based on the physical property information which comprises each layer about the created simple lamination | stacking model. Therefore, the substrate design support apparatus described in Patent Document 2 can predict a displacement due to a temperature change of the multilayer substrate as a change in the unevenness of each part of the substrate.

  However, although the substrate design apparatus described in Patent Document 2 can predict the magnitude of the displacement at each position of the multilayer substrate, it is not assumed to determine whether or not a pattern defect is caused by the displacement. Further, since the displacement amount is calculated for the entire multilayer substrate, when the multilayer substrate is enlarged, the time required for calculating the displacement amount is increased with the increase in size.

JP 2003-086949 A JP 2006-053706 A

  In view of the above problems, an object of the present invention is to provide a multilayer board that can detect and correct a portion that is highly likely to cause a pattern defect from the wiring design information of the multilayer board without making a prototype of the multilayer board. A design support apparatus and a design support method are provided.

  Another object of the present invention is to provide a design support apparatus and a design support method for a multilayer board that can accurately detect a portion that is likely to cause a pattern defect from the wiring design information of the multilayer board. .

  Still another object of the present invention is to provide a design support apparatus and a design support method for a multilayer board that can detect and correct a portion that is likely to cause a pattern defect from the wiring design information of the multilayer board in a short time. There is.

  According to the first aspect of the present invention, the multilayer substrate design support apparatus (1) according to the present invention is a laminate in which a plurality of substrates having wiring patterns are stacked in layers from the acquired wiring design information. An extraction unit (12) for extracting a dangerous part that may cause a pattern defect by heating or pressurizing the wiring pattern, and stacking the wiring pattern included in the extracted dangerous part based on the wiring design information An estimation unit (13) for estimating a displacement amount from the design position of the wiring pattern by heating or pressurizing the body and determining whether or not a pattern defect occurs based on the displacement amount; With such a configuration, it is possible to detect a portion having a high possibility of causing a pattern defect from the wiring design information of the multilayer board without performing a trial production of the multilayer board. In addition, since the amount of displacement is calculated only for the extracted portion, it is possible to detect a portion where a pattern defect is likely to occur from the wiring design information in a short time.

  According to the second aspect of the present invention, the extraction unit (12) includes a dividing unit (121) for dividing the multilayer substrate into a plurality of regions, and wiring design for each of the divided regions. Density calculating means (122) for calculating a pattern density representing the degree of including the wiring pattern based on the information, and dangerous part extracting means (123) for extracting the dangerous part based on the calculated pattern density.

Further, according to the third aspect of the present invention, the dangerous part extraction means (123) sets at least one of the plurality of areas as the attention area, and the pattern density of the attention area and the vicinity of the attention area. The dangerous part is extracted based on the difference in pattern density of any one of the plurality of regions.
Alternatively, according to the fourth aspect of the present invention, the dangerous part extraction means (123) sets at least one of the plurality of areas as the attention area, the pattern density of the attention area, and the vicinity of the attention area. When the absolute value of the difference in pattern density of any of the plurality of regions is equal to or greater than a predetermined threshold and the region of interest is included in the predetermined wiring pattern structure, the predetermined wiring pattern structure is extracted as a dangerous part. By extracting the dangerous part based on the change in pattern density, the dangerous part can be accurately extracted.

  According to the fifth aspect of the present invention, the multi-layer board design support apparatus (1) according to the present invention is compatible with a wiring pattern included in a dangerous part determined to have a pattern defect by the estimation unit. And a correction unit (14) for correcting the design data in the wiring design information. With such a configuration, it is possible to correct a portion having a high possibility of causing a pattern defect from the wiring design information of the multilayer board without performing a trial production of the multilayer board.

  According to the sixth aspect of the present invention, the correction unit (14) has at least one correction rule, and the design corresponding to the wiring pattern included in the dangerous part determined to have a pattern defect. Whether to apply at least one correction rule is determined based on the data, and the design data is corrected based on the correction rule determined to be applicable.

  According to the embodiment of the present invention, the multi-layer board design support apparatus (1) according to the present invention includes a design verification unit (11) that verifies the wiring design information based on a predetermined design rule. Therefore, it is possible to detect wiring design information including a part that causes a problem in circuit design before performing processing such as extraction of a dangerous part and estimation of a displacement amount. Therefore, it is possible to avoid unnecessary processing. Furthermore, it has a rule addition unit (15) for correcting a predetermined design rule or adding a new design rule based on design data corresponding to a wiring pattern included in a dangerous part determined to cause a pattern defect. Thus, the verification accuracy in the design verification unit (11) can be increased as the design support apparatus (1) is used.

  According to the eighth aspect of the present invention, the multilayer substrate design support method according to the present invention is based on the obtained wiring design information, and there is a risk that a pattern defect may occur by heating or pressurizing the laminate. A step of extracting a part (S106) and, based on the wiring design information, the wiring pattern included in the dangerous part extracted by the extraction unit from the design position of the wiring pattern by heating or pressurizing the laminate. (S108) and a step (S109) of determining whether or not a pattern defect occurs based on the displacement. With such a configuration, it is possible to detect a portion having a high possibility of causing a pattern defect from the wiring design information of the multilayer board without performing a trial production of the multilayer board. In addition, since the amount of displacement is calculated only for the extracted portion, it is possible to detect a portion where a pattern defect is likely to occur from the wiring design information in a short time.

  In addition, the code | symbol in the parenthesis attached | subjected to each said means is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

  Hereinafter, a substrate design support apparatus to which the present invention is applied will be described in detail with reference to the drawings. The board design support apparatus to which the present invention is applied is based on the local flow of the ratio of the wiring pattern included from the wiring design information, which is the artwork representing the circuit arrangement of the board of each layer of the multilayer board. Extract dangerous parts where pattern defects may occur. Then, the board design support apparatus estimates the amount of displacement from the design position of the wiring pattern by performing the flow-structure coupling analysis of the dangerous part, and determines whether or not a pattern defect occurs based on the estimation result. Further, when it is determined that a pattern defect occurs, the board design support device automatically corrects the design data of the wiring pattern corresponding to the dangerous part determined to cause the pattern defect. Therefore, an appropriate substrate design can be performed without trial manufacture of a multilayer substrate. In addition, since the board design support apparatus to which the present invention is applied limits the region where the fluid-structure coupled analysis is performed, the verification and correction of the wiring design information can be performed in a relatively short time without requiring a long time for the analysis. It can be performed.

  FIG. 1 shows a functional block diagram of a board design support apparatus 1 to which the present invention is applied. A substrate design support apparatus 1 to which the present invention is applied includes a data input / output unit 2, a storage unit 3, and a processing unit 4. The board design support apparatus 1 acquires wiring design information of the multilayer board from the data input / output unit 2. The processing unit 4 of the board design support apparatus 1 reads necessary information such as design rules and material characteristic data from the storage unit 3 and extracts a portion having a risk of pattern failure from the acquired wiring design information.・ Verify. Further, the processing unit 4 corrects the wiring pattern design data included in the wiring design information as necessary. Thereafter, the board design support apparatus 1 outputs the wiring design information that has been verified (and corrected in some cases) from the data input / output unit 2.

Hereinafter, each part will be described in detail.
The data input / output unit 2 is an interface for connecting the board design support apparatus 1 to an external device, and includes a communication port, an electronic circuit, and driver software compliant with standards such as Ethernet (registered trademark), USB, SCSI, and RS-232C. Etc. The data input / output unit 2 acquires the wiring design information sent from the external device and passes it to the processing unit 4. Further, the wiring design information verified and corrected by the processing unit 4 is output to an external device.

  The storage unit 3 includes design rules, correction rules, physical property data (density, viscosity, thermal diffusivity, etc.) of materials constituting the multilayer substrate, copper constituting the wiring pattern, thickness information on the resin of each layer, vias, etc. 4 for storing various programs and setting files used in 4 and comprising a non-volatile memory such as a flash memory, a magnetic recording medium such as a hard disk, or an optical recording medium such as a CD-ROM and DVD-R / W Is done. The storage unit 3 transmits necessary data in response to a request from the processing unit 4. The storage unit 3 stores various data sent through the processing unit 4.

  The processing unit 4 verifies the wiring design information acquired from the data input / output unit 2 and corrects it if necessary. The processing unit 4 is a semiconductor memory such as a central processing unit (CPU), a numerical operation processor, a ROM, or a RAM. Etc. Further, the processing unit 4 executes a predetermined operation according to the program read from the storage unit 3. Further, the processing unit 4 is connected to the data input / output unit 2 and the storage unit 3, and performs control by outputting predetermined control signals to these units. The processing unit 4 includes a control unit 10, a design verification unit 11, an extraction unit 12, an estimation unit 13, a correction unit 14, and a rule addition unit 15 in order to verify and correct the wiring design information and control each unit. Have.

  Then, the design verification unit 11 verifies whether there is a portion that violates a predetermined design rule in the acquired wiring design information. The extraction unit 12 extracts a portion that may cause a wiring pattern defect from the wiring design information as a dangerous part. Then, the estimation unit 13 performs a flow-structure interaction analysis based on the extracted dangerous part and the artwork and physical property data of the surrounding small area, and determines whether or not a wiring pattern defect occurs. Further, the correction unit 14 corrects the design data corresponding to the dangerous part determined by the estimation unit 13 that the wiring pattern defect occurs based on a predetermined correction rule. The control unit 10 controls each unit of the processing unit 4, the data input / output unit 2, and the storage unit 3.

Hereinafter, each unit of the processing unit 4 will be described.
The control unit 10 delivers various data such as control of the data input / output unit 2 and the storage unit 3 and wiring design information according to the programs and various setting files read from the storage unit 3. Further, the control unit 10 controls processing by the rule verification unit 11, the extraction unit 12, the estimation unit 13, and the correction unit 14 in the processing unit 4.

  The design verification unit 11 verifies the acquired wiring design information based on a predetermined design rule acquired from the storage unit 3. Here, the wiring design information is an artwork representing the circuit arrangement of the substrate of each layer as described above, and is described as CAD data according to a format such as Drawing Exchange File (DXF) or eXtensible Markup Language (XML), for example. . In the wiring design information, the wiring pattern type (land, via, line, etc.), wiring pattern shape, size, position coordinates, etc. are described as design data for each wiring pattern. On the other hand, the predetermined design rule is, for example, for each parameter such as the line width of the wiring pattern in each layer, the distance to the adjacent wiring pattern, the diameter of the via, the length of the wiring pattern, the type of the wiring pattern, and the combination of these parameters. To set the allowable range. That is, each design rule is defined by the upper limit value or the lower limit value of the allowable range of the parameter regarding the evaluation item.

  In addition, design rules are prepared for parameters that can be evaluated and combinations of these parameters. Among them, a design rule for a parameter that has not been evaluated at a certain time is an unused rule. In the unused rule, the upper limit value and the lower limit value of the allowable range for the parameter to be evaluated are stored as values (for example, “−999”) indicating that they are not set. As will be described later, when the upper limit value or the lower limit value of the allowable range is set for a parameter that has not been evaluated by the rule adding unit 15 (that is, when a design rule is added), the design verification unit 11 Design verification is performed using the added design rule.

The design verification unit 11 sequentially reads design data of individual wiring patterns from the wiring design information and obtains parameters used for design verification. Each parameter obtained is applied to a design rule to evaluate whether it is within an allowable range. When the design verification unit 11 finds a parameter that is outside the allowable range, the design verification unit 11 writes the wiring pattern design data related to the parameter to the violation list. The violation list describes, for example, the above-described wiring pattern design data in a list format. If the wiring verification information does not find a wiring pattern that violates (that is, if nothing is described in the violation list), the design verification unit 11 determines that the wiring design information does not have a rule violation part. Then, the wiring design information is sent to the extraction unit 12. On the other hand, when a violating wiring pattern is found in the wiring design information (that is, when there is at least one description in the violation list), the wiring design information is sent to the correction unit 14 together with the violation list.
The design verification unit 11 may verify the wiring design information using another known method. In addition, the design verification unit 11 may perform verification based on a rule determined with respect to other than the dimensions of the wiring pattern (for example, the number of vias).

  When creating the multi-layer substrate, the extraction unit 12 extracts from the wiring design information of the multi-layer substrate, a dangerous portion that may cause a pattern defect by heating or pressurizing the stacked body in which the plurality of substrates are stacked. . For this purpose, the extraction unit 12 includes a dividing unit 121, a density calculating unit 122, and a dangerous part extracting unit 123.

  The dividing means 121 virtually divides the entire multilayer board to be created into small areas. Here, each small region is a cubic region, and one small region includes from the uppermost layer to the lowermost layer of the multilayer substrate. A state of division into small regions will be described with reference to FIGS. FIG. 2A is a schematic plan view of a multilayer substrate, and FIG. 2B is an enlarged view of a region 250 in FIG. 2A and 2B, the size of each wiring pattern 210 is exaggerated for clarity of explanation. As shown in FIGS. 2A and 2B, a wiring pattern 210 is formed on the multilayer substrate 200. Although not shown in the figure, wiring patterns are similarly formed on each layer other than the surface of the multilayer substrate 200. Further, as shown in FIG. 2B, each small region 260 has a sufficiently small size with respect to the wiring pattern and the distance between the wiring patterns in order to accurately evaluate the difference in pattern density described later. Set to In the present embodiment, each small region is a rectangular region in which the length of one side is 1/10 of the average line width of the wiring pattern included in the wiring design information. However, the size of each small area is not limited to this, and for example, it may be a rectangular area in which the length of one side is 1/5 to 1/20 of the average line width of the wiring pattern included in the wiring design information. it can. Further, the size of each small area may be changed depending on the location on the substrate. For example, the size of the small region may be set large in a region with few wiring patterns, and the size of the small region may be set small in a region where wiring patterns are dense. Furthermore, the shape of each small region is not limited to a rectangle, and may be, for example, a shape in which an annulus is divided at equal angular intervals or a triangle. Further, the multilayer substrate may be divided into upper and lower parts, and small areas may be set separately on the upper and lower sides.

  The density calculation unit 122 calculates the pattern density of each small area set by the dividing unit 121. Here, the pattern density refers to a ratio of a substrate on which a wiring pattern is formed among all layers of substrates included in each small region. The density calculation means 122 calculates the pattern density for each small region as follows. First, the density calculation means 122 is “1” if any wiring pattern is formed in a portion included in the small area for each substrate of each layer, and no wiring pattern is formed at all. Set to '0'. Then, the density calculation means 122 adds the above 1 or 0 value obtained for each layer. Finally, the sum is divided by the number of layers constituting the multilayer substrate, and normalized so as to have any value between 0 and 1.

  The calculation of the pattern density will be described with reference to FIG. FIG. 3 is a schematic cross-sectional view of a multilayer board to be created. In FIG. 3, the multilayer substrate 300 is composed of five layers of substrate layers 310a to 310e made of resin. In addition, wiring patterns 320a to 320e are formed between the respective layers according to the design. One small region 330 is indicated by a dotted line. Therefore, when focusing on the small region 330, the wiring pattern 320a formed on the layer 310a and the wiring pattern 320c formed on the layer 310c are included. Therefore, the pattern density of the small region 330 is calculated as (1 + 0 + 1 + 0 + 0) /5=0.4.

  The dangerous part extraction unit 123 extracts a dangerous part that may cause a wiring pattern defect based on a change in pattern density. As described above, in the laminate of the resin film generated in the manufacturing process of the multilayer substrate, a portion having a gap and a portion having no gap are generated depending on the presence or absence of the wiring pattern. Therefore, in the bonding process in which the resin films are bonded to each other by heating the laminate while applying pressure from both sides, the resin may flow so as to fill the voids, thereby causing a wiring pattern defect. However, in a portion where the wiring patterns are dense or in an area where the wiring patterns are firmly connected to the surroundings, the wiring patterns prevent the resin from flowing greatly, so that there is little possibility of pattern defects. On the other hand, in a region where there is no wiring pattern, that is, a region having a large number of voids between layers, deformation due to heating and pressurization is likely to occur. Therefore, a portion where the pattern density changes abruptly compared to the surrounding area, or an isolated pattern (for example, a portion corresponding to a via) surrounded by a region where the pattern density is low causes a large resin flow and causes a pattern defect. It can happen.

  This state will be described with reference to FIG. FIG. 4A is a schematic cross-sectional view of the multilayer substrate 400 before performing the bonding step, and FIG. 4B illustrates the same step as that of the multilayer substrate 400 shown in FIG. 4A. FIG. 4A and 4B, the wiring pattern 410 is indicated by a thick line, and the via 420 is indicated by hatching. Here, comparing FIG. 4A and FIG. 4B, in the region 430 having a high pattern density where the wiring pattern 410 is formed in almost all layers, the wiring pattern changes almost before and after the bonding step. I understand that it is not. On the other hand, in the region 440 sandwiched between portions having a low pattern density, it can be seen that the wiring pattern 410 is largely shifted laterally after the bonding process. Similarly, in the region 450 including the via 420 at the center, it can be seen that the position of the via 420 is shifted between the layers after the bonding process.

  Therefore, the dangerous part extracting unit 123 extracts a dangerous part where a pattern defect may occur by finding a part where the pattern density rapidly changes. For this purpose, the dangerous part extraction unit 123 sequentially sets one small area from each small area as the target small area, and the pattern density of the target small area and the vicinity area of the target small area (for example, eight neighborhoods of the small area). Or the absolute value of the difference between the pattern density and the small area existing in the vicinity of 16). If the absolute value of any pattern density difference is greater than or equal to a predetermined threshold value, the small area of interest is detected as a caution area, and the position of the caution area is stored in the memory constituting the processing unit 4. The predetermined threshold can be set to 0.5, for example.

  When the above process is completed for all the small areas, the dangerous part extracting means 123 has a predetermined wiring pattern structure that is likely to cause a pattern defect based on the position of each area requiring attention and the wiring design information. Compare positions. Then, when any of the areas requiring attention matches the position of the predetermined wiring pattern structure, the dangerous part extracting unit 123 extracts a region including the entire predetermined wiring pattern structure as a dangerous part. The wiring pattern having a predetermined structure is an isolated pattern such as a via, and can be set in advance by experience. The region extracted as the dangerous part is set to a region that includes the above-described wiring pattern structure and a wiring pattern adjacent to the wiring pattern structure, for example.

  The estimation unit 13 determines whether or not a wiring pattern defect occurs in the dangerous part extracted by the extraction unit 12 by performing a fluid-structure coupling analysis. For this purpose, the estimation unit 13 acquires physical property data and thickness information of materials relating to the resin, the copper constituting the wiring pattern, and the like constituting each layer of the laminate included in the extracted dangerous part from the storage part 3, and the dangerous part An analysis model in which corresponding physical property data and thickness information are associated with each other is created. Such an analysis model can be described in, for example, the IGES format. When there are a plurality of extracted dangerous parts, the estimating unit 13 similarly creates an analysis model for each dangerous part.

  When the analysis model is created, the estimation unit 13 performs a flow-structure coupling analysis on the analysis model, and from the design position of the wiring pattern generated when heating and pressurization are applied to the laminate. Estimate the amount of displacement. Here, since various well-known methods and commercially available structural analysis solvers can be used for the fluid-structure interaction analysis, detailed description thereof is omitted. As an example of such well-known methods, Okuda, Oshiro, “Research on Unified Analysis of Thermal Fluid / Structure Coupled Problems and Data Parallelization”, The Japan Society for Computing Technology, Japan Society for Computer Science, The method described in 1999 can be used.

Based on the above estimation result, the estimation unit 13 determines that a pattern defect has occurred in the dangerous part, for example, when any of the following occurs. That is,
(1) The amount of displacement from the design position of the wiring pattern (the horizontal or vertical direction with respect to each layer of the substrate) exceeds a predetermined allowable amount.
(2) contact with an adjacent wiring pattern;
(3) The wiring pattern that should be continuous is interrupted,
(4) The position of the via between each layer exceeds the predetermined allowable amount,
(5) The substrate surface step is a predetermined threshold value or more.
It is.
The predetermined allowable amount can be set to a manufacturing tolerance of the wiring pattern (for example, a displacement amount is within 30 μm).

  When the estimation unit 13 determines that a pattern defect occurs in any dangerous part, the estimation part 13 sends information indicating the dangerous part to the correction part 14 to the correction part 14. Further, the estimation unit 13 uses the design data corresponding to the wiring pattern included in each dangerous part determined to have a pattern defect in the storage unit 3 to be used for the addition and correction of the design rule by the rule addition unit 15 described later. save.

The correction unit 14 corrects the position, size, and the like of the wiring pattern included in the dangerous part determined to cause the pattern defect based on a predetermined correction rule, and updates the wiring design information. Then, the updated wiring design information is sent to the rule verification unit 11 again.
For example, the predetermined correction rule is as follows.
(1) A solid pattern is added around a wiring pattern such as a land.
(2) In a region where the pattern density is sparse (for example, the pattern density is 0.4 or less), a solid pattern is added to any layer to increase the pattern density.
(3) The position or shape of the wiring pattern such as a land is changed so as to eliminate the portion where the displacement exceeds the allowable range.

The correcting unit 14 determines whether or not the above-described correction rules can be sequentially applied to each dangerous part. For example, for rule (1), the distance to the wiring pattern adjacent to the correction target wiring pattern is examined. And the correction | amendment part 14 determines with it being applicable, if the distance is not less than predetermined. Thereafter, the correction unit 14 adds a solid pattern around the wiring pattern to be corrected within a range in which the distance from the adjacent wiring pattern is equal to or greater than a predetermined minimum distance. Similarly, for rule (2), the correction unit 14 first searches for an unused area having a predetermined area or more in which no wiring pattern exists for each layer included in the dangerous part. When such an unused area is found, the correcting unit 14 determines that the rule (2) is applicable. Thereafter, the correction unit 14 adds a solid pattern in the found unused area. Similarly, for the rule (3), the correcting unit 14 similarly determines whether or not it is applicable, and if it determines that it is applicable, corrects the wiring pattern in accordance with the correction rule.
Note that the correction unit 14 may set a priority for each correction rule, and apply the correction rules in order from the correction rule with the highest priority.

  The rule adding unit 15 extracts a design rule used by the rule verification unit 11 based on the wiring pattern in the area where the estimation unit 13 determines that a wiring failure occurs and the surrounding wiring pattern, and stores the design rule in the storage unit 3. Remember. Alternatively, the existing design rule is corrected. Therefore, when the correction of the wiring design information is completed, the rule adding unit 15 stores, from the storage unit 3, design data corresponding to the wiring pattern included in the dangerous part that is determined to have a pattern defect during the correction of the wiring design information. Acquire and add and modify design rules based on the design data.

  The rule adding unit 15 adds a rule as follows, for example. First, the rule adding unit 15 designs data corresponding to each wiring pattern included in the dangerous part where it is determined that a wiring defect occurs (line width, distance to adjacent wiring pattern, via diameter, wiring pattern type, etc.). Among these, parameter values relating to each evaluation item are acquired from the wiring design information. Next, the rule adding unit 15 searches for an existing design rule to be evaluated for each parameter value. If there is no existing design rule for evaluating the parameter value, the rule adding unit 15 adds a design rule for the evaluation item. As described above, design rules that are not used in the form of inequalities are stored in advance as unused rules for items that can be evaluated. That is, the upper limit value and the lower limit value of the allowable range for the parameter relating to the evaluation item are stored as values (for example, “−999”) indicating that they are not set. Therefore, the rule adding unit 15 can add a rule by setting a value to an unset upper limit value or lower limit value in the unused rule. Here, the set upper limit value or lower limit value is a value obtained by adding a predetermined offset to the parameter value so that the value of the parameter related to the evaluation item to be additionally used is excluded from the allowable range.

  Similarly, the rule adding unit 15 can also modify an existing rule. In this case, the rule adding unit 15 compares the parameter value related to the evaluation item with the existing rule, and if the parameter value is included in the allowable range in the existing rule, the parameter value is out of the allowable range. Thus, the upper limit value or lower limit value of the allowable range is corrected.

An example is shown below.
First, the storage unit 3 includes design rules 1 to N including usage rules and unused rules, and when the wiring pattern type is via, it is formed in any adjacent wiring pattern (in any of the stacked bodies). It is assumed that the distance to the wiring pattern may be set to the design rule k (where 1 ≦ k ≦ N). Further, the upper limit value and lower limit value of the parameter (distance to the adjacent wiring pattern) in the design rule k are not set (that is, the design rule k is not used). Also, the offset for the parameter representing the distance is set to 100 μm.

  In this case, when the type of the wiring pattern determined to cause the pattern defect is a via and the distance to the adjacent wiring pattern is 1000 μm, the rule adding unit 15 sets the design rule k to the adjacent wiring pattern. Is set to 900 μm. By setting the upper limit value of the distance to the adjacent wiring pattern in this way, the design rule k becomes effective and is used by the rule verification unit 11 in the subsequent processing.

Further, in the design rule j (where 1 ≦ j ≦ N), when the wiring pattern type is land, the distance to the adjacent wiring pattern (which can be any wiring pattern formed in the stacked body) is the design rule. Assume that j (where 1 ≦ j ≦ N) is set. Further, it is assumed that the upper limit value of the parameter (distance to the adjacent wiring pattern) in the design rule j is set to 2000 μm. In this case, when the type of the wiring pattern determined to cause a wiring failure is a land and the distance to the adjacent wiring pattern is 1500 μm, the rule adding unit 15 sets the design rule j to the adjacent wiring pattern. Is set to 1400 μm. Thus, the upper limit value of the distance to the adjacent wiring pattern is corrected, and the corrected design rule j is used by the rule verification unit 11 in the subsequent processing.
Note that the rule adding unit 15 may set a predetermined design rule in advance so as not to be modified.

  Next, an operation flow of the board design support apparatus 1 to which the present invention is applied will be described with reference to FIG. The operation of the board design support apparatus 1 described below is executed by the control unit 10 of the processing unit 4 in accordance with a program read into the processing unit 4.

  First, the processing unit 4 acquires wiring design information from the data input / output unit 2 (step S101). Next, the rule verification unit 11 of the processing unit 4 verifies the acquired wiring design information using the design rule read from the storage unit 3 (step S102). And the rule verification part 11 will investigate the presence or absence of a rule violation, if verification is completed about all the design rules to be used (step S103). If there is a rule violation, the correction unit 14 of the processing unit 4 corrects the wiring design information (step S110).

  On the other hand, if no rule violation is found in step S103, the extraction unit 12 of the processing unit 4 divides the substrate represented by the wiring design information into a plurality of small regions by the dividing unit 121 (step S104). Next, the extraction unit 12 uses the pattern density calculation unit 122 to calculate the pattern density of each small region (step S105). Then, the extraction unit 12 calculates a difference in pattern density between adjacent small regions, and extracts a risk region where a pattern defect may occur based on the difference (step S106). Next, the extraction unit 12 checks whether or not a dangerous part has been extracted (step S107). If no dangerous part is extracted, the process ends because no point to be corrected is found in the wiring design information.

  On the other hand, when a dangerous part is extracted in step S107, the estimation unit 13 of the processing unit 4 performs a flow-structure training analysis on the dangerous part to estimate a displacement amount from the design position of the wiring pattern ( Step S108). Then, the estimation unit 13 determines whether or not a pattern defect occurs based on the estimated displacement amount (step S109). If it is determined in step S109 that a pattern defect will occur, the correction unit 14 corrects the wiring design information (step S110). Then, the control is returned to before step S102, and the processes of steps S102 to S109 are performed again. On the other hand, when it is determined in step S109 that no pattern defect occurs, the board design support apparatus 1 ends the process.

  As described above, the board design support apparatus 1 to which the present invention is applied extracts a dangerous part where a pattern defect may occur based on a change in pattern density on the multilayer board. Then, the board design support apparatus 1 performs a flow-structure coupling analysis on the dangerous part to estimate the amount of displacement from the design position of the wiring pattern, and determines whether or not a pattern defect occurs based on the estimation result. . Further, when it is determined that the pattern defect occurs, the board design support device 1 automatically corrects the design data of the wiring pattern corresponding to the dangerous part determined to cause the pattern defect. For this reason, it is possible to design an appropriate multilayer board without causing problems such as wiring pattern breakage, misalignment between via layers, and insufficient adhesion between layers without trial production of the multilayer board. In addition, since the substrate design support apparatus 1 to which the present invention is applied performs the flow-structure interaction analysis only in a portion where a pattern defect may occur, the analysis does not take a long time and takes a relatively short time. The wiring design information can be verified and corrected.

  The above-described embodiments are for explaining the present invention, and the present invention is not limited to the above-described embodiments.

  For example, in the board design support apparatus 1 described above, the correction unit 14 and the rule addition unit 15 of the processing unit 4 are omitted, so that the wiring design information is not corrected and is used only for the purpose of verifying the wiring design information. You can also In this case, it is preferable to connect a monitor (not shown) to the processing unit 4. The user who uses the board design support apparatus can easily display the presence / absence of a wiring pattern determined to have a pattern defect by the estimation unit 13 and the location of such a wiring pattern on the monitor. This is to make it possible to know the pattern defect location.

  As described above, various modifications can be made within the scope of the present invention according to the embodiment to be implemented.

It is a functional block diagram of the board | substrate design assistance apparatus to which this invention is applied. (A) is a plane schematic diagram of a multilayer substrate, and (b) is an enlarged display diagram of a region 250 of (a). It is a cross-sectional schematic diagram of the multilayer substrate produced. (A) is a cross-sectional schematic diagram of the multilayer substrate before performing an adhesion process, (b) is a schematic cross-sectional view of the multilayer substrate after performing the adhesion process about the same part as (a). It is an operation | movement flowchart of the board | substrate design assistance apparatus to which this invention is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Board | substrate design support apparatus 2 Data input / output part 3 Memory | storage part 4 Processing part 10 Control part 11 Rule verification part 12 Extraction part 121 Dividing means 122 Density calculation means 123 Hazardous part extraction means 13 Estimation part 14 Correction part 15 Rule addition part 200, 300, 400 Multilayer substrate 210 Wiring pattern 260 Small region 310a-e Insulating substrate layer 320a-e Wiring pattern 330 Small region 410 Wiring pattern 420 Via 430 High wiring pattern density region 440, 450 Surrounded by low wiring pattern density region region

Claims (8)

A design support device for a multilayer board formed by forming a laminate in which a plurality of substrates having wiring patterns are laminated in layers, and heating or pressurizing the laminate,
An input unit (2) for acquiring wiring design information of the multilayer substrate;
From the acquired wiring design information, an extraction unit (12) for extracting a dangerous part where a pattern defect may occur by heating or pressurizing the laminate,
Based on the wiring design information, the amount of displacement of the wiring pattern from the design position by heating or pressurizing the laminated body with respect to the wiring pattern included in the dangerous part extracted by the extraction unit (12) And an estimation unit (13) for determining whether or not a pattern defect occurs based on the displacement amount;
A design support apparatus comprising: The extraction unit (12)
Dividing means (121) for dividing the multilayer substrate into a plurality of regions;
Density calculation means (122) for calculating a pattern density representing a degree of including a wiring pattern based on the wiring design information for each of the plurality of regions divided by the dividing means (121);
Dangerous part extraction means (123) for extracting the dangerous part based on the pattern density;
The design support apparatus according to claim 1, comprising:   The dangerous part extraction means (123) sets at least one of the plurality of regions as a region of interest, a pattern density of the region of interest, and a pattern density of any of the regions near the region of interest. The design support apparatus according to claim 2, wherein the dangerous part is extracted based on a difference between the two.   The dangerous part extraction means (123) sets at least one of the plurality of regions as a region of interest, a pattern density of the region of interest, and a pattern density of any of the regions near the region of interest. 3. The design support according to claim 2, wherein when the absolute value of the difference between the two is greater than or equal to a predetermined threshold and the region of interest is included in the predetermined wiring pattern structure, the predetermined wiring pattern structure is extracted as the dangerous part. apparatus.   The correction unit (14) for correcting design data in the wiring design information corresponding to a wiring pattern included in a dangerous part determined to have a pattern defect in the estimation unit (13). The design support apparatus as described in any one of -4.   The correction unit (14) has at least one correction rule, and whether or not the at least one correction rule can be applied based on the design data corresponding to the wiring pattern included in the dangerous part determined to have a pattern defect. The design support apparatus according to claim 5, wherein the design data is corrected based on the correction rule determined to be applicable. And a design verification unit (11) for verifying the wiring design information based on a predetermined design rule;
A rule adding unit (15) for correcting the predetermined design rule or adding a new design rule based on the design data corresponding to the wiring pattern included in the dangerous part determined to have a pattern defect;
The design support apparatus according to claim 5 or 6, comprising: A method for supporting design of a multilayer board formed by forming a laminate in which a plurality of substrates having wiring patterns are laminated in layers, and heating or pressurizing the laminate,
Obtaining wiring design information of the multilayer substrate (S101);
Extracting from the acquired wiring design information a risk site where pattern defects may occur by heating or pressurizing the laminate (S106);
Based on the wiring design information, a displacement amount from the design position of the wiring pattern is estimated by heating or pressurizing the laminated body with respect to the wiring pattern included in the dangerous part extracted by the extraction unit. Step (S108);
Determining whether a pattern defect occurs based on the displacement amount (S109);
A design support method comprising:

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