JPH04354417A - Bi-cmos logic circuit - Google Patents

Abstract

PURPOSE:To prevent the deterioration a in an input output characteristic due to a delay. CONSTITUTION:When a level of an input signal Vin changes from an H to an L level, a PMOS 63 is turned off for a delay time of a delay circuit 64. A base current IBI outputted from a PMOS51 in an input circuit 50 is entirely used for driving a 1st bipolar transistor(TR) 61. After the lapse of the delay time of the delay circuit 64, an NMOS 63 is turned on by an output of the relevant delay circuit 64 and an output voltage Vout is fully swung.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to an inverter circuit composed of a bipolar transistor (Bi) and a CMOS (complementary MOS transistor), a NAND circuit, a NOR circuit, and an exclusive OR circuit. Circuit (E
The present invention relates to Bi-CMOS logic circuits designed to increase the speed of xOR circuits and the like.

0002

2. Description of the Related Art Logic circuits, such as inverter circuits, are known to consist only of bipolar transistors or MOS transistors, but in recent years, in order to increase speed and reduce power consumption, bipolar transistors and CMOS Various circuits have been proposed that combine these. This circuit is called a Bi-CMOS logic circuit. An example is shown in FIG.

FIG. 2 is a circuit diagram showing an example of the configuration of a conventional Bi-CMOS inverter circuit. This inverter circuit has an input terminal 1 into which an input voltage Vin as an input signal is input, and an output circuit 20 is connected to the input terminal 1 via an input circuit 10.

The input circuit 10 is a circuit that inverts the input voltage Vin and outputs complementary first and second base currents IB1 and IB2, and includes a P-channel MOS transistor (hereinafter referred to as PMOS) 11, and N-channel MO
S transistor (hereinafter referred to as NMOS) 12, 13,
It is composed of 14 CMOS chips. PMOS11
and NMOS12 are connected in series between power supply voltage VCC (eg, 5V) and ground potential VSS, and their gates are commonly connected to input terminal 1. Furthermore, NMOS
13 and 14 are connected in series between the output terminal 2 and the ground potential VSS, and their gates are commonly connected to the input terminal 1.

[0005] An output circuit 20 connected to the output side of the input circuit 10 amplifies the first and second base currents IB1 and IB2 to charge and discharge the capacitance of a load circuit 30 connected to the output terminal 2. It is a circuit. This output circuit 20 is a totem pole type circuit, and the power supply voltage VCC and the output terminal 2
a first NPN bipolar transistor 21 connected between the output terminal 2 and the ground potential VSS; and a second NPN bipolar transistor 22 connected between the output terminal 2 and the ground potential VSS.
It is made up of. VB in FIG. 2 is the base voltage of the bipolar transistor 21.

The load circuit 30 connected to the output terminal 2 is
For example, it is composed of a resistor 31 and a capacitor 32.

Next, the operation will be explained.

First, initially, the input voltage Vin is at the logic “L” level.
”, the output voltage Vout is logic “H”. Then, when the input voltage Vin changes from “L” to “H”, N
MOS12, 13, and 14 are turned on, and output terminal 2
The charge of the load circuit 30 connected to the NMOS 13 is drawn out through the NMOS 13. This current flows as the drain current of the NMOS 14 and the base current IB2 of the second bipolar transistor 22. The base current IB2 drives the second bipolar transistor 22, and rapidly extracts charges from the load circuit 30 with a current β (common emitter current amplification factor) times the base current IB2.

[0009] When the output voltage Vout decreases to the base-emitter voltage Vbe of the bipolar transistor 22, the transistor 22 can no longer be driven, but since the NMOS 14 continues to be in the on state, the output voltage Vout eventually becomes approximately It becomes 0V.

Next, when the input voltage Vin changes from "H" to "L", the NMOSs 12, 13, 14 and the bipolar transistor 22 all turn off, and the PMOS 1
1 is turned on. When the PMOS11 is turned on, the drain current of the PMOS becomes the first base current IB1.
The current flows to the base side of the first bipolar transistor 21 as a result. This bipolar transistor 21 charges the capacitor 32 in the load circuit 30 with a current β times that amount.

As described above, the Bi-CMOS inverter circuit is suitable for high-speed operation because it can control a current β times the current that can be supplied by a general CMOS inverter. Moreover, the current consumption during standby when the input voltage Vin is not inputted is almost the same as that of a general CMOS inverter having the same dimensions. Therefore, this Bi-CMOS
An inverter circuit can be said to be an ideal element that can eliminate the disadvantages of conventional circuits constructed only of bipolar transistors or MOS transistors while maintaining their advantages.

However, in the Bi-CMOS inverter circuit shown in FIG. 2, when the output voltage Vout becomes "H", the base-emitter voltage Vb of the bipolar transistor 21
e exists, so the “H” output voltage Vout is VCC
There is a drawback that it stops at -Vbe. This drawback is illustrated in FIG.

FIG. 3 is an input/output characteristic diagram based on a simulation of the Bi-CMOS inverter circuit of FIG. As shown in this figure, when the power supply voltage VCC=5V, the "H" output voltage Vout stops at approximately 4.4V.

[0014] In order to solve this drawback, other conventional Bi
- In FIG. 4 showing a circuit diagram of a CMOS inverter circuit, a normally-on type PMOS 23 is connected between the base and emitter of a bipolar transistor 21.

[0015] In this Bi-CMOS inverter circuit,
Since the base of the PMOS 23 is connected to the ground potential VSS, it functions as a resistor. Therefore, the output voltage Vout
Even if the voltage rises to VCC-Vbe and the bipolar transistor 21 becomes inoperable, the PMOS 23 causes current IP to flow there and continue to charge up, and eventually the "H" output voltage Vout becomes equal to the value of VCC. Become.

[0016]

[Problems to be Solved by the Invention] However, the conventional circuit shown in FIG. 4 also has the following problems.

FIG. 5 is an input/output characteristic diagram obtained by simulation of the circuit shown in FIG.

In the circuit of FIG. 4, when the PMOS 11 is turned on and the first base current IB1 is supplied to the base of the first bipolar transistor 21, the PMOS
23 also flows, and the bipolar transistor 2
The base voltage VB of the bipolar transistor 21 decreases, and the driving ability of the bipolar transistor 21 decreases. Therefore, in the circuit of Figure 4, although the output voltage Vout fully swings, in terms of the input/output delay of the inverter, the delay characteristics are lower than that of the circuit of Figure 2, and the accuracy is lower than that of the circuit of Figure 2. There was a problem, and it was difficult to solve it.

The present invention provides a Bi-CMOS logic circuit which solves the problem of the prior art, which is that the input/output characteristics deteriorate due to delay.

[0020]

[Means for Solving the Problems] In order to solve the above problems, the present invention operates on and off according to an input signal, takes the logic of the input signal, and outputs first and second base currents with opposite phases. a first bipolar transistor connected to the output terminal and amplifying the first base current to charge the output terminal side; and a first bipolar transistor connected to the output terminal and charging the second base current. a second bipolar transistor that amplifies current and discharges the output terminal side;
A delay circuit is provided in a Bi-CMOS logic circuit including a MOS transistor connected between the base of the first bipolar transistor and the output terminal.

The delay circuit has a function of delaying the input signal by a predetermined time to turn on the MOS transistor when the first bipolar transistor is driven by the first base current.

[0022]

[Operation] According to the present invention, Bi-CMOS
Since we have configured a logic circuit, for example, if the input signal is “H”→
When the level becomes "L", the MOS transistor is turned off for a predetermined period of time. During that time, all the first base current output from the input circuit is used to drive the first bipolar transistor. Then, after the delay time by the delay circuit has elapsed, the MOS transistor is turned on by the delay circuit, and the voltage on the output terminal takes full swing.

In this way, the delay circuit delays the ON operation of the MOS transistor, and when the output terminal becomes "H", only the first bipolar transistor is driven in the first half, and the MOS transistor is driven in the second half. As a result, input/output characteristics can be improved. Therefore, the above problem can be solved.

[0024]

[Embodiment] FIG. 1 shows a Bi-
FIG. 2 is a circuit diagram of a CMOS inverter circuit.

This inverter circuit has an input terminal 41 for inputting an input voltage Vin, and an output terminal 42 for outputting an output voltage Vout. An input circuit 50 that inverts the input voltage Vin and outputs complementary first and second base currents IB1 and IB2 is connected to the input terminal 41.

[0026] The input circuit 50 includes a PMOS 51 and an NMO
S52, 53, 54, and the power supply voltage VCC (for example,
5V) and ground potential VSS, PMOS51 and NM
OS52 are connected in series, and their gates are connected to input terminal 4.
1 is commonly connected. Further, NMOSs 53 and 54 are connected in series between the output terminal 42 and the ground potential VSS, and their gates are commonly connected to the input terminal 41. A totem pole type output circuit 60 is connected to the output side of this input circuit 50.

The totem pole type output circuit 60 has a function of amplifying the first and second base currents IB1 and IB2 to charge and discharge the capacitance of the load circuit 70 connected to the output terminal 42. This output circuit 60 is an NPN type first
and second bipolar transistors 61 and 62. The gate of the first bipolar transistor 61 is P
The drains of the MOS 51 and the NMOS 52 are connected, their collectors are connected to the power supply voltage VCC, and their emitters are connected to the output terminal 42, respectively. Second bipolar transistor 62
The gate is connected to the source of the NMOS 53 and the drain of the NMOS 54, the collector is connected to the output terminal 42, and the emitter is connected to the ground potential VSS.

The load circuit 70 connected to the output terminal 42 includes, for example, a resistor 71 and a capacitor 72.

Furthermore, the first bipolar transistor 61
The source and drain of the PMOS 63 are connected to the base and emitter of the PMOS 63, respectively. Furthermore, input terminal 4
1 and the gate of PMOS63, an input voltage Vin
A delay circuit 64 is connected to delay the time for a predetermined period of time. The delay circuit 64 is, for example, a two-stage CMOS inverter 64a.
, 64b.

Next, the operation will be explained.

First, the input voltage Vin of the input terminal 41 is “
When the output voltage is "L", the output voltage Vout of the output terminal 42 is "H".Here, the input voltage Vin is changed from "L" to "H".
When it is set, the NMOSs 52, 53, and 54 are turned on. As a result, the accumulated charge in the capacitor 72 in the load circuit 70 is drawn out through the NMOS 53 and divided into the drain current of the NMOS 54 and the second base current IB2 of the bipolar transistor 62. Then, the bipolar transistor 62 is driven, and the accumulated charge in the load circuit 70 is extracted with a current value β times the base current IB2.

At this time, since the PMOS 51 is in the off state and the base voltage VB of the bipolar transistor 61 is "L", the bipolar transistor 61 is in the off state. Furthermore, since the output voltage of the inverter 64a in the delay circuit 64 is "L" and the output voltage VP of the inverter 64b is "H", the PMOS 63 is also in an off state.

When the output voltage Vout gradually decreases and becomes lower than the base-emitter voltage Vbe of the bipolar transistors 61 and 62, the bipolar transistor 62 turns off, but since the NMOS 54 is on, it eventually turns off. The output voltage Vout becomes 0V.

Next, immediately after the input voltage Vin changes from "H" to "L", the NMOSs 52, 53, and 54 and the bipolar transistor 62 are turned off, but the PMOS 51 is turned on. At this time, the output voltage of the inverter 64a also changes from "L" to "H", but the output voltage VP of the inverter 64b has not changed yet. During this period, PMOS
The first base current I supplied by the on-state of 51
Since all of B1 flows into the base of the bipolar transistor 61, the drop in the base voltage VB is also small. Therefore, the first base current IB1 starts flowing early, and the current value also becomes high. Therefore, bipolar transistor 61 is driven more strongly, causing load circuit 70 to have a large collector current IC.
I will charge it with.

[0035] The output voltage Vout increases and VCC-Vb
When it increases to around e, the driving ability of the bipolar transistor 61 decreases, but at this point, the inverter 64b
The output voltage VP of PMOS63 changes from “H” to “L”.
Turn on. When PMOS63 turns on,
A current IP flows through the PMOS 63, charging up the load circuit 70 to the power supply voltage VCC.

The advantages of this first embodiment will be explained with reference to FIGS. 6 to 8.

FIG. 6 is an input/output characteristic diagram obtained by simulation of the circuit of FIG. 1, FIG. 7 is a current characteristic diagram obtained by simulation of the conventional circuit of FIG. 4, and FIG. 8 is a current characteristic diagram obtained by simulation of the circuit of FIG. 1. . Note that VP in FIG. 6 is the base voltage of PMOS63, and IC in FIGS. 7 and 8.
is the collector current of the first bipolar transistors 21, 61.

Input the rise time of the output voltage Vout 5
0% and output 50%, if the conventional time in FIG. 5 is set to 1, the improvement in FIG. 6 is 0.882. Output 90%
Looking at it in terms of , it can be seen that it has improved by about 20%, from 1 → 0.939 → 0.827. Furthermore, when comparing the current values, in contrast to the conventional diagram shown in FIG. 7, the first base current IB1 in FIG. It can be seen that the current IP flowing through the PMOS 63 rises in the latter half. Therefore, Bi in this example
-The CMOS inverter circuit has improved input/output characteristics compared to the conventional circuit shown in FIG.

FIG. 9 shows a second embodiment of the present invention.
2 is a circuit diagram of a CMOS inverter circuit, in which elements common to those in FIG. 1 are given the same reference numerals; FIG.

This Bi-CMOS inverter circuit is the first
The difference from the embodiment is that instead of the input circuit 50 in FIG.
The point is that an input circuit 50A having a different circuit configuration is provided. This input circuit 50A has a circuit configuration in which the NMOS 52 in the input circuit 50 of FIG. 1 is removed.

[0041] In this Bi-CMOS inverter circuit,
When the input voltage Vin transitions from "H" to "L", the through current flowing from the PMOS 51 to the NMOS 52 in FIG.
It can be used as the base current IB1. Therefore, the time for the output voltage Vout to rise to "H" becomes faster, and as shown in FIG.
The speed is improved.

The advantages of this second embodiment will be explained with reference to FIGS. 10 and 11.

FIG. 10 is an input/output characteristic diagram obtained by simulation of the circuit of FIG. 9, and FIG. 11 is a current characteristic diagram obtained by simulation of the circuit of FIG.

Similar to the first embodiment, when looking at the output rise time at 50% input and 50% output, if the time in conventional FIG. 5 is set to 1, then in FIG. and has improved. Looking at the point of output 90%, it can be seen that the output is improved by about 20% from 1 to 0.939 to 0.827, similar to the first embodiment.

Furthermore, when comparing the current values, in comparison with the conventional diagram shown in FIG. 7, in the present embodiment shown in FIG. It can be seen that the collector current IC flowing through the first bipolar transistor 61 is also large, and the current IP flowing through the NMOS 63 rises in the latter half. Therefore, the first
The speed is further improved compared to the embodiment.

[0046] Note that the present invention is not limited to the above embodiments,
Various modifications are possible. Examples of such modifications include the following.

(a) In the above embodiment, Bi-CMO
Although an example of an inverter circuit was given as an S logic circuit, by changing the input circuits 50 and 50A, NAN
Other Bi circuits such as D circuits, NOR circuits, ExOR circuits, etc.
- It is also possible to apply the NMOS 63 and delay circuit 64 of the above embodiment to a CMOS logic circuit.

(b) Although the delay circuit 64 is constructed from two stages of CMOS inverters, it can also be constructed from other delay means such as a capacitor.

(c) The first and second bipolar transistors 61 and 62 are configured with PNP type transistors, or the NMOS 63 connected thereto is configured with PMOS.
It is also possible to configure

[0050]

As described above in detail, according to the present invention, the delay circuit delays the base current of the first bipolar transistor by a predetermined period of time, and the MOS transistor connected to the first bipolar transistor is activated. Since it is turned on, the time required to follow the voltage change on the output terminal with respect to the input signal becomes faster, and the input/output characteristics are improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a Bi-CMOS inverter circuit showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional Bi-CMOS inverter circuit.

FIG. 3 is an input/output characteristic diagram of FIG. 2;

FIG. 4 is a circuit diagram of another conventional Bi-CMOS inverter circuit.

FIG. 5 is an input/output characteristic diagram of FIG. 4;

FIG. 6 is an input/output characteristic diagram of FIG. 1;

7 is a current characteristic diagram of FIG. 4. FIG.

FIG. 8 is a current characteristic diagram of FIG. 1;

FIG. 9 is a circuit diagram of a Bi-CMOS inverter circuit showing a second embodiment of the present invention.

FIG. 10 is an input/output characteristic diagram of FIG. 9;

FIG. 11 is a current characteristic diagram of FIG. 9;

[Explanation of symbols]

41 Input terminal 42
Output terminal 50, 50A
Input circuit 51 PMOS52, 53
, 54 NMOS 60 Output circuit 61, 62
First and second bipolar transistors

Claims (1)

[Claims] 1. An input circuit having a CMOS configuration, which is turned on and off by an input signal and outputs first and second base currents of opposite phases by calculating the logic of the input signal; a first bipolar transistor that amplifies the first base current to charge the output terminal side; and a second bipolar transistor connected to the output terminal that amplifies the second base current and discharges the output terminal side. a bipolar transistor and a MOS transistor connected between the base of the first bipolar transistor and the output terminal,
In the Bi-CMOS logic circuit, when the first bipolar transistor is driven by the first base current, the input signal is delayed for a predetermined time to
A Bi-CMOS logic circuit characterized by being provided with a delay circuit that turns on an OS transistor.