JPH04335268A - Reproducing device for digital data - Google Patents

Abstract

PURPOSE:To simplify constitution by adding dummy data to reproduced digital data in such a way that the data constitution of two groups added the respective parities of one and the other become the same and execute a processing in the same error processing means by means of C1 and C2 signs. CONSTITUTION:An error correcting circuit 23 detects the error of the C1 sign by means of the check of the C1 parity in digital data inputted with a change- over switch 22 so as to correct the error. Reproduced data where the error is corrected is inputted to a data adding circuit 25 with the change-over switch 24 and dummy data added reproduced data in the circuit 25 is inputted to the circuit 23 again with the switch 22. The circuit 23 detects the error of the C2 sign by means of the check of the C2 parity in the reproduced data so as to correct the error but, at this time, the constitution of the C2 and C1 signs are the same. Thus, an operation and the reproducing processing are executed in the same circuit 23 so as to simplify constitution.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is directed to a video recording medium for recording audio signals recorded together with video signals as digital data.
The present invention relates to a digital data reproducing device suitable for application to TR.

0002

[Background Art] Digital data handled by a digital data reproducing device such as a digital VTR has a correction code added to the recorded data in advance, and based on this correction code, the reproducing device can perform error processing such as error detection and error correction. It's like this.

A product code of C1 parity and C2 parity is known as a data structure to which this correction code is added. An example of this product code is shown in FIG.
The data structure of 0 is the digital audio tape recorder (
DAT), which shows the data structure of one block, and C1 parity is added by calculating the data in the vertical direction of this one block, and C1 parity is added.
1 code, and C2 parity is added in the calculation of data in the horizontal direction, resulting in a C2 code with C2 parity added. In this way, a product code is constructed by adding parity twice both vertically and horizontally. Then, during playback, C1 code and C2 code
By performing code syndrome calculations, it is possible to determine whether an error has occurred in each code. This syndrome operation can be performed, for example, by adding the data that makes up each code, and when the calculated value becomes 0, it can be determined that there is no error in this code series, and when the calculated value does not become 0, it can be determined that there is no error in this code series. It can be determined that this is occurring.

0004

[Problems to be Solved by the Invention] By the way, when a product code is constructed from a C1 code and a C2 code, the data structure is different between the two codes. There is an inconvenience in that two systems of processing circuits, one for the C2 code and the other for the C2 code, are required. That is, as shown in FIG. 11, for example, the reproduced data obtained at the input terminal 51 of the reproduced digital data is supplied to the C1 error correction processing circuit 52, and the C1 error correction processing circuit 52 performs error correction by checking the C1 parity. Perform processing. Then, the reproduced data processed by the C1 error correction processing circuit 52 is supplied to the C2 error correction processing circuit 53, and the C2 error correction processing circuit 53 performs error correction processing by checking C2 parity. is supplied from the output terminal 54 to the subsequent circuit. In this way, processing such as error correction has been performed using a two-stage processing circuit, but the provision of two systems of processing circuits has the disadvantage of complicating the circuit structure of the reproducing apparatus.

An object of the present invention is to simplify the circuit configuration for error processing of reproduced data in a digital data reproducing apparatus.

[0006]

[Means for Solving the Problems] The present invention is a digital data reproducing device for reproducing digital data recorded on a magnetic tape, in which a C1 code to which C1 parity is added and a C2 parity to which C2 parity is added as digital data. In a digital data reproducing device that reproduces product-coded data using a C2 code, the data structure of a series in which one parity is added to the digital data reproduced from a magnetic tape, and the data structure of a series in which the other parity is added. Dummy data is added so that the data structure is the same, and the reproduced digital data to which this dummy data is added is processed by the same error processing means for the C1 code and the C2 code.

[0007]

[Operation] By doing this, the data structure during error processing becomes the same for the C1 code and the C2 code, making it possible to perform reproduction processing with the same error processing means, and using only one system of error processing means. It will be better if you prepare.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 7. In this example, an example in which the present invention is applied to a VTR device that records and reproduces a digital audio signal in a time-sharing manner with a video signal is shown.

In FIG. 1, reference numeral 1 denotes a rotary head drum, and magnetic heads 2 and 3 are arranged on this rotary head drum 1 with an angular interval of 180° from each other. In this case, the rotary head drum 1 is rotated at a frame frequency by a servo circuit (not shown) in synchronization with the luminance signal of the recorded video signal.

A magnetic tape (not shown) is run obliquely at a constant speed over an angular range of just over 221 degrees with respect to the rotating peripheral surfaces of these magnetic heads 2 and 3, and
Video signals are recorded and played back within an angular range of 80°, approximately 3
Digital audio signals are recorded and played back within an angular range of 6°.

The format of the digital audio signal recorded on the magnetic tape and reproduced by the VTR of this example will now be explained. Each block has the data structure shown in FIG. That is, one block consists of 44 symbols, and one symbol each is allocated to a synchronization signal, block address, ID, and parity (parity of block address and ID) in order from the beginning, and the next 36 symbols are allocated to recorded data such as audio data or C2 parity is assigned and the last four symbols are assigned C1 parity. in this case,
Each symbol is composed of 8 bits, and when data is processed by the recording circuit and the reproduction circuit, it is processed as 8-bit parallel data. Then, the data of this block configuration is 22 blocks as one segment,
One frame consists of five segments. For this reason, 1
One frame consists of 10 blocks. The above-mentioned C2 parity is added to each segment to form a product code.

The configuration of one frame is as shown in FIG. 4, and the configuration of one segment is as shown in FIG. 5. That is, of the 22 blocks constituting one segment, data such as voice is assigned to 36 predetermined symbols in 18 blocks (see FIG. 3), and C2 parity is assigned to 36 predetermined symbols in the remaining 4 blocks. Note that the data recording section in FIG. 5 has 38 symbols because two predetermined symbols of the header section are added to the above-mentioned 36 symbols. Then, data of this segment configuration is collected into five segments to form one frame of data shown in FIG. 4. For this one frame of data, C2 parity is assigned to 20 blocks out of 110 blocks. By configuring the recording data in this way, C1 parity functions as a correction code for data in each block, C2 parity functions as a correction code for data in each frame (between blocks), and by adding both parities, Constructed as a product code.

Returning to the configuration of FIG. 1 again, the reproduction signals of the magnetic heads 2 and 3 are supplied to the reproduction amplifiers 5 and 6 via the rotary transformer 4, and the outputs of the reproduction amplifiers 5 and 6 of the respective channels are Supplied to equalizers 7 and 8. Then, the outputs of the equalizers 7 and 8 of the respective channels are supplied to a changeover switch 9 for switching digital audio signals. When the magnetic heads 2 and 3 are located in an angular range of approximately 36° for reproducing the digital audio signal described above, this selector switch 9 selects and outputs the reproduced signal from the magnetic head 2 or 3 within this angular range. let Further, although not shown, another changeover switch selects and outputs a signal reproduced within an angular range of about 180° for reproducing the video signal, and supplies the signal to the video signal reproduction system circuit.

The reproduced signal output from the changeover switch 9 is supplied to a comparator 10 to be converted into binary data, and the output of the comparator 10 is supplied to a demodulation circuit 11. The demodulated signal output from the demodulation circuit 11 is then supplied to the digital signal processing circuit 20.
0 performs various digital processing such as error correction using parity codes, time axis expansion, and deinterleaving. In this case, a memory 15 is connected to the digital signal processing circuit 20, and this memory 15 is used to perform digital processing such as error correction and time axis expansion. This memory 15 has a capacity to store at least one frame's worth of data (one frame's worth of data including dummy data to be described later).

The digital data processed by the digital signal processing circuit 20 is then transferred to the digital/analog converter 1.
2, converted into an analog signal by this digital/analog converter 12, averaged this analog signal by a low-pass filter 13 to obtain a good analog audio signal,
This analog audio signal is supplied to the audio signal output terminal 14.

Next, the configuration of the digital signal processing circuit 20 of this example is shown in FIG.
The demodulated output of
supply to a. The reproduced data obtained at the movable contact 22m of the changeover switch 22 is transferred to the error correction circuit 23.
The error correction circuit 23 performs error correction by parity check. In this case, the error correction circuit 23 performs a parity check on the C1 code to which C1 parity has been added (or the C2 code, which will be described later and has the same configuration as the C1 code), out of the digital data having the frame structure described above. This circuit detects the location where the error occurs and performs error correction. When performing this error correction, data for one frame is temporarily stored in the memory 15 and processed.

[0017] Then, the reproduced data subjected to error correction by the error correction circuit 23 is supplied to the movable contact 24m of the changeover switch 24. In this case, the reproduced data on which the C1 code error has been corrected is supplied to the first fixed contact 24a of the changeover switch 24, and the reproduced data on which the C2 code error has been corrected is supplied to the second fixed contact 24a of the changeover switch 24. Fixed contact 24
Switching control of the movable contact 24m is performed so as to supply the signal to the point b. Then, the first fixed contact 24a of the changeover switch 24
The reproduced data obtained is supplied to a dummy data addition circuit 25, and dummy data is added to the reproduced data. In this case, in this example, "0" data is added as dummy data so that the structure of the C2 code is the same as the structure of the C1 code.

That is, as shown in FIG. 6 by hatching the range of dummy data D0, of the 22 blocks constituting the original data of one segment, 18 blocks to which audio data etc. are allocated, and C2 This inserts 20 blocks of data between the 4 blocks to which parity is assigned, and all 20 blocks are filled with “0”.
Add data. By doing this, the vertical direction (
The number of symbols in the C1 code direction) and the number of blocks in the horizontal direction (C2 code direction) become equal, and the code structure of the C1 code and the code structure of the C2 code become substantially the same. In this case, the position (symbol) to which C1 parity is originally assigned
“0” data is also added to

The reproduced data to which dummy data has been added in this way is supplied from the dummy data adding circuit 25 to the second fixed contact 22b of the changeover switch 22.

Furthermore, the error-corrected reproduced data obtained at the second fixed contact 24b of the changeover switch 24 is
The data is supplied to a deinterleaving circuit 26 and restored (deinterleaved) based on the interleaved data for recording. The output data of the deinterleave circuit 26 is then supplied to an interpolation circuit 27 to perform predetermined interpolation processing. In this case, the memory 15 is also used for processing in the deinterleave circuit 26 and interpolation circuit 27. Then, the interpolation circuit 27
The playback data outputted by the
The signal is supplied to an analog converter 12.

Note that since the memory 15 connected to the digital signal processing circuit 20 handles reproduced data to which dummy data has been added as described above, the memory 15 has an area for storing one frame of data as shown in FIG. Dummy data D0 is prepared in . That is, since 100 blocks of dummy data D0 are added to one frame composed of five segments, an area is set that can store 100 blocks more than one frame of playback data.

Next, the operation of reproducing a digital audio signal in the reproducing apparatus configured as described above will be explained. The digital audio signal demodulated by the demodulation circuit 11 and supplied to the digital signal processing circuit 20 is , is first supplied to the error correction circuit 23 via the changeover switch 22, and in this error correction circuit 23, an error in the C1 code is first detected by syndrome calculation by checking the C1 parity, and error correction is performed at the location where the error occurs. be exposed. and,
The reproduced data output from the error correction circuit 23 after error correction by checking the C1 parity is supplied to the dummy data addition circuit 25 via the changeover switch 24, and dummy data is added to the data of each segment as shown in FIG. Add data. Then, the reproduced data to which the dummy data has been added is again supplied to the error correction circuit 23 via the changeover switch 22, and an error in the C2 code is detected by syndrome calculation based on a C2 parity check. Make corrections. At this time,
Since the C2 code has the same code structure as the C1 code by adding dummy data, errors can be detected using exactly the same syndrome calculation as the C1 code.

[0023] Since the dummy data is all "0" data, the addition of dummy data does not change the syndrome calculation result, and the calculated value is different from when the syndrome calculation is performed on a C2 code to which no dummy data is added. It will be exactly the same.

[0024] Then, the reproduced data on which the C2 code error has been corrected is transferred from the error correction circuit 23 to the changeover switch 2.
4 is supplied to the deinterleave 26, and the deinterleaved playback data is supplied to the interpolation circuit 27,
The interpolated playback data is supplied to the digital/analog converter 12 via the terminal 28.

By performing the reproduction processing of the digital audio signal in this manner, error detection and error correction using the C1 parity and error detection and error correction using the C2 parity are performed in the same error correction circuit 23. Unlike the conventional example shown in FIG. 11, there is no need to connect the error correction circuit (error detection circuit) in two stages, one for C1 parity and one for C2 parity, and the configuration of the reproduced data processing circuit becomes simpler. In the above embodiment, the error correction process and the dummy data addition process were explained as separate circuit blocks, but each block of data is stored in the memory and the stored data is calculated under the control of a microcomputer. Then, error processing such as error detection and error correction may be performed. In this case as well, syndrome calculations can be performed using the same control data, and the configuration for controlling error processing becomes simple.

The block structure (segment structure) of the data shown in the above embodiment is merely an example, and can be applied to data of other structures. For example, one segment consists of 30 blocks as shown in FIG. 8, and one block consists of 27 symbols of audio data (or C2 parity) and 4
C1 parity of the symbol, audio data is allocated to 24 blocks out of 30 blocks, and the remaining 6
In the case of a data configuration in which C2 parity is assigned to a block, dummy data is added as shown in FIG. That is, 24 blocks to which audio data is allocated, and C2
Three blocks of dummy data D0' are added between the six blocks to which parity is assigned, and two symbols of dummy data D0' are added after the four symbols of C1 parity in each block. Also in this case, all dummy data D0' are set to "0" data.

As shown by hatching in FIG. 9, by adding dummy data D0', the code structure of the C1 code and the code structure of the C2 code become the same, and error processing can be performed with the same syndrome calculation. This simplifies the configuration for error handling.

Furthermore, the code structure of the C1 code and the code structure of the C2 code may be made the same by adding dummy data to data having other structures.

[0029]Although the dummy data was all "0" data in the above embodiment, if it does not affect error processing,
Other data (ie, "1" data) may be added.

Further, in the above embodiment, an example was explained in which the present invention was applied to a digital audio signal reproducing circuit of a VTR device, but it can also be applied to various other digital magnetic reproducing devices.

[0031]

According to the present invention, the data structure at the time of error processing is the same for the C1 code and the C2 code, so that both codes can be reproduced by the same syndrome calculation using the same error processing means. Therefore, only one system of error processing means is required, and the configuration of the playback device can be simplified accordingly.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing a reproduction system circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing main parts of FIG. 1;

FIG. 3 is an explanatory diagram showing a block configuration of data in one embodiment.

FIG. 4 is an explanatory diagram showing a frame structure of data in one embodiment.

FIG. 5 is an explanatory diagram showing a segment configuration of data in one embodiment.

FIG. 6 is an explanatory diagram showing a segment configuration of data in one embodiment.

FIG. 7 is a configuration diagram showing a storage area of a memory in one embodiment.

FIG. 8 is an explanatory diagram showing a segment configuration of data according to another embodiment.

FIG. 9 is an explanatory diagram showing a segment configuration of data according to another embodiment.

FIG. 10 is an explanatory diagram showing an example of a product code.

FIG. 11 is a configuration diagram for conventional error correction processing.

[Explanation of symbols]

2, 3 Magnetic head 12 Digital/analog converter 14 Analog audio signal output terminal 15 Memory 20 Digital signal processing circuit 22, 24 Selector switch 23 Error correction circuit 25 Dummy data addition circuit 26 Deinterleave circuit 27 Interpolation circuit

Claims (1)

[Claims] 1. A digital data reproducing device for reproducing digital data recorded on a magnetic tape, the digital data being product encoded using a C1 code to which C1 parity is added and a C2 code to which C2 parity is added. In the digital data reproducing device that reproduces the digital data reproduced from the magnetic tape, the data structure of the series to which one parity is added is the same as the data structure of the series to which the other parity is added. A digital data reproducing device in which dummy data is added so that the dummy data is added, and the reproduced digital data to which the dummy data is added is processed by the same error processing means for the C1 code and the C2 code.