JPH03176867A - Data recording and reproducing device - Google Patents

Abstract

PURPOSE:To securely detect even a data error over the whole block units by providing an error control circuit for error-correcting or error-detecting an output data of a demodulation circuit with an error correction code or an error detection code, added in each block unit. CONSTITUTION:The error correction code or the error detection code is added to the data of the block unit by a 1st means (error control circuit) 11, while an output data of the 1st means 11 is converted in the block unit into other code and modulated by a 2nd means (modulation circuit) 7 in accordance with a previously set modulation table. Then, an output data of the 2nd means 7 is recorded and reproduced by a 3rd means 4, while a reproduced data by the 3rd means 4 is reversely converted in the block unit into the original code and demodulated by a 4th means (demodulation circuit) 10 in accordance with a conversion table, and also a reproduced data in the block unit of other code than in the conversion table is reversely converted into a data of a prescribed value excluding 0. Furthermore, an output data of the 4th means 10 is error- corrected or error-detected by a 5th means 11 with the error correction code or the error detection code, added in the block unit. By this method, even the data error over the whole block units can securely be detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data recording and reproducing apparatus for recording and reproducing digital data on a recording medium such as an optical disk.

[Conventional technology]

When recording and reproducing digital data on an optical disk, etc., an error correction code (FCC) or error detection code (CRC) is applied to each block of data, such as a sector unit.
is added and these data are recorded as a digitally modulated bit pattern.

During playback, the bit pattern is read and demodulated,
Thereafter, data error correction and error detection processing is performed on a block-by-block basis. Thereby, highly reliable reproduction data can be obtained from an optical disc or the like.

In such a data recording/reproducing device, if there is a defect on the recording medium, the original bit pattern is replaced with another modulation pattern different from the original bit pattern in that part, and this modulation pattern becomes a hit pattern for the original digital data. This may result in a bit pattern that cannot exist. Such data errors can be corrected by the error control processing unit, but if data errors can be detected in advance during data demodulation, the error position can be determined, so the so-called "erasure correction"
This makes it possible to improve error correction ability and error detection ability.

There is a method of determining whether or not there is an error pattern in the bit pattern reproduced once and notifying the error control processing section of the error to improve the error correction ability and error detection ability. The demodulation circuit is based on JP-A-63-1.
! It is described in detail in Japanese Patent No. 19429.

This is a data demodulation circuit for a data recording/reproducing device based on the 4/15 modulation method, which converts 8-bit data into a 15-bit data bit pattern and records/reproduces it. If there is a specific pattern '101' in the reproduced bit pattern that cannot exist, it detects this and outputs an error detection signal.Error control processing unit performs error correction and error detection using this error detection signal.

[Problem to be solved by the invention]

According to the above-mentioned conventional technology, the error correction ability and error detection ability are improved for several errors in a series of data to which FCC and CRC are added, such as in the sector unit of an optical disk, but for burst errors, etc. ECC and CR
If all the data in the block to which C is added is incorrect, or if the entire sector data is incorrect due to readout of an unrecorded area due to an error in specifying an area during replacement sector processing, or a disturbance in the adjustment of the reproduction signal, etc. , error correction becomes impossible and is ineffective.

In addition, in the above case, when the bit pattern detected as an error pattern is demodulated by the data demodulation circuit, this will change to other data, but if this data is
Assuming that the data changes to the value "0" in bytes (hereinafter, numbers shown in brackets are decimal numbers), FCC and C
When all data that is error corrected and detected by RC or ECC and CRC has a value of "0",
In principle, the syndrome result obtained by FCC or CRC calculations will also have a value of "0", and therefore it will be determined that there is no error. This poses a major problem in terms of the system, as even though the button contains erroneous data, it is no longer possible to correct the error or even detect the error.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data recording and reproducing apparatus that can solve such problems and reliably detect errors even in data errors that cover entire blocks.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a first means for adding an error correction code or an error detection code to data in units of blocks, and a method for converting output data of the first means according to a preset modulation table. a third means for recording and reproducing the output data of the second means in another code in units of blocks; and converting the data reproduced by the third means back into the original code in accordance with the conversion table in units of blocks; a fourth means for demodulating the code and inversely converting the reproduced data in the block unit of the code not in the conversion table into data with a predetermined value other than 0; and adding the output data of the fourth means in the block unit. and a fifth means for correcting or detecting errors using an error correction code or an error detection code.

[Effect]

The code pattern for each block of recorded data is
Must be one of the code patterns in the modulation table.

Therefore, when this data is reproduced without errors, the original data is restored by performing inverse code conversion according to the block-by-block busy modulation table.
Furthermore, by comparing the code of the reproduced data in units of blocks with the code in the modulation table, it can be determined whether the data in units of blocks is incorrect.

If there is an error in the reproduced data in units of blocks, this reproduced data is inversely converted to data with a value other than "0". As a result, in the error control means, even if all the data in a block is erroneous, all of this data is set to "0".
, it is possible to detect that this block-based data is incorrect.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram showing an embodiment of a data recording/reproducing apparatus according to the present invention, in which 1 is an optical disk, 2 is a spindle motor, 3 is a servo circuit, 4 is an optical head, 5 is a synchronous playback circuit, and 6 is a synchronous playback circuit. Tracking control circuit, 7 is a modulation circuit, 8
1 is an A/D conversion circuit, 9 is a bit detection circuit, 10 is a demodulation circuit, 11 is an error control circuit, 12 is an external interface control circuit, and 13 is a data input/output terminal.

In the figure, a data input/output terminal 13iC is connected to a computer (not shown), and an external interface control circuit 12 controls the interface with the external computer.

When recording data from an external computer, etc., the spindle motor 2 rotates under the control of the servo circuit 3, so that the optical disc 1, which can be recorded and reproduced,
rotates at a predetermined number of rotations.

Data output from an external computer etc. is input from the data input/output terminal 16 and is supplied to the external interface control circuit 12, so that the data transfer speed is adjusted to the optical disc 1.
controlled so that it is suitable for recording. The data controlled by the external interface control circuit 12 in this way is supplied to the error control circuit 11 and is FCC-controlled in sector units.
and CRC are added, and further supplied to the modulation circuit 7 and subjected to bit pattern conversion so that the unit bit pattern becomes a pattern of a predetermined number of bits on the optical disc 1, and then supplied to the optical head 4 and recorded on the optical disc 1. recorded.

Here, 4/11 modulation is used as the modulation method. This converts %1 byte of data into an 11-bit bit pattern.

One byte of data has 256 bit patterns of hexadecimal numbers (00) to (FF) (hereinafter, numerical values shown in parentheses are hexadecimal numbers). Furthermore, as an 11-bit bit pattern, 4 channel bits out of 11 channel bits (2° pit, 21 bit, . . . , 210 bit) are converted into bits (i.e., I) on optical disc 1.
11# bit). There are C4==530 such 11-bit bit patterns, and 256 different bit patterns are selected from these and made to correspond to the 256 bit patterns of the 1-byte data, respectively.

Hereinafter, the bit pattern consisting of 256 11 bits selected in this way will be referred to as a modulation pattern, and an example of this modulation pattern is shown in FIG. However, in the same figure, 0 to
The numerical value 255 is a value expressed in decimal notation of one byte of data, and indicates the correspondence between the value of one byte of data and the corresponding modulation pattern. For example, in FIG. 3(a), 1 byte of data with the value "0" is sent to @10010010010 by the modulation circuit 7 (FIG.
' is the modulation pattern. In Figure 3 (a), the value is "0" ~
[The modulation pattern for 1 byte of data of 127J is shown, and (b) of the same figure shows the modulation pattern for 1 byte of data of 127J.
It shows a modulation pattern for byte data.

Returning to FIG. 1, during reproduction, the spindle motor 2 rotates under the control of the servo circuit 3 to rotate the optical disk 1, and the optical head 4 sends a signal (bit pattern) representing a bit pattern based on a modulation pattern from the optical disk 1. signal) is played.

This bit pattern signal has a distorted waveform and becomes an analog signal, and is digitized into 8 bits for each channel bit period of the modulation pattern by the A/D conversion circuit 8 and converted to a digital signal, and then sent to the pit detection circuit. 9. Further, the bit pattern signal output from the optical head 4 is also supplied to a synchronization reproduction circuit 5, and a synchronization signal of the channel bit period is reproduced.

Bit detection circuit? Then, using the synchronization signal from the synchronization reproducing circuit 5, the "1" bit in the modulation pattern (that is, the bit on the optical disk 1) is determined from the value of the input 8-bit digital data, and the modulation pattern is Detect. This modulation pattern is supplied to the demodulation circuit 10, where it is converted and demodulated into the original 1-byte data according to the modulation table shown in FIG. 3.However, the supplied modulation pattern is other than the modulation pattern shown in FIG. , @11110oo
oooo'), 1 byte of specific pattern data is output as an error detection signal. This error detection data is a bit pattern with a value of "255".

The output data of the demodulation circuit 10 is transferred to the error control circuit 11. In the chatter control circuit 11, the supplied data is collected in units of sectors, and error correction processing by ECC and error detection processing by CRC are performed in each sector.

The error detection signal representing the error that could not be corrected by the data processed in this way and the error correction processing by the error detection processing is the data that is transmitted from the data input/output terminal 13 after the transfer rate is converted by the external interface control circuit 12. It will be transferred to a computer etc. that will not be used.

Note that during playback, the tracking control circuit 6 controls the optical disc 1.
The tracking control signal recorded in the servo circuit 3 is reproduced to control the servo circuit 3 to perform tracking control.

As described above, in this embodiment, even if an unrecorded area is read due to a burst error or an error in the readout area specification and data is erroneous over the entire block, the demodulation circuit 10 detects this error and changes the value. is “0”
”, the error control circuit 11 can perform reliable error detection.

FIG. 5 is a block diagram showing an embodiment of the pit detection circuit 9 in FIG.
is a shift register, 17 to 24 are registers, 25 is a comparison selection circuit, 26 is a comparison circuit, 27 is a register control circuit,
27 is an OR circuit, and 29 is an output terminal.

In the figure, the input terminal 14 is connected to the A/D conversion circuit 8 (
Parallel 8-bit data A from FIG. 1) is input. This parallel 8-bit data A is input at a channel bit period of an 11-bit modulation pattern, and is input to registers 17 to 2.
0 and is supplied to the comparison circuit 26.

Registers 17 to 20 are 8-bit registers, and are controlled by register control circuit 2b to record data A from input terminal 14 (hereinafter referred to as input data). The comparison and selection circuit 25 selects the minimum value data among the data recorded in the registers 17 to 20, and the selection data B and the input data A are compared in the comparison circuit 26. The register control circuit 27 operates according to the comparison result signal C from the comparison circuit 26, and when the input data A is larger than the selection data B, the register control circuit 27 selects one of the registers 17 to 20 that records the selection data B. comparison selection circuit 25
This register is rewritten with this input data, and when input data A is smaller than selection data B, any register 17 to 2 is
0 also prevents data from being rewritten. This results in 1
When one digitized bit pattern signal consisting of one bit is input from the input terminal 14, K is the four digital values representing the bits of this bit pattern signal (i.e., "1# bit of the modulation pattern)". The signals are recorded in shift registers 17 to 20, respectively.

On the other hand, the synchronization signal E reproduced by the synchronization reproduction circuit 5 is supplied from the input terminal 15 to the shift register 16 . The shift register 16 has 11 output terminals, and shifts the supplied synchronizing signal E at the channel bit period of the 11-bit bit pattern signal A, sequentially starting from the 11 output terminals. Therefore, the shift register 16 outputs parallel 11-bit data F at the channel bit period. In this output data F, one channel bit is always a '1' bit, and in the order of output, the first channel bit, the second channel bit, etc.
The "1" bit is transferred in the order of... and the synchronization signal E
When input, the first channel bit becomes 1'' bit again.

Output data F of the shift register 16 is simultaneously supplied to 11-bit registers 21-24. These registers 2
1 to 24 are also controlled by the register control circuit 27.

That is, the register control circuit 27 now controls the register 17.
At the same time, the output data F of the shift register 16 is recorded in the register 21.

Similarly, when registers 18, 19 or 20 are rewritten, output data F of shift register 16 is simultaneously recorded in registers 22, 25 or 24.

Therefore, for example, if the digital value of the first channel bit of the pit pattern signal A is recorded in the register 18, only the first channel bit is recorded in the register 21. Ru. Therefore, if the bit pattern signal A input from the input terminal 14 is "10010010010", then the register 21 has, for example, "1oooooooooooo".
The data F of pattern 0001000 is in the butter register 22 of ', and the data F of pattern 0000 is 0 in the register 23.
Data F with a pattern of "0000010000" and data F with a pattern of "00000000010" are respectively recorded in the register 24.

The respective data recorded in these registers 21 to 24 are logically summed for each channel bit of the same rank by an OR circuit 28. As a result, the modulation pattern G of the 11-bit pattern "10010010010" is obtained at the output terminal 29.

As described above, the registers 17 to 20, the comparison selection circuit 25
, the comparison circuit 26 and the register control circuit 27 detect the channel bits representing the bits of the input pit pattern signal A and their timing, and based on this,
Registers 21-24. The OR circuit 28 obtains a bit position detection signal of a modulation pattern representing one happy pit position.

FIG. 2 is a block diagram showing a specific example of the demodulation circuit 10 in FIG. In the switching circuit, 55 and 56 are output terminals.

In the same figure, output data G of a bit detection circuit 9011 bits is input from an input terminal 30, and is input to a data conversion circuit 6.
1 and the error pattern detection circuit 52. The data conversion circuit 51 converts the bit pattern of the input data G into a third
Compare it with the bit pattern in the modulation table shown in the figure,
When the bit pattern of this input data G is in this modulation table, the corresponding 8-bit data H
Convert to In addition, the error pattern detection circuit 62 detects a bit pattern of input data G with an 11-bit bit pattern (hereinafter referred to as an error pattern) in which only four channel bits are "1# bits" and is not in the modulation table of FIG. When the input data G is in any of these error patterns, the input data G is determined to be an error and an error detection signal I is output. Pattern Ha4.C
There are 4-360 modulation patterns, and there are 2 modulation patterns in Figure 3.
There are 8-256 patterns, so there are 660-25 error patterns.
There are 6=74 ways.

The switching circuit 64 selects the output data H of the normal data conversion circuit 61 and outputs the output data H from the output terminal 65 to the entertainment control circuit 11 (first
When the error pattern detection circuit 32 outputs an error detection signal, the fixed data generation circuit 66 selects fixed value data other than "0", that is, fixed data J. and is supplied to the error control circuit 11.

This fixed data J is, for example, the value 1-255 given earlier.
This is the 8 pit data of j.

Note that the error detection signal I is also transmitted from the output terminal 66 to the first
The signal is supplied to the error control circuit 11 shown in the figure.

3 is a block diagram showing another specific example of the demodulation circuit 10 in FIG. 1, 37 is an input terminal, 58 is a register, and parts corresponding to those in FIG. 2 are given the same reference numerals and are duplicated. Omit the explanation.

In the figure, the normal switching circuit 34 is the data conversion circuit 51.
The output data of H is selected. The output data L of the switching circuit 34 is supplied from the output terminal 35 to the error control circuit 11 (FIG. 1) and also to the register 38, and is supplied to the clock K having the same period as the input data G from the input terminal 67. recorded by. Therefore, register 68
This means that the data outputted immediately before the data H currently outputted from the data conversion circuit 61 is always recorded.

Here, when the error detection signal is output from the error pattern detection circuit 32, the switching circuit 64 selects the output data of the register 68 and sends it to the error control circuit 11 via the output terminal 35.
It is also supplied to the register 38. As a result, although the input data G has an error, during the period when such data is being input, the output data H of the data conversion circuit 31 for the correct input data G immediately before the input data G with the first error is repeatedly It will be sent to the error control circuit 11.

As described above, in this specific example, instead of using fixed data as the error pattern as in the specific example shown in Figure 2, the correct 11-bit data immediately before the imposed 11-bit data G is demodulated. This is 8-bit data. In the embodiment shown in FIG. 1 using this specific example, when image data is handled as an application for data to be recorded and reproduced, the error correction control circuit 11 (FIG. 1) corrects the previous value of data that cannot be error-corrected. This makes errors less noticeable.

FIG. 4 is a block diagram showing still another specific example of the demodulation circuit 10 in the 11th mode, in which 39 is an error pattern conversion circuit, and parts corresponding to those in FIG. 2 are given the same reference numerals and are duplicated. The explanation will be omitted.

In the figure, an error pattern conversion circuit 69 is shown.

When the modulation pattern of input data G is not in the modulation table shown in Fig. 3, an error detection signal is output and demodulation is performed for the modulation pattern in the modulation table shown in Fig. 3 whose Hamming distance is closest to the modulation pattern of this error. Data M
(However, the value of this demodulated data is not "0"). When the switching circuit 64 receives the tampering detection signal l, it selects the output data M of the error pattern conversion circuit 39 and sends it from the output terminal 35 to the error control circuit 11 (FIG. 1).

As described above, in this specific example, since the error modulation pattern is converted to the demodulation pattern for the modulation pattern closest to it, the probability that erroneous reproduced data is converted to correct data increases, and the data error correction rate increases. improves.

In addition, in the above embodiment, the modulation method is the 4/11 modulation method, but other modulation methods may be used.
Furthermore, it goes without saying that the present invention can be applied to all systems that modulate and demodulate digital data added with FCC or CRC.

〔Effect of the invention〕

As explained above, according to the present invention, ECC and CRC
Even if the data in units of blocks to which is added is scattered throughout, the error can be reliably detected.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the data recording/reproducing apparatus according to the present invention, FIGS. 2 to 4 are block diagrams showing specific examples of the demodulation circuit in FIG. 1, and FIG. FIG. 3 is a block diagram showing a specific example of a bit detection circuit in the embodiment shown in FIG. 1. FIG. 3 is a diagram showing an example of a modulation table used in the embodiment shown in FIG. 1... Optical disk 4... Optical head 7... Modulation circuit 8... A/D conversion circuit 9... Pit detection circuit 10... Demodulation circuit 11... Error control circuit 61... Data conversion circuit 32...Error pattern detection circuit 33...Fixed data generation circuit 64...Switching circuit 38...Register 39...Error pattern conversion circuit. 63: 11oooooo1o1 127: 10110000010 61I ¥1 Cb) 1 2 110000001in

Claims (1)

[Claims] 1. A first means for adding an error correction code or an error detection code to data in units of blocks, and converting the output data of the first means in units of blocks according to a preset modulation table. a second means for converting and modulating the output data of the second means; a third means for recording and reproducing the output data of the second means; and a third means for recording and reproducing the output data of the second means; a fourth means for inversely converting and demodulating the original code, and inversely converting the reproduced data of the block unit of the code not in the conversion table into data of a predetermined value other than 0; and output data of the fourth means. a fifth means for correcting or detecting an error using an error correction code or an error detection code added to each block. 2. The data recording and reproducing apparatus according to claim 1, wherein the data of the predetermined value other than 0 obtained by the inverse transformation by the fourth means is data of a fixed value. 3. In claim 1, the data of the predetermined value other than 0 obtained by inverse transformation by the fourth means is the data obtained by inverse transformation last among the data already demodulated and obtained according to the conversion table. A data recording/reproducing device characterized in that the data has the same value as the data. 4. In claim 1, the data of the predetermined value other than 0 obtained by the inverse transformation by the fourth means is such that the reproduced data having the closest Hamming distance on the conversion table to the original reproduced data of the data is the one in the conversion table. A data recording/reproducing device characterized in that the data is inversely converted according to the following.