JP2622953B2 - Malfunction detection method for digital recording / reproducing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In order to check the operation of a digital data recording / reproducing apparatus using an error correction code, a known data signal is supplied from a host to an encoding circuit, and interleaving in the encoding circuit is performed. In addition to storing in a memory, a check code is created in this encoding circuit, added to the known data, and modulated, demodulated and decoded to detect a malfunction.

Further, in order to shorten the processing time, the addition of the error correction code may be performed during transmission or reception of data.

[Industrial applications]

The present invention relates to a system for inspecting a malfunction of a recording / reproducing apparatus for recording / reproducing digital data on a high-density recording medium such as an optical disk or a magneto-optical memory.

[Conventional technology]

In order to check the digital data recording / reproducing apparatus for abnormalities, known data is supplied from the host, and the recording / reproducing apparatus performs recording / reproduction, and the reproduced data is compared with the known data. A loop-back method of checking for the presence or absence of a malfunction is performed.

[Problems to be solved by the invention]

In this conventional inspection method, it is necessary to transfer data via a bus connecting the host and the controller. If this bus is a bidirectional bus, both input and output data must be transferred simultaneously. Also, when using a pair of unidirectional buses, it is not possible to simultaneously perform input and output of memory on the host side, so it is necessary to reduce the operation speed of the circuit and provide a time difference between the input and output signals, etc. Different timing was needed.

[Means for solving the problem]

The present invention provides a controller (1) for transferring digital data to and from a host, and an encoding circuit (2) for adding a check code for error detection and error correction to data output from the controller (1). ), A modulation circuit (3) for modulating the data signal to which the check code is added, and a recording device (4) for recording and reproducing the modulated data signal.
A demodulation circuit (5) for demodulating a data signal reproduced from the recording device (4); and a decoding circuit for correcting and detecting a data error from the data of the demodulated data signal and the check code. (6) that outputs data decoded by the decoding circuit (6) to the controller (1), transfers data from the controller (1) to the encoding circuit (2), In a malfunction detection method in a digital recording / reproducing apparatus in which data transfer from the controller to the controller is performed at the same time, an interleave memory (8) for storing data output from the controller (1) to the encoding circuit (2). ) And a loop-back switch for switching the output of the modulation circuit (3) to either the recording device (4) or the demodulation circuit (5). A known digital data is input from the host via the controller (1), the input known digital data is stored in the interleave memory (8), and the known digital data is stored in the interleaved memory (8). Correspondingly, some of the codes of a plurality of correction sequences in the check code formed by the coding circuit (2) are stored in the interleave memory (8) in a manner of adding them to the known digital data. Thereafter, the output of the modulation circuit (3) is connected to the demodulation circuit (5) by the loopback switch (7), and in this state, the codes of the plurality of correction sequences in the check code are read from the interleave memory (8). The known digital data to which a part of the symbols is added is output to the modulation circuit (3). When the force, to form the remaining sign of the sign of the plurality of correction sequence in the check code by the encoding circuit (2),
The above-mentioned known digital data to which a part of codes of a plurality of correction sequences in the check code outputted to the modulation circuit (3) is added is further added.

(Operation)

Therefore, the known digital data for inspection is temporarily stored in an interleave memory, a part of the check code is added to the digital data stored in the interleave memory, and then the digital data is read out from the interleave memory, modulated and read. At the time of reading data for modulation, the remaining check code is further added, the modulated data is demodulated, the demodulated data is decoded, and the data obtained thereby is output to the controller. The time required for the additional processing can be reduced, and the inspection processing can be performed quickly.

〔Example〕

FIG. 1 shows an example of a recording / reproducing apparatus to which the present invention is applied, and an encoding circuit 2 for creating and adding a correction code for performing error correction or error detection to data from a controller 1; A modulation circuit 3 for modulating a data signal to which a correction code is added from a circuit 2 for recording / reproducing with a recording device 4, and an output of the modulation circuit 3 is directly connected to an input of a demodulation circuit 5 for inspection. A loop-back switch 7 for constituting a loop-back circuit; and a decoding circuit 6 for performing error correction or error detection of data by using a correction code of a reproduced signal and supplying the data to the controller 1. The controller 1 transfers data to and from a host (not shown) via a bus.

The modulation circuit 3 further adds a synchronization signal to the data signal, and the demodulation circuit 5 notifies the controller 1 of the occurrence of the error by using a synchronization error flag if there is an error in the synchronization signal. Indicates that an error is detected, a flag is set, and the occurrence of an error is notified to the controller 1.

In this embodiment, as a code for correcting data errors, for example, as described in the magazine “Radio Technology”, March 1983, pages 167 to 169,
A well-known cross-interleaved Reed-Solomon code (hereinafter referred to as CIRC) is used. In this CIRC, C1, C2
A two-series correction sequence code called a sequence number is used.

FIG. 2 shows an example of an encoding circuit of the recording / reproducing apparatus shown in FIG. 1, which comprises an input register 11, an output register 12, and an interleave memory 13 connected to a data bus 10; Are stored in the input register 11 and then stored in the reinterleave memory 13 at the address specified by the memory write address counter 17.

When using check codes such as C ₁ and C ₂ parity, C ₁
C ₁ parity and by the encoder 14, C ₂ encoder 15
Generates a C ₂ parity, C ₁ encoder address counter 1
8, C ₂ writes these check code to the address of the specified interleaved memory 13 by the encoder address counter 19.

In the next step, this interleaved memory 13
When reading from memory is instructed, memory read counter 1
6, from the address indicated by the C ₁ encoder address counter 18, C ₂ encoder address counter 19,
Data, C ₁ parity and C ₂ parities is read from the data bus 10 via the output register 12 is sent to the modulation circuit 3.

In the first embodiment of the present invention, the data from the controller 1 is written to the interleave memory 13 in the first step as described above without using the check code,
This data is read by the next read command.

In the second embodiment of the present invention, as shown in FIG.
Tailored to the storage capacity, # 1 and # when the two sectors of data 2 is supplied to the coding circuit 2 at the same time, generates a check code C _1, C ₂ by C ₁ encoder 14 and C ₂ encoder 15 from the data Then, it is stored together with the data in the interleave memory 13 as described above. Then, in the second step, the data and
The C ₁ and C ₂ check codes are read out, and the C ₁ parity and C ₂ parity are decoded by the decoding circuit 6 via the modulation circuit 3, the loopback switch 7 and the demodulation circuit 5 to correct or detect data errors, and the data is corrected. At the same time, a loopback output to the controller 1 is executed.

In this embodiment, since the generation of C ₁ parity is performed by interleaving, to not be immediately coded from the data is input, the generation of further C ₂ parities this
Since C ₁ parity generation of can not generate a not from the end, results in a delay in the first step of the process.

To reduce this delay, in the third embodiment of the present invention, as shown in FIG. 4, the generation of check codes in the first step, C ₁ parity for some of the data of # 1 sector and performed for C ₂ parity only, #
Generation of C ₁ parity and C ₂ parity for the remaining portion and # 2 sectors of a sector to perform in the second step. In this case, the time required for data transfer from the controller 1 to the encoding circuit 2 is the same as that of the second embodiment, and the time required for the second step of performing loopback is not significantly affected.

Further, as a fourth embodiment, as shown in FIG.
The generation of the C ₁ and C ₂ parities can all be performed in the second step.

〔The invention's effect〕

As described above, according to the present invention, known digital data for inspection is temporarily stored in an interleave memory, and a part of a check code is added to the digital data stored in the interleave memory. The digital data is read out from and modulated, and at the time of reading out the data for the modulation, the remaining check code is further added, the modulated data is demodulated, the demodulated data is decoded, and the data obtained thereby is obtained. Since the data is output to the controller, the time required for the process of adding the check code can be reduced, and the effect that the check process can be performed quickly is obtained.

[Brief description of the drawings]

1 is a diagram showing a configuration of a recording / reproducing apparatus to which the present invention is applied, FIG. 2 is an embodiment of an encoding circuit, and FIGS. 3, 4, and 5 are implementations of an inspection system according to the present invention. It is a timing chart showing an aspect. 1 is a controller, 2 is an encoding circuit, 3 is a modulation circuit, 4
Is a recording device, 5 is a demodulation circuit, 6 is a decoding circuit, 7 is a loopback switch, and 8 is an interleave memory.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Osamu Adachi 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Ricoh Co., Ltd. (72) Inventor Masamitsu Suzuki 1-3-6 Nakamagome, Ota-ku, Tokyo Ricoh Co., Ltd. (56) References JP-A-59-221044 (JP, A) JP-A-59-98263 (JP, A) JP-A-60-246066 (JP, A)

Claims (1)

(57) [Claims] A controller for transferring digital data to and from a host, and an encoding circuit for adding a check code for error detection and error correction to data output from the controller. 2), a modulation circuit (3) for modulating the data signal to which the check code is added, and a recording device (4) for recording and reproducing the modulated data signal.
A demodulation circuit (5) for demodulating a data signal reproduced from the recording device (4); and a decoding circuit for correcting and detecting data errors from the data of the demodulated data signal and the check code. (6) that outputs data decoded by the decoding circuit (6) to the controller (1), transfers data from the controller (1) to the encoding circuit (2), In a malfunction detection method in a digital recording / reproducing apparatus in which data transfer from the controller to the controller is performed non-simultaneously, an interleave memory (8) for storing data output from the controller (1) to the encoding circuit (2). ) And a loopback switch for switching the output of the modulation circuit (3) to either the recording device (4) or the demodulation circuit (5). A known digital data is input from the host via the controller (1), the input known digital data is stored in the interleave memory (8), and the known digital data is stored in the interleave memory (8). In the interleaving memory (8), a part of codes of a plurality of correction sequences in the check code formed by the coding circuit (2) corresponding to the known digital data is added to the known digital data. After that, the output of the modulation circuit (3) is connected to the demodulation circuit (5) by the loopback switch (7). The known digital data to which some of the codes are added is output to the modulation circuit (3), and At the time of output, the encoding circuit (2) forms the rest of the codes of the plurality of correction sequences in the check code, and outputs a plurality of correction codes in the check code to be output to the modulation circuit (3). A malfunction detection method in a digital recording / reproducing apparatus, wherein a further code is added to the known digital data to which a part of codes of a series is added.