JPH04324103A - Digital data reproducing device - Google Patents

Abstract

PURPOSE:To improve the error rate of the reproduced data by optimizing the characteristic of the equalizer at the time of reproducing the digital data recorded magnetically. CONSTITUTION:The equalizers equalizing the reproduced data that the product encoding is performed by a C1 parity and a C2 parity are provided for plural systems (equalizers 8, 9) by changing the characteristics of them respectively. The reproduced data is made by selecting good data from the reproduced digital data of each system equalized by the equalizers 8, 9 by the C1 parity check, by selecting good data by the C2 parity check and by selecting the optimum reproduced digital data from two pieces of data selected by the both parity checks.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is directed to a video recording medium for recording audio signals recorded together with video signals as digital data.
The present invention relates to a digital data reproducing device suitable for application to TR.

0002

2. Description of the Related Art In digital data reproducing apparatuses such as digital VTRs, it is necessary to equalize reproduced signals using an equalizer in order to reduce the error rate of reproduced data. This reproduction equalization reduces inter-symbol interference and improves the error rate, but it largely depends on the characteristics of the recording circuit and the characteristics of the magnetic tape to be recorded. For example, when reproducing digital data recorded on a certain magnetic tape, as shown in Figure 9, when the equalizer characteristic is a, the error rate is the lowest and good reproduction is possible. The value of a changes depending on the characteristics of the magnetic tape and the recording conditions. Therefore, in order to always play with the lowest error rate, when starting playback,
It is conceivable to detect the reproduction state such as the error rate and adjust the equalizer characteristics so as to obtain the best reproduction state.

0003

[Problem to be Solved by the Invention] However, when automatically adjusting the equalizer characteristics in this way, the adjustment is made so that the error rate etc. are good during actual playback. There was an inconvenience that it took time for the equalizer characteristics to become optimal. That is, there is no equalizer that automatically optimizes its characteristics immediately upon starting playback. In addition, the optimal equalization state always changes depending on the recording signal condition, and even if the equalizer characteristic is automatically adjusted, for example, as shown in FIG. 9, the optimum error rate will always be achieved with this characteristic was not necessarily obtained.

An object of the present invention is to always optimize the characteristics of an equalizer in a digital data reproducing device.

[0005]

[Means for Solving the Problems] The present invention is a digital data reproducing device for reproducing digital data recorded on a magnetic tape, for example as shown in FIG. In a digital data reproducing device that reproduces product-encoded data, multiple systems of equalizers, each with different characteristics, are prepared to equalize the digital data reproduced from the magnetic tape.
The reproduction digital data of each system equalized by the plurality of equalizers is subjected to syndrome calculation using C1 parity, and based on the syndrome calculation result using this C1 parity, the reproduction digital data of the optimum system is selected and the first In addition to creating a data group with a frame structure of Selecting the reproduced digital data as a data group of a second frame structure,
Furthermore, from the data groups of the first and second frame structures, the optimum system of reproduction digital data is selected as a data group of a third frame structure, and this data group of the third frame structure is used as reproduction data. This is what I did.

[0006]

[Operation] In this way, optimal data is individually selected based on the C1 parity and C2 parity of the reproduced digital data, and further optimal data is selected from the individually selected data. This means that the optimum system of equalizer is selected for each bit, and digital data equalized by the equalizer with the optimum characteristics is always reproduced.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 7. In this example, an example in which the present invention is applied to a VTR device that records and reproduces a digital audio signal in a time-sharing manner with a video signal is shown.

In FIG. 1, reference numeral 1 indicates a rotary head drum, and magnetic heads 2 and 3 are arranged on this rotary head drum 1 with an angular interval of 180° from each other. In this case, the rotary head drum 1 is rotated at a frame frequency by a servo circuit (not shown) in synchronization with the luminance signal of the recorded video signal.

A magnetic tape (not shown) is run obliquely at a constant speed over an angular range of just over 221 degrees with respect to the rotating peripheral surfaces of these magnetic heads 2 and 3, and
Video signals are recorded and played back within an angular range of 80°, approximately 3
Digital audio signals are recorded and played back within an angular range of 6°.

[0010] Here, the format of the digital audio signal recorded and played back by the VTR of this example will be explained.
Each block has the data structure shown in FIG. That is, 1
A block consists of 44 symbols, and one symbol each is assigned to a synchronization signal, block address, ID, and parity (parity of block address and ID) in order from the beginning. Recorded data such as audio data or C2 parity is allocated to the next 36 symbols. C1 parity is assigned to the last four symbols. In this case, each symbol is composed of 8 bits, and when data processing is performed in the recording system circuit and the reproduction system circuit, it is processed as 8-bit parallel data. A plurality of blocks of data having this block configuration are collected into one frame, and the above-mentioned C2 parity is added to each frame. In this case, C1 parity is a correction code for data within a block, while C2 parity is a correction code for data between blocks, and is configured as a product code by adding both parities.

To explain this product code, an example of data using the product code (the configuration is different from this example) is shown in FIG.
The data structure shown in FIG. 6 is applied to a digital audio tape recorder (DAT), and 1
The configuration of a block is shown, and C1 parity is added by calculating data in the vertical direction of one block, and C2 parity is added by calculating data in the horizontal direction. In this way, a product code is constructed by adding parity twice both vertically and horizontally.

Returning to the configuration of FIG. 1 again, the reproduction signals of the magnetic heads 2 and 3 are supplied to the reproduction amplifiers 5 and 6 via the rotary transformer 4, and the outputs of the reproduction amplifiers 5 and 6 of the respective channels are It is supplied to a changeover switch 7 for switching digital audio signals. When the magnetic heads 2 and 3 are located within an angular range of about 36° for reproducing the digital audio signal described above, this selector switch 7 selects and outputs the reproduced signal from the magnetic head 2 or 3 within this angular range. let Further, although not shown, another changeover switch selects and outputs a signal reproduced within an angular range of about 180° for reproducing the video signal, and supplies the signal to the video signal reproduction system circuit.

The reproduced signal output from the changeover switch 7 is then supplied to two equalizers 8 and 9. These two equalizers 8 and 9 have different equalization characteristics,
The outputs of the equalizers 8 and 9 are supplied to separate comparators 10 and 11, respectively, to convert them into binary data, and the outputs of the comparators 10 and 11 are sent to separate demodulation circuits 1 and 11, respectively.
2 and 13. In the following description, the circuit of equalizer 8 → comparator 10 → demodulation circuit 12 will be referred to as a first system, and the circuit of equalizer 9 → comparator 11 → demodulation circuit 13 will be referred to as a second system.

The demodulated signals output from the demodulation circuits 12 and 13 of both systems are supplied to the data selection circuit 20. The reproduced data selected by the data selection circuit 20 is then supplied to the digital signal processing circuit 14, which performs various digital processing such as error correction using parity codes, time axis expansion, and deinterleaving. In this case, the digital signal processing circuit 14 has a memory 15.
is connected, and this memory 15 is used to perform processing such as expansion of the time axis.

The digital data processed by the digital signal processing circuit 14 is then transferred to the digital/analog converter 1.
6, the digital/analog converter 16 converts the signal into an analog signal, the low-pass filter 17 averages the analog audio signal to produce an analog audio signal, and the analog audio signal is supplied to the audio signal output terminal 18.

Next, the configuration of the data selection circuit 20 and its vicinity is shown in FIG. 2. The reproduced signal obtained at the output terminal 7a of the changeover switch 7 is supplied to the first system equalizer 8 The output of the equalizer 8 of the system is supplied to the comparator 10 to convert it into binary data, and this binary data is supplied to the D flip-flop 19a, where the clock extraction circuit 19 extracts the clock from the reproduced signal. Performs synchronized data detection and converts it into digital data. Then, the detected digital data is supplied to the demodulation circuit 12, and the digital data demodulated by the demodulation circuit 12 is supplied to the memory 21 and the syndrome calculation circuit 23 that constitute the data selection circuit 20. In this case, the memory 21 has a capacity that can store at least one frame's worth of data.

Similarly, the output of the equalizer 9 of the second system is supplied to the comparator 11 to generate binary data.
The value data is supplied to the D flip-flop 19b, and this D
The flip-flop 19b detects data in synchronization with the clock extracted from the reproduced signal by the clock extraction circuit 19, and converts it into digital data. Then, the detected digital data is supplied to the demodulation circuit 13, and the digital data demodulated by the demodulation circuit 13 is supplied to the memory 22 and the syndrome calculation circuit 24 that constitute the data selection circuit 20. In this case, the memory 22 also has a capacity capable of storing at least one frame's worth of data.

[0018] Then, the syndrome calculation circuits 23 and 2
4, a syndrome calculation is performed using the C1 parity from the outputs of the demodulation circuits 12 and 13, and a syndrome calculation is performed using the C2 parity of one frame of data stored in the memories 21 and 22. Then, the calculation results of both syndrome calculation circuits 23 and 24 are sent to the error detection circuit 2.
5, the error detection circuit 25 determines the error occurrence situation from the syndrome calculation result, and supplies data regarding the determined error occurrence situation to the microcomputer 26. This microcomputer 26 performs various controls related to error correction processing of reproduced data.

The data output directly from the demodulation circuits 12 and 13 is supplied to one and the other fixed contacts of the changeover switch 27, and the data selected under the control of the microcomputer 26 is supplied to the memory 29. do. This changeover switch 27 is used to select reproduced data that has been detected as good in the syndrome calculation using C1 parity.

Furthermore, the data stored in the memories 21 and 22 is supplied to one and the other fixed contacts of the changeover switch 28, and the data on the side selected under the control of the microcomputer 26 is supplied to the memory 29. This changeover switch 28 is a syndrome calculation using C2 parity.
This is for selecting playback data detected as good. Note that data selection control by the microcomputer 26 is performed based on the flowchart of FIG. 3, which will be described later.

Then, the syndrome arithmetic circuit 30 uses one frame worth of data stored in the memory 29 to calculate
A syndrome calculation using C1 parity and a syndrome calculation using C2 parity are performed. Then, the data stored in the memory 29 is supplied to the digital signal processing circuit 14 via the terminal 31, and the syndrome calculation circuit 3
Data such as the calculation result at 0 is supplied to the digital signal processing circuit 14 via the terminal 32. Then, the digital signal processing circuit 14 performs error correction of the reproduced data supplied from the memory 29 side based on the syndrome calculation result supplied from the syndrome calculation circuit 30 side. Here, the procedure for selecting data under the control of the microcomputer 26 will be explained with reference to the flowchart in FIG. Syndrome operation using C1 parity with equalized data is
Performed by syndrome calculation circuits 23 and 24 (step 10)
1). At this time, the microcomputer 26 sets n=1 as an initial value (step 102). and,
Based on the calculation result in step 101, the error occurrence status of the data of both systems is determined (step 103). In this judgment, an and cn are the C of the data of the two systems.
The data string in the direction in which 1 parity is added is shown. That is,
As shown in FIG. 4, data D1 processed by the first system equalizer 8 includes data sequences a1, a2 in a direction that can be checked by C1 parity, and data in a direction that can be checked by C2 parity. Column b1,
Suppose that it is composed of b2... Also, as data D2 processed by the equalizer 9 of the second system, C
1 data string c1 in the direction that can be checked by parity
, c2 . . . and data strings d1, d2 . . . in directions that can be checked by C2 parity. In the following description, in order to simplify the description, it is assumed that each direction is composed of three data strings.

[0022] Then, the data D1 of the first and second systems
and D2, the data string a1, a2, etc., which can be checked by C1 parity, and c1, c2, etc., is selected with the changeover switch 27, which has no error by checking C1 parity (step 104).
, to be written into the memory 29. That is, when there is no error in the data string of the first system of data D1, the data string of the first system of data D1 is written into the memory 29 (step 105), and the data string of the second system of data D2 is written. When there is no error, the data D2 of this second system
write the data string in the memory 29 (step 10
6). Then, when writing of one data string is completed,
The value obtained by adding 1 to the initial value 1 is set as n (step 107
). Then, it is determined whether the value of n exceeds 3 (step 108), and the writing of each data string of any system in steps 104 to 107 is repeated until the value of n exceeds 3. When the selection of one frame of data by the C1 parity check is completed and the selected data D3 (see FIG. 4) is obtained, the process moves to the next step.

In the next step (step 109), it is determined whether the data series written to the memory 29 by the above selection is completely error-free data by checking the C1 parity. At this time, when it is determined that all the data is error-free, it is assumed that complete data of this frame has been obtained, and one frame of data written in the memory 29 at this time is sent from the terminal 31 to the digital signal processing circuit 14. data selection in this frame is completed (step 128). Also, if there is an error in any data series, the equalizer 8 of the first system
Equalized data and second system equalizer 9
The syndrome calculation circuits 23 and 24 perform syndrome calculation using C2 parity with the equalized data (step 110). At this time, the microcomputer 26 sets n=1 as an initial value (step 1
11). Then, based on the calculation result in step 110, the error occurrence status of the data in both systems is determined (step 11
2). Then, among the data D1 and D2 of the first and second systems, the data strings b1, b2, and d1, d2, which can be checked by C2 parity, are
1. The data string with no error after the parity check is selected by the changeover switch 28 (step 113) and written into the memory 29. That is, the data D of the first system
When there is no error in the data string of data D1 of this first system, the data string of data D1 of this first system is written to the memory 29 (step 114), and when there is no error in the data string of data D2 of the second system, this data string of data D1 of this first system is written into the memory 29 (step 114). The data string of data D2 of system 2 is written into the memory 29 (step 115).
). When writing of one data string is completed, the value obtained by adding 1 to the initial value 1 is set to n (step 116).
. Then, it is determined whether the value of n exceeds 3 (step 117), and the writing of each data string of any system in steps 113 to 116 is repeated until the value of n exceeds 3. When the selection of one frame of data by the C2 parity check is completed and the selected data D4 (see FIG. 4) is obtained, the process moves to the next step.

[0024] Then, the next step (step 118)
Now, it is determined whether or not the data series written to the memory 29 by the above selection is completely error-free data by checking the C2 parity. At this time, if it is determined that the data is free of errors, it is assumed that complete data for this frame has been obtained, and at this time the memory 2
One frame of data written in 9 is supplied from the terminal 31 to the digital signal processing circuit 14, and data selection for this frame is completed (step 128). Furthermore, when there is an error in any data series, the error occurrence status of the data written in the memory 29 is determined.

That is, first, by processing within the memory 29,
The data D3 selected based on the parity C1 written in the memory 29 and the data D4 selected based on the parity C2 are combined to generate synthetic data D5 (see FIG. 4).
is created, and the location where the error occurs is detected from this composite data D5. As part of this detection work, first data D5
The values of K and L indicating the address position of are set to 1 (step 119). Then, starting from the addresses (A1, B1), a parity check is performed to determine whether the data is error-free (step 120). If there is no error in the data at the corresponding address, the data at this address is determined to be correct data (step 121). Furthermore, if there is no error in the data at the corresponding address, an error flag is set at this address (step 122).

[0026] Then, the address value K of one data string A
It is determined whether or not exceeds 3 (step 123), and if it does not exceed 3, 1 is added to the value of K (step 124).
, the process returns to the determination at step 120. Then, when the address value K exceeds 3, the address value K of the data string A is set to 1 (step 125), and in this state, it is determined whether the address value L of the other data string B exceeds 3 ( In step 126), if the value does not exceed 3, the value obtained by adding 1 to the value of L is set as the address value L (step 127), and the process returns to step 120.

By changing the address values in this way, it is determined whether or not there is an error in all the addresses of the data D5, and the data D5 is supplied from the terminal 31 to the digital signal processing circuit 14, and the data regarding the error flag is also transmitted. The signal is supplied from the terminal 32 to the digital signal processing circuit 14, and the digital signal processing circuit 14 performs error correction of the data D5 based on the error flag (step 128).

Next, the reproduction processing of the digital audio signal reproduced in this manner will be explained, focusing on the operation of the data selection circuit 20.

FIG. 4 is a diagram showing an example of a data selection state in the data selection circuit 20. This FIG. 4 shows a state in which one predetermined frame of data is processed, and D1 is the first
D2 represents one frame of data processed by the equalizer 8 of the second system, and D2 represents one frame of data processed by the equalizer 9 of the second system. Here, to simplify the explanation, it is assumed that one frame of data is composed of 3 bits x 3 bits, but in reality, one frame is composed of multiple pieces of one block of data shown in Figure 5. Ru. The ○ mark added to the data string of each frame data indicates that there is no error in the syndrome operation of this bit series, and the × mark added to the data string of this bit series indicates that there is an error in the syndrome operation of this bit series. show. That is, data D1 is data string a1 and a among data strings a1, a2, a3 that can be checked by C1 parity.
3 is ○ and data string a2 is ×, data strings b1, b2, b3 that can be checked by C2 parity
Among them, data string b1 is ○, data string b2 and b
Suppose that 3 is x. Furthermore, the data D2 is a data string c1, c2, which can be checked by C1 parity.
Suppose that within c3, data string c3 is ○, data strings c1 and c2 are ×, and among data strings d1, d2, d3 that can be checked by C2 parity, data strings d1 and d2 are ○, and data string d3 is Suppose that ×. In this case, an error has occurred in the data D1 and D2 at the address indicated by a black circle.

At this time, by selecting the selector switch 27, the data string a1 that can be checked by the C1 parity
, a2, a3 and the data strings c1, c2, c3, the data string without errors is supplied to the memory 29 side and is set as data D3. That is, in the first data string, data string a1 is ○, data string c1 is x, and data string a1 is selected. Further, since the second and third data strings are determined to be in the same state by the parity check, the data string (whichever is fine) that has been determined in advance to be selected preferentially is selected. Each data string of the data D3 selected in this way is converted into A1,
Let them be A2 and A3.

Furthermore, data strings b1, b2, b3 and data strings d1, d that can be checked by C2 parity
2 and d3, the data string on the side without an error is supplied to the memory 29 side and is set as data D4. That is,
In the second data string, data string d2 is ○, data string b2 is x, and data string d2 is selected. Further, since the first and third data strings are determined to be in the same state by the parity check, the data string that has been previously determined to be selected preferentially is selected. Each data string of the data D4 selected in this way is converted to B1,
Let them be B2 and B3.

[0032] Furthermore, these data D3 and D4
If any of the data is complete without errors,
This complete data is supplied as it is to the subsequent processing circuit (digital signal processing circuit 14), but when there is an error in both data D3 and D4 as shown in FIG. 4, the data strings A1, A2, Composite data D5 is created from A3, B1, B2, and B3. This composite data D5 is created by preferentially using a data string without errors, so that data D3 and D4 are both C1 parity and have an error, and data D3 and D4 are both C2 parity and have an error. Only the data at the address that intersects with the data string is
This is the location where the error occurred. Therefore, the number of locations where errors occur is greatly reduced. That is, in the example of FIG. 4, only the address at the intersection of the data string A2 with an error in C1 parity and the data string B3 with an error in C2 parity is the location where the error occurs. It can be seen that the error occurrence state in this data D5 is improved compared to data D1 or data D2.

Further, this data D5 is sent to the digital signal processing circuit 14 together with the data regarding the error flag.
By supplying the data to the side, error correction etc. are performed and the data is made more complete.

By performing the data selection process in the data selection circuit 20 in this way, the two systems of equalizers 8 and 9
Synthesized data is obtained by using the good parts of the equalized data, resulting in a digital audio signal with few errors, and it is possible to reproduce the audio signal with good quality. That is, when the equalization characteristics of the circuit of this example are shown in FIG. 7, the characteristics of the equalizer 8 are expressed as x,
If the characteristic of the equalizer 9 is y, then the data selection circuit 20
By selecting the better output of both equalizers 8 and 9, the characteristics shown by the broken line, which is a combination of the characteristics of both equalizers 8 and 9, can be equivalently obtained. Therefore, even if the optimal equalization characteristics are partially different even for data reproduced from the same magnetic tape due to differences in the bit arrangement of the reproduced data, etc.
Data equalized with optimal equalization characteristics is always obtained, and the error rate is the lowest for all data sequences.

In this case, since the judgment of good data by syndrome calculation is made for all reproduced data immediately after the start of data reproduction, it may take some time from the start of data reproduction until the equalization characteristics become optimal. This allows playback with the lowest error rate at all times.

Furthermore, since the error rate is the lowest in all the data strings of the reproduced data, the digital signal processing circuit 1
4, correction processing such as correction of error data and interpolation of missing data is performed less frequently, and the burden on the error correction circuit and the like in the digital signal processing circuit 14 is reduced.

In each of the above-mentioned embodiments, two systems of equalizers and their peripheral circuits are prepared, the first system and the second system, and the better one of these two systems is switched. More equalizers may be prepared and switched. That is, for example, as shown in FIG. 8, six equalizers each having slightly different equalization characteristics are prepared,
The outputs of these six equalizers may be switched by syndrome calculation. By doing so, as shown by the broken line in FIG. 8, the equalization characteristics become good over a very wide range, and the error rate of reproduced data can always be kept at the lowest level.

Further, in the above embodiment, an example was explained in which the present invention was applied to a digital audio signal reproducing circuit of a VTR device, but it can also be applied to various other digital magnetic reproducing devices.

[0039]

According to the present invention, optimal data is individually selected based on the C1 parity and C2 parity of reproduced digital data, and further optimal data is selected from the individually selected data. Therefore, the optimal system of equalizer is selected for each bit, and the digital data equalized by the equalizer with the optimal characteristics is always reproduced, and the error rate is always maintained for all data strings of the reproduced data. can be kept at the lowest level.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a reproduction system circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing main parts of FIG. 1;

FIG. 3 is a flowchart diagram for explaining one embodiment.

FIG. 4 is an explanatory diagram showing an example of data selection in one embodiment.

FIG. 5 is an explanatory diagram showing a data structure of one embodiment.

FIG. 6 is an explanatory diagram showing an example of a product code.

FIG. 7 is a characteristic diagram showing the characteristics of an equalizer according to one embodiment.

FIG. 8 is a characteristic diagram showing the characteristics of an equalizer according to another embodiment.

FIG. 9 is a characteristic diagram showing conventional equalizer characteristics.

[Explanation of symbols]

2, 3 Magnetic head 8, 9 Equalizer 12, 13 Demodulation circuit 14 Digital signal processing circuit 16 Digital/analog converter 20 Data selection circuit 21, 22, 29 Memory 23, 24, 30 Syndrome calculation circuit 25 Error detection circuit 26 Microcomputer 27, 28 Changeover switch

Claims (1)

[Claims] 1. A digital data reproducing device for reproducing digital data recorded on a magnetic tape, the digital data reproducing device for reproducing the digital data product-encoded by C1 parity and C2 parity, comprising: A plurality of equalizer systems with different characteristics are prepared to equalize the digital data reproduced from the magnetic tape, and the reproduced digital data of each system equalized by the plurality of equalizers is subjected to syndrome calculation using C1 parity. , based on the syndrome calculation result by the C1 parity, selects the optimum system of reproduced digital data to form the data group of the first frame structure, and also reproduces the reproduced digital data of each system equalized by the plurality of equalizers. data, respectively, to C2
Syndrome calculation is performed using the parity, and based on the syndrome calculation result using the C2 parity, the optimum system of reproduced digital data is selected as a data group with a second frame structure, and the data with the first and second frame structures are further processed. A digital data reproducing apparatus that selects an optimal system of reproduced digital data from a group of data to form a data group of a third frame structure, and uses the data group of the third frame structure as reproduced data.