JPH04283474A - Digital data reproducing device - Google Patents

Abstract

PURPOSE:To optimize the characteristic of an equalizer at the time of reproducing magnetic-recorded digital data, and to improve the error rate of reproduction data. CONSTITUTION:The plural systems of equalizers 8 and 9 whose characteristics are changed, are prepared as the equalizers which equalize the reproduction data. Then, the syndrome arithmetic operation of the reproduction digital data of each system which are equalized by the plural equalizers 8 and 9, is operated at each bit system. Then, the reproduction digital data of the optimal system are selected at each bit system, based on this syndrome arithmetic result.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is directed to a video recording medium for recording audio signals recorded together with video signals as digital data.
The present invention relates to a digital data reproducing device suitable for application to TR.

0002

2. Description of the Related Art In digital data reproducing apparatuses such as digital VTRs, it is necessary to equalize reproduced signals using an equalizer in order to reduce the error rate of reproduced data. This reproduction equalization reduces inter-symbol interference and improves the error rate, but it largely depends on the characteristics of the recording circuit and the characteristics of the magnetic tape to be recorded. For example, when reproducing digital data recorded on a certain magnetic tape, as shown in Figure 8, when the equalizer characteristic is a, the error rate is the lowest and good reproduction is possible. The value of a changes depending on the characteristics of the magnetic tape and the recording conditions. Therefore, in order to always play with the lowest error rate, when starting playback,
It is conceivable to detect the reproduction state such as the error rate and adjust the equalizer characteristics so as to obtain the best reproduction state.

0003

[Problem to be Solved by the Invention] However, when automatically adjusting the equalizer characteristics in this way, the adjustment is made so that the error rate etc. are good during actual playback. There was an inconvenience that it took time for the equalizer characteristics to become optimal. That is, there is no equalizer that automatically optimizes its characteristics immediately upon starting playback. In addition, the optimal equalization state always changes depending on the recording signal condition, and even if the equalizer characteristic is automatically adjusted to, for example, a shown in FIG. was not necessarily obtained.

An object of the present invention is to always optimize the characteristics of an equalizer in a digital data reproducing device.

[0005]

[Means for Solving the Problems] The present invention provides an equalizer for equalizing digital data reproduced from a magnetic tape in a digital data reproducing apparatus for reproducing digital data recorded on a magnetic tape, as shown in FIG. of,
Prepare multiple systems (equalizer 8 system and equalizer 9 system) with different characteristics, and use these multiple equalizer 8 systems.
. It is designed to select data and output it.

[0006]

[Operation] By doing this, the optimal system of equalizer is selected for each bit series of reproduced digital data,
Digital data equalized by an equalizer with optimal characteristics is always reproduced.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 6. In this example, an example in which the present invention is applied to a VTR device that records and reproduces a digital audio signal in a time-sharing manner with a video signal is shown.

In FIG. 1, reference numeral 1 indicates a rotary head drum, and magnetic heads 2 and 3 are arranged on this rotary head drum 1 with an angular interval of 180° from each other. In this case, the rotary head drum 1 is rotated at a frame frequency by a servo circuit (not shown) in synchronization with the luminance signal of the recorded video signal.

A magnetic tape (not shown) is run obliquely at a constant speed over an angular range of just over 221 degrees with respect to the rotating peripheral surfaces of these magnetic heads 2 and 3, and
Video signals are recorded and played back within an angular range of 80°, approximately 3
Digital audio signals are recorded and played back within an angular range of 6°.

[0010] Here, the format of the digital audio signal recorded and played back by the VTR of this example will be explained.
The data structure is shown in Figure 3, and one block consists of 44 symbols. One symbol each is allocated to the synchronization signal, block address, ID, and parity (parity of block address and ID) in order from the beginning, and the next 36 symbols are Recorded data such as audio data or C2 parity is assigned, and C1 parity is assigned to the last four symbols. In this case, each symbol is composed of 8 bits, and when data processing is performed in the recording system circuit and the reproduction system circuit, it is processed as 8-bit parallel data.

Then, the reproduction signals of the magnetic heads 2 and 3 are supplied to reproduction amplifiers 5 and 6 via the rotary transformer 4, and the outputs of the reproduction amplifiers 5 and 6 of the respective channels are connected to a switch for switching digital audio signals. Supplied to switch 7. This changeover switch 7 allows the magnetic head 2,
3, the reproduction signal from the magnetic head 2 or 3 within this angular range is selected and output. Although not shown, another selector switch selects and outputs the signal reproduced within an angular range of about 180° for reproducing the video signal.
Supplies to the video signal reproduction circuit.

The reproduced signal output from the changeover switch 7 is then supplied to two equalizers 8 and 9. These two equalizers 8 and 9 have different equalization characteristics,
The outputs of the equalizers 8 and 9 are supplied to separate comparators 10 and 11, respectively, to convert them into binary data, and the outputs of the comparators 10 and 11 are sent to separate demodulation circuits 1 and 11, respectively.
2 and 13. In the following description, the circuit of equalizer 8 → comparator 10 → demodulation circuit 12 will be referred to as a first system, and the circuit of equalizer 9 → comparator 11 → demodulation circuit 13 will be referred to as a second system.

The demodulated signals (8-bit data) output from the demodulating circuits 12 and 13 of both systems are supplied to the data switching circuit 20. Here, the configuration of the data switching circuit 20 is shown in FIG. 2. 8-bit data from the demodulation circuit 12 of the first system is sent to separate error detection circuits 31, 32 for each bit series via a terminal 21. ‥Supply to 38. Further, the 8-bit data from the demodulation circuit 13 of the second system is sent to a separate error detection circuit 41 for each bit series via the terminal 22.
, 42...48.

The respective error detection circuits 31 to 38
, 41 to 48 perform syndrome calculations to detect errors. That is, the following syndrome S0 calculation is performed for each bit sequence of one block.

[0015]

[Math. 1] S0 =D0 +D1 +D2 + +D4
3

In this number 1, D0 to D43 are 1
Indicates the value of each bit sequence of 44 symbols in the block,
By calculating this number 1, it is determined that there is no error in the bit sequence where syndrome S0 = 0, and syndrome S
When 0 does not become 0, it is determined that an error has occurred in the corresponding bit sequence.

The error detection results of the demodulated data of the first system are supplied from the error detection circuits 31 to 38 to the error counter 23, and the error detection results of the demodulated data of the second system are supplied to the error detection circuits 41 to 38. 48 to the error counter 24, and the respective error counters 23, 24
The number of error occurrences in both systems (that is, how many series errors have occurred among the 8 series) is counted for each block.

Then, the count data of both counters 23 and 24 is supplied to an error number comparison circuit 25, and it is detected which system of demodulated data has fewer errors. The comparison results are then supplied to error evaluation circuits 51 to 58, which will be described later.

Furthermore, the error detection results of error detection circuits 31 to 38 that detect errors in the demodulated data of the first system, and the error detection results of error detection circuits 41 to 48 that detect errors of the demodulated data of the second system. The results are supplied to error evaluation circuits 51, 52, . . . 58 for each bit sequence. That is, the output of the error detection circuit 31 and the output of the error detection circuit 41 are supplied to the error evaluation circuit 51, and the error detection results of the same bit series of both systems are similarly supplied to the error evaluation circuits 52, 53, etc. do. Each of the error evaluation circuits 51 to 58 determines whether the good data in the corresponding bit sequence is the demodulated data of the first system or the demodulated data of the second system, and selects the demodulated data of the good system. Outputs a switching signal to This determination of a good system causes the data of the system without errors to be selected if there is an error in the data of only one system of the corresponding bit sequence. In addition, if there is no error in both systems or if there is an error in both systems, the error number comparison circuit 25
Based on the output of , it is determined which system has the least number of errors in one block as a whole (that is, among all eight bit sequences), and data of the system with the least number of errors is selected. Furthermore, if there is no error in both systems or if there is an error in both systems, and the number of errors occurring in one block as a whole is the same, data from either system may be selected. However, in this example,
At this time, priority is given to outputting the second system.

Here, error evaluation in the error evaluation circuits 51 to 58 will be explained with reference to the flowchart of FIG.
When data for a block is supplied and the syndrome calculation for this block is completed (step 101), each error evaluation circuit 51 to 58 determines that the error occurrence state of the corresponding bit sequence is the demodulated data of the first system. It is determined whether the demodulated data of the second system is the same (step 102). At this time, each error detection circuit 31
.about.38, based on the outputs of 41 to 48. When it is determined that they are not the same (that is, only one system has no error), it is determined whether the first system is error-free (step 103), and the first system is error-free. When , a switching signal for selecting demodulated data of the first system is output for this bit sequence (step 104). Further, when it is determined in step 103 that the first system is not error-free (that is, when the second system is error-free), this bit sequence is used to generate a switching signal that selects the demodulated data of the second system. Output (step 105). Furthermore, when it is determined in step 102 that the demodulated data of the first system and the demodulated data of the second system are the same, based on the output of the error number comparison circuit 25, the demodulated data of the second system in this block is determined. It is determined whether the number of errors occurring is less than the number of errors occurring in the first system (step 106). At this time, if the number of errors occurring in both systems is the same, it is assumed that the number of errors occurring in the second system is smaller. When it is determined that the number of errors occurring in the second system is smaller, a switching signal is output that selects the demodulated data of the second system for this bit sequence (step 105). Further, when it is determined that the number of errors occurring in the first system is smaller, a switching signal is output for selecting the demodulated data of the first system for this bit series (step 104).

[0021] Delay circuits 61 and 62 each delay the input data by one block of the 8-bit data from the demodulation circuit 12 of the first system obtained at the terminal 21.
68 to one of the fixed contacts of the changeover switches 81, 82, . . . , 88. Furthermore, a delay circuit 71 delays input data by one block for each 8-bit data from the demodulation circuit 13 of the second system obtained at the terminal 22.
, 72... 78, selector switches 81, 82...
88 to the other fixed contact side. The movable contacts of the changeover switches 81 to 88 for each bit series are switched by a switching signal output from the error evaluation circuits 51 to 58 for the corresponding bit series. Then, data obtained at the movable contacts of the changeover switches 81 to 88 for each bit series is supplied to output terminals 91, 92, . . . 98 for each bit series.

Returning to the explanation of FIG. 1 again, the 8-bit data obtained at the output terminals 91 to 98 is supplied to the digital signal processing circuit 14 as good reproduction data, and the digital signal processing circuit 14 Performs various digital processing such as axis extension, error correction using parity checking, and deinterleaving. In this case, a memory 15 is connected to the digital signal processing circuit 14, and this memory 15 is used to perform processing such as time axis expansion.

The digital data processed by the digital signal processing circuit 14 is then transferred to the digital/analog converter 1.
6, the digital/analog converter 16 converts the signal into an analog signal, the low-pass filter 17 averages the analog audio signal to produce an analog audio signal, and the analog audio signal is supplied to the audio signal output terminal 18.

Next, the reproduction processing of the digital audio signal reproduced in this manner will be explained, focusing on the operation of the data switching circuit 20.

FIG. 5 is a diagram showing an example of data switched by the data switching circuit 20. This FIG. 5 shows four predetermined blocks of data, A1 to A8 being processed by the first system circuit. Each bit sequence of 8-bit data forming each block is collectively shown, and B1 to B8 collectively represent each bit sequence of 8-bit data forming each block processed by the circuit of the second system. A circle mark added to each bit sequence indicates that there is no error in the syndrome calculation for this bit sequence, and an x mark indicates that there is an error in the syndrome calculation for this bit sequence. The output data selected and switched according to the procedure shown in the flowchart of FIG. 4 is output after being delayed by one block due to the processing time of the syndrome calculation.

In the first block shown in FIG. 5, among the data A1 to A8 processed in the first system,
There is an error in data A1, A2, A3, A7, and among data B1 to B8 processed in the second system, data B2,
There is an error in B5. At this time, in the first bit series, data A1 has an error and data B1 has no error, so data B1 without an error is selected. Similarly, the third
Even in the bit series, 5th bit series, and 7th bit series, there are errors in data A3, B5, and A7, and data B3 and A
Since there is no error in data B3, A5, and B7, data B3, A5, and B7 without errors are selected. Furthermore, in other bit series, since the error occurrence state is the same in both systems (no error or error in both systems), the number of errors occurring in one block of each system is determined. In this case, the data processed by the first system has errors in four bit sequences, and the data processed by the second system has errors in two bit sequences.
Since there are errors in two bit sequences, it is determined that the data processed by the second system has fewer errors and is better data. Therefore, for bit sequences with the same error state, the data processed in the second system (i.e., B2,
B4, B6, B8) are selected.

[0027] Similarly, in subsequent blocks, systems that have performed good data processing are determined for each bit sequence, and are sequentially output. In addition, in this example, if the number of errors in each block is the same and an error occurs in both systems, or if no error occurs in both systems, the second system is used for this bit system. The data that has been processed is selected with priority (in the case of the second and third blocks in FIG. 5).

By supplying the reproduced data selected in this manner to the digital signal processing circuit 20, the reproduced data supplied to the digital signal processing circuit 20 has the lowest error rate of all bit sequences. This results in a digital audio signal with fewer errors, allowing for good audio signal reproduction. That is, the equalization characteristics of the circuit of this example are shown in FIG. By switching, the characteristics shown by the broken line, which is a combination of the characteristics of both equalizers 8 and 9, can be obtained equivalently. Therefore, even if the optimal equalization characteristics are partially different even for data reproduced from the same magnetic tape due to differences in the bit arrangement of the reproduced data, the data will always be equalized with the optimal equalization characteristics. is obtained, and the error rate is the lowest among all bit sequences.

In this case, since the judgment of good data by syndrome calculation is made for all reproduced data immediately after the start of data reproduction, it may take some time from the start of data reproduction until the equalization characteristics become optimal. This allows playback with the lowest error rate at all times.

Furthermore, since the error rate is the lowest for all bit sequences of the reproduced data, correction processing such as correction of error data and interpolation of missing data is less likely to be performed within the digital signal processing circuit 20. The burden on the error correction circuit and the like within the digital signal processing circuit 20 is reduced.

In each of the above-mentioned embodiments, two systems of equalizers and their peripheral circuits, the first system and the second system, are prepared, and the better one of these two systems is switched. More equalizers may be prepared and switched. That is, for example, as shown in FIG. 7, six equalizers each having slightly different equalization characteristics are prepared,
The outputs of these six equalizers may be switched by syndrome calculation. By doing so, as shown by the broken line in FIG. 7, the equalization characteristics become good over a very wide range, and the error rate of reproduced data can always be kept at the lowest level.

Furthermore, the error detection using the syndrome calculation shown in the above-mentioned embodiment is merely an example, and the error detection may be performed using other calculations. In this case, in the above embodiment, the syndrome calculation is performed for each block, and switching is performed for each bit sequence in this one block period, but if the syndrome calculation can be performed in a shorter period, the equalizer may be switched in a shorter period. It's okay.

Further, in the above embodiment, an example was explained in which the present invention was applied to a digital audio signal reproducing circuit of a VTR device, but it can also be applied to various other digital magnetic reproducing devices.

[0034]

[Effects of the Invention] According to the present invention, an equalizer with optimal characteristics is selected for each bit sequence of reproduced digital data, and
Digital data equalized by an equalizer with optimal characteristics is always reproduced, and the error rate can always be kept at the lowest level for all bit sequences of the reproduced data.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a reproduction system circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing main parts of FIG. 1;

FIG. 3 is an explanatory diagram showing a data structure of one embodiment.

FIG. 4 is a flowchart diagram for explaining one embodiment.

FIG. 5 is an explanatory diagram showing an example of data switching according to an embodiment.

FIG. 6 is a characteristic diagram showing characteristics of an equalizer according to one embodiment.

FIG. 7 is a characteristic diagram showing the characteristics of an equalizer according to another embodiment.

FIG. 8 is a characteristic diagram showing conventional equalizer characteristics.

[Explanation of symbols]

2, 3 Magnetic head 8, 9 Equalizer 12, 13 Demodulation circuit 14 Digital signal processing circuit 16 Digital/analog converter 20 Data switching circuit 23, 24 Error counter 25 Error number comparison circuit 31 to 38, 41 to 48 Error detection circuit 51 ~58
Error evaluation circuits 61-68, 71-78 Delay circuits 81-88 Changeover switch

Claims (1)

[Claims] 1. In a digital data reproducing device for reproducing digital data recorded on a magnetic tape, a plurality of equalizer systems each having different characteristics are prepared for equalizing the digital data reproduced from the magnetic tape, and the plurality of equalizers are provided with different characteristics. Syndrome calculation is performed for each bit sequence of the reproduced digital data of each system equalized by the equalizer, and based on the syndrome calculation result, the optimum system of reproduced digital data for each bit sequence is selected and output. Digital data playback device.