JPH04333951A - Dma controller for processor - Google Patents

Abstract

PURPOSE:To obtain the direct memory access(DMA) controller for a processor to calculate continuous or discontinuous addresses and to transfer block data by temporarily setting the initial addresses of memories at transfer destination and transfer source and the parameter of the address calculation. CONSTITUTION:An address calculation circuit successively calculates the addresses of the transfer source memory and the transfer destination memory to perform access to the initial address of the transfer source memory in storage circuits 181a and 181c and the initial address of the transfer destination memory in storage circuits 181b and 181d based on the number of skips, block width, transfer source address index, transfer destination address index and transfer word number in storage circuits 182-186, outputs those addresses and executes DMA transfer. On the other hand, the contents of the storage circuits 181a-181d are updated with the addresses as the calculated results.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to direct memory access transfer control between memories, and for example, to a direct memory access control device for a microprocessor.

0002

[Prior Art] Fig. 4 shows, for example, IE transaction on circuits and
Systems (IEE TRANSACTION O
N CIRCUITS AND SYSTEMS) (
Vol. 36, NO. 10, Oct. 1989, p12
67-1274) is a diagram showing direct memory access (hereinafter referred to as DMA) transfer in a conventional processor, and in the figure, 10 is a processor, 2 is a
0 is an external data memory that stores image data, 100
is an execution unit 110,1 that executes calculations using a calculation unit, etc.
20 is a 2-port internal data memory, 360 is a direct memory access control device (hereinafter referred to as
DMAC), 130, 140 and 150 are an execution unit 100 and internal data memories 110 and 120, respectively.
160 and 170 are buses connecting the internal data memories 110 and 120 and the DMAC 360;
0 is a memory area for storing picture frame data of source 0 (hereinafter referred to as source 0 memory area), 2
10 is a memory area for storing picture frame data of source 1 (hereinafter referred to as source 1 memory area);
220 is a memory area (hereinafter referred to as destination memory area) that stores destination picture frame data.

Next, the operation will be explained. The data S0(i) at address i of the internal data memory 110 is transferred to the bus 130.
is transferred to the execution unit 100 via. Data S1(i) at address i in internal data memory 120 is transferred to execution unit 100 via bus 140. execution unit 1
In 00, the two input data S0(i) and S1(i
), and the calculation result is transferred to bus 150 as R(k).
The data is sent to the internal data memory 110 via the .

[0004] Also, independently of the operation of the execution unit 100, the data S1 (I+1) at address (I+1) of the source 1 memory area 210 is transferred to the DMA-
DMA transfer to internal data memory 120 via bus 160. DM from internal data memory to external data memory
A.It works. The same goes for DMA transfer, and data R(k-1) at address (k-1) of the internal data memory 110 is transferred to the DMA bus 1 independently of the operation of the execution unit 100.
When the DMAC 360 transfers image block data by DMA to the destination memory area 220 via the DMAC 70, the DMAC 360 performs serial addressing for each row as shown in FIG. 3(a) for the external data memory. Access is performed using dimensional serial addressing, and internal data memory is accessed using serial addressing.

[0005]

[Problems to be Solved by the Invention] Since the conventional microprocessor that performs DMA transfer is configured as described above, image block data is transferred from an external data memory to perform image signal processing, etc. as shown in FIG. 3(b). When DMA transfer is performed by thinning out data as sub-samples as shown in FIG. 2, data cannot be transferred all at once, and the address must be changed one word at a time before transfer. In the case of DMA transfer from the internal data memory to the external data memory, similarly to the above, it was not possible to DMA transfer the thinned out block data at once.

The present invention was made to solve the above-mentioned problems, and it is possible to perform DMA transfer of block data as shown in FIG. 3(a) independently of transfer by a program. It is an object of the present invention to obtain a microprocessor that can also perform DMA transfer of block data that has been thinned out (every other block in this example) as shown in a) and FIG. 3(c).

[0007]

[Means for Solving the Problems] A DMA control device for a microprocessor according to the present invention uses a supplied initial address value and parameters (skip number, block width, index value, and transfer word number) for performing an address operation. Based on the storage circuit to be stored and the contents stored in the storage circuit, an address for accessing the transfer source memory and an address for accessing the transfer destination memory are calculated and output, and the calculation results are stored in the storage circuit. and an address calculation circuit that updates the address.

[0008]

[Operation] DMA of the microprocessor in this invention
The control device stores an initial address for DMA transfer supplied from a microprocessor, a program, etc. and parameters for performing subsequent address calculations in a storage circuit, and the address calculation circuit calculates the transfer source memory based on the contents of this storage circuit. and the address of the transfer destination memory, data is transferred between the memories using this address, and the address stored in the storage circuit is updated with the result of the calculation.

[0009]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration in which a DMA control device according to the present invention is built into a microprocessor. In the figure, 1 is a microprocessor that is an embodiment of the present invention, 180 is a DMAC that controls direct memory access transfer, 110, 120, 130, 140, 15
0, 160, 170, 20, 200, 210, and 220 are the same as the conventional ones.

FIG. 2 shows D inside the microprocessor of FIG.
This is a diagram showing the configuration of a MAC 180, in which 180a,
180b, 180c, and 180d are storage circuits that store the initial addresses of the transfer source and destination and the address of the operation result; 182 is a storage circuit that stores the skip width of memory access; and 183 is a 1-block memory area for two-dimensional addressing. 184 and 185 are index value storage circuits used to modify the transfer source and destination addresses; 186 is a storage circuit that stores the number of words to be transferred in DMA transfer;
Reference numeral 87 is an address calculation circuit that calculates and outputs addresses for the number of transferred words according to the various parameters described above.

Next, the operation will be explained. Memory access is performed independently by execution unit 100 and DMA 180. Data S at address i of internal data memory 110
0(i) to execution unit 100 via bus 130. Data S1 at address i of internal data memory 120
(i) to execution unit 100 via bus 140. The execution unit 100 performs an operation between the two input data S0(i) and S1(i), and sends the operation result R(k) to the internal data memory 110 via the bus 150.
Send to.

In the DMA transfer by the DMAC 180, the initial address of the first line to be accessed and the initial address of the next line to be accessed of the transfer source memory are stored in the address storage circuits 181a and 181c by a program, and the initial address of the next line to be accessed is stored in the storage circuits 181b and 181d as the transfer destination. Set the initial address of the memory and the initial address of the next line to be written, set the skip width for memory block area access in the memory circuit 182, and set the block width of the block memory area for two-dimensional addressing in the memory circuit 183. and memory circuit 1
The address index values of the transfer source and transfer destination are set in 84 and 185, respectively, and the number of transfer words is set in the storage circuit 186. The address calculation circuit 187
Based on the memory values stored in 81a to 181d and 182 to 186, the addresses of the transfer source memory and transfer destination memory for the specified number of words are calculated and sequentially output, thereby creating a connection between the external memory and the internal memory. Make a transfer. Further, the transfer source address of the calculation result is stored in the storage circuit 181a or 181c, and the transfer destination address is stored in the storage circuit 181b or 181d, and the contents are updated.

Next, when performing DMA transfer of image block data whose addresses are discontinuous but regularly arranged as shown in FIG. i”, and the memory circuit 18
The first address "p" of the internal data memory of the transfer destination is set in 1b, "0" indicating "not to be used" is set in the memory circuits 181c and 181d, and the skip number "1" is set in the memory circuit 182. , set the block width "4" in the memory circuit 183, set the transfer source address index value "j-(i+3)" in the memory circuit 184, and set the transfer destination address index value "q-(p+3)" in the memory circuit 185. )", and the number of transfer words "16" is set in the storage circuit 186. The address arithmetic circuit 187 updates the address values of the memory circuits 181a and 181b according to the parameter values set in each memory circuit, and sequentially updates the address values of "i, i+1, i+2,
Then, when i+3 is output, the address index value of the storage circuit 184 is added to i+3, and "j, j+2, j+3" is output, and similarly j+3 is output.
by adding the address index value to “k,…,k+
3,l,l+1,l+2,...,l+3", the transfer source address for 16 words is output.The transfer destination address is also calculated in the same way as the transfer source address, and "p , p+1, p+2, p+3, q,...,
s+2, s+3'' and performs DMA transfer.

Furthermore, when data of image blocks arranged as shown in FIG. 3(b) is transferred by DMA, the storage circuit 18
1a is set to "i", the storage circuit 181b is set to "p", the storage circuit 181c is set to "j+1", and the storage circuit 18
1d is set to "q+1", the memory circuit 182 is set to the skip number "2", and the memory circuit 183 is set to the block width "4".
, set the transfer source address index value "k-(i+2)" in the memory circuit 184, set the transfer destination address index value "r-(p+2)" in the memory circuit 185, and set the transfer source address index value "r-(p+2)" in the memory circuit 186. Set the number of transfer words to “8”. The address calculation circuit 187 calculates addresses based on the parameters set in these storage circuits, and
While updating the address values of 81a, 181b, 181c and 181d, the transfer source address is sequentially changed to “i, i+2,
i+1, i+3, ..., l+1, l+3", output the transfer destination address as "p, p+2, q+1, q+3, ..." and
Perform MA transfer.

Furthermore, when data of image blocks arranged as shown in FIG. 3(c) is transferred by DMA, the storage circuit 18
1a as the initial address, and the memory circuit 181b.
"p" in the storage circuit 181c, "0" indicating "not to be used" or "j" at the start address of the next line of the transfer destination.
"0" indicating "not used" in the memory circuit 181d.
” or the next line start address of the transfer destination “q”, set “2” in the memory circuit 182, set “4” in the memory circuit 183, and store the transfer source address index value in the memory circuit 184. If "0" is set in the circuit 181c, "j-(i+2)" is set, and if "j" is set, "
k-(i+2)", and if the address index value of the transfer destination in the storage circuit 185 is set to "0" in 181d, "q-(p+2)" is set, and if "q" is set, "r" is set. -(p+2)" and set the number of transfer words "8" in the memory circuit 186, the address calculation circuit 187 allows the memory circuits 181a, 181b, 181c
While updating the address value of 181d, the transfer source address is sequentially changed to “i, i+2, j, j+2, ..., l, l+2.
”, and the forwarding address is “p, p+2, q, q+2, …,
s, s+2'' and performs DMA transfer.

Note that DMA transfer involves transferring from source 0 picture frame 200 or source 1 picture frame 210 to internal data memory 110 or 120 via DMAC 180 and DMA-bus 160;
Some data is transferred from the internal data memory 110 or 120 via the DMA bus 170 to the destination picture frame 220 via the DMAC 180.

In the above embodiment, the configuration of the DMAC 180 is as shown in FIG. 2, but it has two storage circuits each for the transfer source address and transfer destination address, and has a plurality of transfer source indexes and a plurality of transfer destination indexes. It's okay. For example, if you have two of each, in Figure 3(b), the transfer source indexes are "j+1-(i+2)" and "
k-(j+3)", and the destination index is "q+1(p+2)" and "r-(q+3)".
Set seeds.

It is also possible to have two storage circuits each for the transfer source address and transfer destination address, and set the frame width of the external memory instead of the transfer source index and transfer destination index. For example, 100 in a horizontal row
When handling a word memory frame, the block width is set to "3" and the transfer source address is set to "i" in Figure 3(b).
”, “j+1”, and address calculation circuit 18
7, the first line is “i” for the block width, “i+2”
”, and the second line outputs the address of “j+
1", "j+3", and the third line is the value obtained by subtracting (block width - 1) from twice the set frame width "100" (2 lines), in this example, 100 x 2 - (3-1
)=198 to “i+2” to get “k”, then “
Similarly, in the fourth line, output 1 to “j+3”.
98 is added and "l+1" and "l+3" are output.

The DMAC 180 is shown in FIGS. 3(a) and 3(b).
) or continuous memory data as shown in Fig. 3(c) or discrete memory data (not just every other, every second, every third, etc. in two-dimensionally arranged memory blocks) can be sequentially accessed. The DM of the above embodiment or other embodiments may be configured to output an address as shown in FIG.
It is not limited to the configuration of AC.

Further, the external data memory 20 is conveniently stored as a source 0 picture frame 200, a source picture 1 frame 210, and a destination picture frame 22.
However, the memory areas of the respective picture frames may overlap.

Furthermore, in the above embodiment, since there is a correlation between the addressing of the internal memory of the microprocessor and the addressing of the external memory, for example, when addressing the internal memory in the format shown in FIG. Addressing of the external memory is performed in the format shown in FIG. 3(a). However, it is not necessarily necessary to unify the input/output addressing format; for example, addressing the external memory input by DMA transfer may be performed at intervals as shown in Figure 3(b), and the input data may be addressed as shown in Figure 3(a). Thus, one line may be sequentially output to the internal memory in a block form so that addressing is continuous, and the limitation is not limited by the relationship between addressing on the input side and addressing on the output side.

[0022]

[Effects of the Invention] As described above, according to the present invention, the DMA controller inside the microprocessor is configured to store parameters from a program and calculate a transfer source address and a transfer destination address based on the parameters. Therefore, sub-sampling of block data can be performed and DMA transfer can be performed by setting parameters once.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a microprocessor according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a DMAC in Embodiment 1 of the present invention.

FIG. 3 is a diagram showing a pixel arrangement on a memory to be accessed in Embodiment 1 of the present invention.

FIG. 4 is a diagram showing the configuration of a conventional microprocessor.

[Explanation of symbols]

1 Microprocessor 20 of the present invention External data memory 100 Execution units 110, 120 Internal data memories 130, 140, 150 Buses 160, 170 DMA-bus 180 DMA controllers 181a to 181d Storage circuit 182 for latching addresses Memory for latching the number of skips circuit 183
Memory circuits 184 and 185 that latch the block width Memory circuit 186 that latches the address index value Memory circuit 187 that latches the number of transferred words
Address calculation circuit 200 Source 0 picture frame 210 Source 1 picture frame

Claims (1)

[Claims] 1. A direct memory access control device for a processor that transfers data between memories, comprising: a memory circuit that stores a supplied initial address and parameters for calculating the address; and a memory circuit that stores a supplied initial address and parameters for calculating the address; An address calculation circuit that calculates and outputs an address for accessing a transfer source memory and an address for accessing a transfer destination memory, and updates an address stored in the storage circuit with the calculated address. Direct memory access control device for processors.